Hi,

I created a patch that will (hopefully) increase the performance for TLB
miss handling.

- enlarge the distance between rsm psr.dt and srlz (the movl do not need
data access)

- let the processor check for the case of page not present (because for
useable systems the common case is that the page is present, so optimize
for that and drop the conditional branch)

- let the processor also check for privilege level because it's very
very rare

The second modification will result (rarely) in the insertion of an
unused TLB entry. But this entry will be overwritten with the useable
entry when the page is swapped in. The time needed for the insertion of
the TLB entry and the additional interruption will be neglectible
compared to the time needed for swapping in.

Since I'am waiting for Itanium 2 (Itanium 1 does not have any relevance
nowadays) I have done no performance testing. All Itanium 2 owners are
invited for testing.

Please tell me your comments.

Christian