This patch is against a tree created by cloning Bjorn's BK
tree on May 20, and applying his error logging patch (posted
to ia64 list on May 8th ... since I'm sure he's going to
include it as it is so good).

The underlying algorithm is to save information about what
each of the ITR/DTR registers is mapping, then at MCA time
we can purge the whole TLB (TC and TR) and reload the TR
registers before jumping to virtual mode.

DTR[2] gets some special treatment as we didn't want to touch
the context switch path to update the saved area on potentially
every context switch, so it gets reconstructed from ar.k4.

There is a major cleanup of the processor save/restore code
in mca_asm.S (which apparently was written before silicon, it
was using some out-of-date spec for control registers).

There's a minor cleanup in the logging code to only print
implemented registers (this just needs to be moved over to
Bjorn's new "salinfo" tool when all the print code gets
deleted from the kernel).


-Tony Luck.  With special thanks to Jenna Hall (who started work
on this, oh so long ago) and Fenghua Yu (who ported to 2.4.21
and tidied up my messes).

2.5 version needs some more work to co-exist with the kernel
relocation patch