From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Choi, Youngsoo" Date: Wed, 16 Jul 2003 15:57:35 +0000 Subject: RE: IA-64 instruction latencies Message-Id: List-Id: References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linux-ia64@vger.kernel.org Hi, For Itanium2 http://www.intel.com/design/itanium2/manuals/251110.htm page 17 For Itanium http://www.intel.com/design/itanium/downloads/245474.htm page 9-12 For all the manuals, http://www.intel.com/design/itanium/manuals.htm For more information about optimization, there is a document, "Introduction to Microarchitectural Optimization for Itanium 2 Processors", available on the Intel Developer Services web site http://cedar.intel.com/cgi-bin/ids.dll/topic.jsp?catCode=BMC ------- Youngsoo Choi EPD Architecture Team Tel.: (408) 653-8970 Intel Corporation Loc.: SC12/3rd/Pole L2 -----Original Message----- From: CH Gowri Kumar [mailto:gkumar@csa.iisc.ernet.in] Sent: Wednesday, July 16, 2003 8:31 AM To: linux-ia64@vger.kernel.org Subject: IA-64 instruction latencies Hello All, I am unable to find a document which gives the latencies of the different instructions of Itanium instruction set. Can anyone point me to such a document? Regards, Gowri Kumar - To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html