After some investigation I discovered that a "flushrs" at the start of my
signal handler cured the problem.

Looking at "arch/ia64/kernel/gate.S" revealed that a "cover" is used to
get the registers onto the backing store (commented as such several
times), but by my understanding there is enough scope from the instruction
description that they may be cached. Therefore, should gate.S include a
"flushrs" as well or, for performance reasons be left for the user to
decide?