From: David Mosberger <davidm@napali.hpl.hp.com>
To: linux-ia64@vger.kernel.org
Subject: Re: [RFC] Endianness and signals
Date: Tue, 21 Oct 2003 00:10:35 +0000 [thread overview]
Message-ID: <marc-linux-ia64-106669550812841@msgid-missing> (raw)
In-Reply-To: <marc-linux-ia64-106669369711349@msgid-missing>
>>>>> On Tue, 21 Oct 2003 00:42:09 +0100, "R. Lake" <rich@lakes.plus.com> said:
Richard> Further to my study of IA64 architecture, and to an extent
Richard> the linux kernel, I wonder if the gate page ought to
Richard> default to little endian upon issue of a signal. i.e. "rum
Richard> 2" prior to any loads/stores? It would seem to me that in
Richard> the current state, if the process were preempted
Richard> immediately after a memory access (fundamentally) in
Richard> big-endian mode the signal context would likely execute in
Richard> the wrong endianness and fail. - It's my understanding
Richard> that the user mask is preserved in the context switch.
I don't think the psABI requires twiddling the PSR.be bit on signal
delivery (though it probably also does not disallow it). The thing
is, if you have an applications that's completely big-endian, you'd
probably NOT want to clear PSR.be on a signal. On the other hand, if
you just have one or two routines which turn on PSR.be, then clearing
the bit is clearly advantageous (e.g., would avoid sigprocmask()
calls). But given that the current kernel behavior has existed for a
long time, I'm not sure it's a good idea to change the behavior now
(it's not like you _can't_ have big-endian code at the moment).
--david
next prev parent reply other threads:[~2003-10-21 0:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-10-20 23:42 [RFC] Endianness and signals R. Lake
2003-10-21 0:10 ` David Mosberger [this message]
2003-10-21 20:37 ` Cary Coutant
2003-10-21 20:56 ` David Mosberger
2003-10-21 21:57 ` Cary Coutant
2003-10-21 22:24 ` David Mosberger
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