RE: [RFC] Better MCA recovery on IPF

["Alberto Munoz" <amunoz@vmware.com>]

> > Hi,
> > 
> > I just wondered if a speculative load hitting a cache or memory
> > error does cause an exception on IA64 ? 
> 
> I dont think a speculative load should cause a problem - at 
> least until 
> code tries to consume the data by transfering it to a 
> processor register.

If you are doing a read (which is what a speculative load will be
generating), the error will be generated by whatever part of the logic that
detects it. You cannot possible send poisoned data through a memory bus and a
system bus (at least not the Intel system buses I am familiar with) without
having some of the error checking logic (ECC or parity) complaining about it
(this means generating an MCA).

> As I understand the cpu architecture, an error that occurs 
> reading data
> will result in a poisoned cache line being delivered to the 
> cpu cache. 
> The poisoned cache line can stay in the cache forever. No MCA error is
> reported until the data is actually consumed by tranfering 
> the data from 
> cache to a cpu register. 

The problem is that the cache error checking logic has no way of knowing that
the data it is about to supply to some register is going to be used for a
speculative operation. The cache logic is pretty far away (in processor
terms) from the decoding logic.

Bert Munoz

> This requires some support from the chipset. Some chipsets dont fully
> support this error model.
> 
> 
> 
> 
> -- 
> Thanks
> 
> Jack Steiner (steiner@sgi.com)          651-683-5302
> Principal Engineer                      SGI - Silicon Graphics, Inc.
> 
> 
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