From: Damien Le Moal <dlemoal@kernel.org>
To: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>,
cassel@kernel.org, richardcochran@gmail.com,
piyush.mehta@xilinx.com, axboe@kernel.dk, michal.simek@amd.com
Cc: linux-ide@vger.kernel.org, linux-kernel@vger.kernel.org,
git@amd.com, Piyush Mehta <piyush.mehta@amd.com>
Subject: Re: [PATCH 1/2] ata: ahci_ceva: fix error handling for Xilinx GT PHY support
Date: Mon, 22 Jan 2024 19:28:53 +0900 [thread overview]
Message-ID: <069e3e67-fd93-4af4-905e-d4087a5b3153@kernel.org> (raw)
In-Reply-To: <1705604904-471889-2-git-send-email-radhey.shyam.pandey@amd.com>
On 1/19/24 04:08, Radhey Shyam Pandey wrote:
> From: Piyush Mehta <piyush.mehta@amd.com>
>
> Platform clock and phy error resources are not cleaned up in Xilinx GT PHY
> error path. To fix introduce error label for ahci_platform_disable_clks and
> phy_power_off/exit and call them in error path. No functional change.
>
> Fixes: 9a9d3abe24bb ("ata: ahci: ceva: Update the driver to support xilinx GT phy")
> Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> ---
> ---
Your patch format is strange... There is one too many "---" line here.
Other than that, looks OK to me.
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
--
Damien Le Moal
Western Digital Research
next prev parent reply other threads:[~2024-01-22 10:28 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-18 19:08 [PATCH 0/2] ata: ahci_ceva: fix xilinx GT PHY support Radhey Shyam Pandey
2024-01-18 19:08 ` [PATCH 1/2] ata: ahci_ceva: fix error handling for Xilinx " Radhey Shyam Pandey
2024-01-22 7:39 ` Dan Carpenter
2024-01-22 10:28 ` Damien Le Moal [this message]
2024-01-22 13:02 ` Niklas Cassel
2024-02-07 18:28 ` Pandey, Radhey Shyam
2024-02-07 20:42 ` Niklas Cassel
2024-01-18 19:08 ` [PATCH 2/2] ata: ahci_ceva: add missing enable regulator API " Radhey Shyam Pandey
2024-01-22 10:29 ` Damien Le Moal
2024-01-22 13:28 ` Niklas Cassel
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