SiS 180 pata

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* SiS 180 pata
@ 2004-07-05 10:53 Nicola
  2004-07-05 13:43 ` Jeff Garzik
  0 siblings, 1 reply; 19+ messages in thread
From: Nicola @ 2004-07-05 10:53 UTC (permalink / raw)
  To: uwe.koziolek; +Cc: linux-ide

Dear Sirs,
I have a problem with my SiS 180 controller sata/pata, running
under Fedora Core 2 x86_64, with both kernels 2.6.5 and 2.6.6.

I own a brand new mb for my AMD3200+, Jetway S755max
with a Sis chipset 755, southbridge 963 + Sis 180.

The supplementary Sis 180 chipset controls another parallel ata port
(2 channels) and two sata ports. I'm not interested in sata ports
for the time being.

I would like to use my Pioneer dvd recorder on the
third parallel ide, controlled by the sis 180 chipset.
It is recognised from the bios and it works under xp, so it has to be
a software isse.
(the same happens if I attach a 40G drive).

However the drive is not detected by linux:

libata version 1.02 loaded.
ata1: SATA max UDMA/133 cmd 0xD800 ctl 0xDC02 bmdma 0xE800 irq 19
ata2: SATA max UDMA/133 cmd 0xE000 ctl 0xE402 bmdma 0xE808 irq 19
ata1: no device found (phy stat 00000000)
scsi1 : sata_sis
ata2: no device found (phy stat 00000000)
scsi2 : sata_sis

I have tried to mount it under every possible hd device, as well as sd one.
I have also read /usr/src/linux/Documentation/ide.txt and tried with various
ide2=... combinations at boot time, without success.

Now I'm quite confused. Does the sata_sis module covers only the sata side 
of the sis 180 chipset?

I would highly appreciate any help you could give me. I really
need this interface working.

Thanks a lot in advance

Nicola

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-05 10:53 SiS 180 pata Nicola
@ 2004-07-05 13:43 ` Jeff Garzik
  2004-07-05 14:03   ` Nicola
  0 siblings, 1 reply; 19+ messages in thread
From: Jeff Garzik @ 2004-07-05 13:43 UTC (permalink / raw)
  To: Nicola; +Cc: uwe.koziolek, linux-ide

Nicola wrote:
> I have tried to mount it under every possible hd device, as well as sd one.
> I have also read /usr/src/linux/Documentation/ide.txt and tried with various
> ide2=... combinations at boot time, without success.
> 
> 
> Now I'm quite confused. Does the sata_sis module covers only the sata side 

Correct...   as the name implies.

You need to add PCI ids to the SIS IDE driver.

	Jeff




^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-05 13:43 ` Jeff Garzik
@ 2004-07-05 14:03   ` Nicola
  2004-07-05 20:31     ` Uwe Koziolek
  0 siblings, 1 reply; 19+ messages in thread
From: Nicola @ 2004-07-05 14:03 UTC (permalink / raw)
  To: Jeff Garzik; +Cc: uwe.koziolek, linux-ide

On Monday 05 July 2004 15:43, you wrote:

> > Now I'm quite confused. Does the sata_sis module covers only the sata
> > side
>
> Correct...   as the name implies.
>
> You need to add PCI ids to the SIS IDE driver.
>
> 	Jeff
I've added the id few days ago (not yet approved):
http://pciids.sourceforge.net/iii/?i=1039

should be something like:
{ "SiS180",     PCI_DEVICE_ID_SI_180,   ATA_133   },
inside sis5513.c

May I help somehow in developping/testing the pata driver?
Please let me know

Thank you
Nicola

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-05 14:03   ` Nicola
@ 2004-07-05 20:31     ` Uwe Koziolek
  2004-07-05 20:55       ` Jeff Garzik
  2004-07-05 21:05       ` Nicola
  0 siblings, 2 replies; 19+ messages in thread
From: Uwe Koziolek @ 2004-07-05 20:31 UTC (permalink / raw)
  To: Nicola; +Cc: Jeff Garzik, linux-ide

Hello Nicola,

please can you provide the output of lspci -vvxxx

> should be something like:
> { "SiS180",     PCI_DEVICE_ID_SI_180,   ATA_133   },
> inside sis5513.c
> 
if the pata ports on the Sis180 a using the same ID 180, then we have a
conflict. We have 2 drivers for SIS 180.

I expect a different way in the SiS180 chip: a different ID
The output of lspci may helps hopefully.

But maybe i do not answer before next monday.

Uwe




^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-05 20:31     ` Uwe Koziolek
@ 2004-07-05 20:55       ` Jeff Garzik
  2004-07-05 21:15         ` Nicola
  2004-07-05 21:05       ` Nicola
  1 sibling, 1 reply; 19+ messages in thread
From: Jeff Garzik @ 2004-07-05 20:55 UTC (permalink / raw)
  To: Uwe Koziolek; +Cc: Nicola, linux-ide

Uwe Koziolek wrote:
> Hello Nicola,
> 
> please can you provide the output of lspci -vvxxx
> 
> 
>>should be something like:
>>{ "SiS180",     PCI_DEVICE_ID_SI_180,   ATA_133   },
>>inside sis5513.c
>>
> 
> if the pata ports on the Sis180 a using the same ID 180, then we have a
> conflict. We have 2 drivers for SIS 180.
> 
> I expect a different way in the SiS180 chip: a different ID
> The output of lspci may helps hopefully.
> 
> But maybe i do not answer before next monday.

If it uses the same PCI id, I can work on that, on the libata side.

	Jeff




^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-05 20:55       ` Jeff Garzik
@ 2004-07-05 21:15         ` Nicola
  0 siblings, 0 replies; 19+ messages in thread
From: Nicola @ 2004-07-05 21:15 UTC (permalink / raw)
  To: Jeff Garzik; +Cc: Uwe Koziolek, linux-ide

[-- Attachment #1: Type: text/plain, Size: 837 bytes --]

On Monday 05 July 2004 22:55, Jeff Garzik wrote:
> Uwe Koziolek wrote:
> > Hello Nicola,
> >
> > please can you provide the output of lspci -vvxxx

> If it uses the same PCI id, I can work on that, on the libata side.
>
> 	Jeff
Here is the complete one, if it is of any usage.
I have just received a mail from another guy with the same mb. He states he's 
unable to install FC2 on his sata disk, which is recognised by the bios, but 
not by linux:
libata version 1.02 loaded.
ata1: SATA max UDMA/133 cmd 0xDC00 ctl 0xE002 bmdma 0xEC00 irq 19
ata2: SATA max UDMA/133 cmd 0xE400 ctl 0xE802 bmdma 0xEC08 irq 19
ata1: no device found (phy stat 85101e00)
ata1: thread exiting
scsi1 : sata_sis
ata2: no device found (phy stat 00e30304)
ata2: thread exiting
scsi2 : sata_sis

Please find attached the full lspci -vvxxx.

Thanks a lot 
Nicola



[-- Attachment #2: lspci.txt --]
[-- Type: text/plain, Size: 25565 bytes --]

00:00.0 Host bridge: Silicon Integrated Systems [SiS] 755 Host (rev 01)
	Subsystem: Silicon Integrated Systems [SiS] 755 Host
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
	Latency: 32
	Region 0: Memory at e0000000 (32-bit, non-prefetchable)
	Capabilities: [a0] AGP version 3.0
		Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4
		Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none>
	Capabilities: [d0] #08 [0120]
	Capabilities: [f0] #08 [8000]
00: 39 10 55 07 07 00 10 22 01 00 00 06 00 20 00 00
10: 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 39 10 55 07
30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 00 00
40: 16 00 74 17 0c ff 90 e0 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 0c 80 00 00 00 00 00 00 00 00 00 00 00 00 21 10
80: 00 00 00 00 00 00 14 c8 00 00 00 10 00 03 00 02
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 d0 30 00 07 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 30 0f 01 00 00 00 00 00 00 00 00 00
c0: 00 08 18 00 02 88 45 28 00 00 00 00 00 01 00 00
d0: 08 f0 20 01 60 00 11 11 d0 00 77 77 22 05 35 00
e0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 08 00 00 80 44 01 99 f8 00 00 00 00 77 77 33 00

00:01.0 PCI bridge: Silicon Integrated Systems [SiS] SG86C202 (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 99
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=32
	Memory behind bridge: e6000000-e8ffffff
	Prefetchable memory behind bridge: e4000000-e5ffffff
	BridgeCtl: Parity- SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B-
00: 39 10 02 00 07 01 20 02 00 00 04 06 00 63 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 20 f0 00 20 22
20: 00 e6 f0 e8 00 e4 f0 e5 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0e 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 02 40 00 00 09 00 80 00 08 00 00 00 00 00 00 00
60: 30 02 60 60 aa 10 00 00 23 23 98 15 00 00 08 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 15 18 15 18

00:02.0 ISA bridge: Silicon Integrated Systems [SiS] SiS963 [MuTIOL Media IO] (rev 25)
	Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
00: 39 10 63 09 0f 00 00 02 25 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: d2 03 07 0b 0c 40 3d dd 10 00 00 00 11 20 04 03
50: 11 28 02 01 60 0b 20 0b a9 04 12 00 d2 00 00 00
60: 0c 0b 80 09 ff c1 0a 12 09 80 00 46 97 00 02 14
70: 05 00 ff ff 00 10 00 2e 20 00 20 80 f2 00 00 40
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 00 40 00 00 00 00 0c 80 00 00 00 00 00 41
d0: 20 0c 00 01 22 62 32 00 85 00 04 2a aa aa aa aa
e0: 40 00 00 f8 42 20 44 00 bd 42 00 00 00 00 00 00
f0: 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.1 SMBus: Silicon Integrated Systems [SiS]: Unknown device 0016
	Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Interrupt: pin B routed to IRQ 17
	Region 4: I/O ports at 10c0 [size=32]
00: 39 10 16 00 01 00 80 02 00 00 05 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: c1 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00
40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.5 IDE interface: Silicon Integrated Systems [SiS] 5513 [IDE] (prog-if 80 [Master])
	Subsystem: Silicon Integrated Systems [SiS] SiS5513 EIDE Controller (A,B step)
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 128
	Region 4: I/O ports at 4000 [size=16]
00: 39 10 13 55 05 00 00 02 00 80 01 01 00 80 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 40 00 00 00 00 00 00 00 00 00 00 39 10 13 55
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 06 00 00 00 00 00
50: f2 07 f2 07 2a 96 d5 c0 00 00 00 00 00 00 00 00
60: fb aa fb aa 00 00 00 00 00 00 00 00 00 00 00 00
70: 1e 32 09 05 56 23 06 04 1e 32 09 05 00 60 1c 1e
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.7 Multimedia audio controller: Silicon Integrated Systems [SiS] Sound Controller (rev a0)
	Subsystem: Unknown device 16f3:473d
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (13000ns min, 2750ns max)
	Interrupt: pin C routed to IRQ 18
	Region 0: I/O ports at c000
	Region 1: I/O ports at c400 [size=128]
	Capabilities: [48] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=55mA PME(D0-,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 39 10 12 70 05 00 90 02 a0 00 01 04 00 20 00 00
10: 01 c0 00 00 01 c4 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 f3 16 3d 47
30: 00 00 00 00 48 00 00 00 00 00 00 00 0b 03 34 0b
40: 04 00 00 00 00 00 00 00 01 00 42 c6 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:03.0 USB Controller: Silicon Integrated Systems [SiS] USB 1.0 Controller (rev 0f) (prog-if 10 [OHCI])
	Subsystem: Silicon Integrated Systems [SiS] USB 1.0 Controller
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (20000ns max), Cache Line Size 08
	Interrupt: pin A routed to IRQ 20
	Region 0: Memory at ea003000 (32-bit, non-prefetchable)
00: 39 10 01 70 07 00 80 02 0f 10 03 0c 08 20 80 00
10: 00 30 00 ea 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 39 10 01 70
30: 00 00 00 00 00 00 00 00 00 00 00 00 0c 01 00 50
40: 00 00 00 00 5c ae 01 00 0f 02 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 c2 c9
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:03.1 USB Controller: Silicon Integrated Systems [SiS] USB 1.0 Controller (rev 0f) (prog-if 10 [OHCI])
	Subsystem: Silicon Integrated Systems [SiS] USB 1.0 Controller
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (20000ns max), Cache Line Size 08
	Interrupt: pin B routed to IRQ 21
	Region 0: Memory at ea000000 (32-bit, non-prefetchable)
00: 39 10 01 70 07 00 80 02 0f 10 03 0c 08 20 00 00
10: 00 00 00 ea 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 39 10 01 70
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 02 00 50
40: 00 00 00 00 5c ae 01 00 0f 02 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 c2 c9
e0: 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:03.3 USB Controller: Silicon Integrated Systems [SiS] USB 2.0 Controller (prog-if 20 [EHCI])
	Subsystem: Silicon Integrated Systems [SiS] USB 2.0 Controller
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (20000ns max)
	Interrupt: pin D routed to IRQ 23
	Region 0: Memory at ea001000 (32-bit, non-prefetchable)
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 39 10 02 70 06 00 90 02 00 20 03 0c 00 20 00 00
10: 00 10 00 ea 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 39 10 02 70
30: 00 00 00 00 50 00 00 00 00 00 00 00 09 04 00 50
40: 80 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 c9 00 00 00 00 0a 00 00 21 00 00 00 00
60: 20 20 7f 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 01 00 00 00 00 00 08 c0 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:04.0 Ethernet controller: Silicon Integrated Systems [SiS] SiS900 PCI Fast Ethernet (rev 90)
	Subsystem: Silicon Integrated Systems [SiS] SiS900 10/100 Ethernet Adapter
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (13000ns min, 2750ns max)
	Interrupt: pin A routed to IRQ 19
	Region 0: I/O ports at c800
	Region 1: Memory at ea002000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [40] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 39 10 00 09 07 00 90 02 90 00 00 02 00 20 00 00
10: 01 c8 00 00 00 20 00 ea 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 39 10 00 09
30: 00 00 00 00 40 00 00 00 00 00 00 00 0c 01 34 0b
40: 01 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:08.0 SCSI storage controller: LSI Logic / Symbios Logic 53c875 (rev 03)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 144 (4250ns min, 16000ns max), Cache Line Size 10
	Interrupt: pin A routed to IRQ 18
	Region 0: I/O ports at cc00
	Region 1: Memory at ea004000 (32-bit, non-prefetchable) [size=256]
	Region 2: Memory at ea005000 (32-bit, non-prefetchable) [size=4K]
00: 00 10 0f 00 17 00 00 02 03 00 00 01 10 90 00 00
10: 01 cc 00 00 00 40 00 ea 00 50 00 ea 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 11 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ca 00 00 05 47 00 00 0f 00 00 00 00 80 00 08 02
90: ff d0 f6 3f 00 ff ff ff 20 f0 31 31 a0 53 00 ea
a0: 00 08 24 00 00 00 00 50 b8 53 00 ea c0 53 00 ea
b0: 00 50 00 ea 00 c0 f6 3f 46 6d 00 81 c0 a3 00 ea
c0: 8f 05 00 00 00 00 70 0e 0c 00 80 00 07 0c 02 80
d0: 00 00 02 80 00 00 02 80 00 00 02 80 00 84 00 40
e0: 5e 56 a0 06 6e d5 cf de 20 10 95 c8 f6 fe ca 3b
f0: 00 81 08 49 57 9d b7 ac 27 25 45 a0 f5 d7 f7 fd

00:0a.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10)
	Subsystem: Unex Technology Corp. ND010
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (8000ns min, 16000ns max)
	Interrupt: pin A routed to IRQ 16
	Region 0: I/O ports at d000
	Region 1: Memory at ea006000 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 d0 00 00 00 60 00 ea 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 29 14 10 d0
30: 00 00 00 00 50 00 00 00 00 00 00 00 03 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 02 76 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:0b.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10)
	Subsystem: Realtek Semiconductor Co., Ltd. RT8139
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (8000ns min, 16000ns max)
	Interrupt: pin A routed to IRQ 17
	Region 0: I/O ports at d400
	Region 1: Memory at ea007000 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 d4 00 00 00 70 00 ea 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:0c.0 RAID bus controller: Silicon Integrated Systems [SiS]: Unknown device 0180 (prog-if 85)
	Subsystem: Silicon Integrated Systems [SiS]: Unknown device 0180
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 128
	Interrupt: pin A routed to IRQ 19
	Region 0: I/O ports at d800
	Region 1: I/O ports at dc00 [size=4]
	Region 2: I/O ports at e000 [size=8]
	Region 3: I/O ports at e400 [size=4]
	Region 4: I/O ports at e800 [size=16]
	Region 5: I/O ports at <unassigned>
00: 39 10 80 01 07 00 20 02 00 85 04 01 00 80 00 00
10: 01 d8 00 00 01 dc 00 00 01 e0 00 00 01 e4 00 00
20: 01 e8 00 00 01 00 00 00 00 00 00 00 39 10 80 01
30: 00 00 00 00 00 00 00 00 00 00 00 00 0c 01 00 00
40: 56 23 06 04 56 23 06 04 00 00 00 00 00 00 00 00
50: 82 20 82 00 2a 96 00 03 00 00 00 00 00 00 00 00
60: ff aa 00 00 d9 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: bd 33 72 40 bd 33 72 40 00 00 00 00 00 00 00 00
90: 34 00 00 03 01 00 00 00 cc 04 0c 10 c0 05 c0 05
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 01 00 18 00 00 03 00 00 00 00 00 00
d0: 00 00 00 00 01 00 18 00 00 03 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Capabilities: [80] #08 [2101]
00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00
40: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00
50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00
60: 00 00 00 00 e4 00 00 00 0f cc 00 0f 0c 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 08 00 01 21 20 00 11 11 22 05 75 80 02 00 00 00
90: 56 04 51 02 00 00 ff 00 07 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 03 00 00 00 00 00 3f 00 00 00 40 00 01 00 00 00
50: 00 00 40 00 02 00 00 00 00 00 40 00 03 00 00 00
60: 00 00 40 00 04 00 00 00 00 00 40 00 05 00 00 00
70: 00 00 40 00 06 00 00 00 00 00 40 00 07 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00
b0: 03 0a 00 00 00 0b 00 00 03 00 40 00 00 ff ff 00
c0: 00 00 00 00 00 00 00 00 13 10 00 00 00 f0 0f 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 01 00 00 00 01 00 00 01 01 00 00 02 01 00 00 03
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 fe e0 00 00 fe e0 00 00 fe e0 00 00 fe e0 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 33 00 00 00 00 00 00 00 45 34 e2 13 31 0b 00 00
90: 00 8c 0c 08 06 06 7b 3e 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 21 fc 20 1e de 00 00 00 8f e3 03 10 89 80 1f 0c
c0: 00 00 03 00 00 20 00 00 00 00 00 00 00 00 00 00
d0: 71 8d d2 81 5d 89 81 b6 8a cc 31 92 e4 78 0a 09
e0: 08 a6 f9 45 69 6a 02 56 d9 0f 59 bb 80 39 e9 c5
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: ff 3b 00 00 40 00 00 00 00 00 00 00 00 00 00 00
50: 20 80 07 00 42 00 00 00 00 00 00 00 80 a3 e3 48
60: c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00
80: 00 23 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 03 00 00 00 70 00 00 00 00 fc 01 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 1b 00 00 40 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 02 00 71 02 10 27 00 20 00 00 00 00
e0: 00 00 00 00 20 07 61 00 08 01 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

01:00.0 VGA compatible controller: Matrox Graphics, Inc. MGA G400 AGP (rev 04) (prog-if 00 [VGA])
	Subsystem: Matrox Graphics, Inc. Millennium G400 32Mb SDRAM
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (4000ns min, 8000ns max), Cache Line Size 08
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at e4000000 (32-bit, prefetchable)
	Region 1: Memory at e6000000 (32-bit, non-prefetchable) [size=16K]
	Region 2: Memory at e7000000 (32-bit, non-prefetchable) [size=8M]
	Capabilities: [dc] Power Management version 2
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [f0] AGP version 2.0
		Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4
		Command: RQ=32 ArqSz=0 Cal=0 SBA+ AGP+ GART64- 64bit- FW- Rate=x1
00: 2b 10 25 05 07 00 90 02 04 00 00 03 08 20 00 00
10: 08 00 00 e4 00 00 00 e6 00 00 00 e7 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 2b 10 78 03
30: 00 00 00 00 dc 00 00 00 00 00 00 00 03 01 10 20
40: 20 0d 04 50 08 3c 00 00 00 00 00 00 00 00 00 00
50: 00 30 00 01 21 a4 90 01 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 f0 22 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 02 00 20 00 07 02 00 1f 01 03 00 1f 00 00 00 00


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-05 20:31     ` Uwe Koziolek
  2004-07-05 20:55       ` Jeff Garzik
@ 2004-07-05 21:05       ` Nicola
  2004-07-05 21:24         ` Uwe Koziolek
  1 sibling, 1 reply; 19+ messages in thread
From: Nicola @ 2004-07-05 21:05 UTC (permalink / raw)
  To: Uwe Koziolek; +Cc: Jeff Garzik, linux-ide

On Monday 05 July 2004 22:31, you wrote:
> Hello Nicola,
>
> please can you provide the output of lspci -vvxxx
>
Here we are:

00:0c.0 RAID bus controller: Silicon Integrated Systems [SiS]: Unknown device 
0180 (prog-if 85)
	Subsystem: Silicon Integrated Systems [SiS]: Unknown device 0180
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- 
SERR- FastB2B-
	Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- 
<MAbort- >SERR- <PERR-
	Latency: 128
	Interrupt: pin A routed to IRQ 19
	Region 0: I/O ports at d800
	Region 1: I/O ports at dc00 [size=4]
	Region 2: I/O ports at e000 [size=8]
	Region 3: I/O ports at e400 [size=4]
	Region 4: I/O ports at e800 [size=16]
	Region 5: I/O ports at <unassigned>
00: 39 10 80 01 07 00 20 02 00 85 04 01 00 80 00 00
10: 01 d8 00 00 01 dc 00 00 01 e0 00 00 01 e4 00 00
20: 01 e8 00 00 01 00 00 00 00 00 00 00 39 10 80 01
30: 00 00 00 00 00 00 00 00 00 00 00 00 0c 01 00 00
40: 56 23 06 04 56 23 06 04 00 00 00 00 00 00 00 00
50: 82 20 82 00 2a 96 00 03 00 00 00 00 00 00 00 00
60: ff aa 00 00 d9 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: bd 33 72 40 bd 33 72 40 00 00 00 00 00 00 00 00
90: 34 00 00 03 01 00 00 00 cc 04 0c 10 c0 05 c0 05
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 01 00 18 00 00 03 00 00 00 00 00 00
d0: 00 00 00 00 01 00 18 00 00 03 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-05 21:05       ` Nicola
@ 2004-07-05 21:24         ` Uwe Koziolek
  2004-07-05 21:27           ` Nicola
  2004-07-05 21:30           ` Nicola
  0 siblings, 2 replies; 19+ messages in thread
From: Uwe Koziolek @ 2004-07-05 21:24 UTC (permalink / raw)
  To: Nicola; +Cc: Jeff Garzik, linux-ide

Hello Nicola,

please provide the complete output of lspci -vvxxx, not only the the
device 1039:0180. I want to see, if there is a different IDE-Adapter
to SIS5513/18 and SiS180.
If not, the pata ports may be the slaves on SIS180.

regards
Uwe

> Here we are:
> 
> 00:0c.0 RAID bus controller: Silicon Integrated Systems [SiS]: Unknown device 

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-05 21:24         ` Uwe Koziolek
@ 2004-07-05 21:27           ` Nicola
  2004-07-07  5:36             ` Jeff Garzik
  2004-07-05 21:30           ` Nicola
  1 sibling, 1 reply; 19+ messages in thread
From: Nicola @ 2004-07-05 21:27 UTC (permalink / raw)
  To: Uwe Koziolek; +Cc: Jeff Garzik, linux-ide

[-- Attachment #1: Type: text/plain, Size: 457 bytes --]

On Monday 05 July 2004 23:24, Uwe Koziolek wrote:
> Hello Nicola,
>
> please provide the complete output of lspci -vvxxx, not only the the
> device 1039:0180. I want to see, if there is a different IDE-Adapter
> to SIS5513/18 and SiS180.
> If not, the pata ports may be the slaves on SIS180.
>
> regards
> Uwe
>
> > Here we are:
> >
> > 00:0c.0 RAID bus controller: Silicon Integrated Systems [SiS]: Unknown
> > device
Sure, sorry. Here is the attachment.


[-- Attachment #2: lspci.txt --]
[-- Type: text/plain, Size: 25565 bytes --]

00:00.0 Host bridge: Silicon Integrated Systems [SiS] 755 Host (rev 01)
	Subsystem: Silicon Integrated Systems [SiS] 755 Host
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
	Latency: 32
	Region 0: Memory at e0000000 (32-bit, non-prefetchable)
	Capabilities: [a0] AGP version 3.0
		Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4
		Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none>
	Capabilities: [d0] #08 [0120]
	Capabilities: [f0] #08 [8000]
00: 39 10 55 07 07 00 10 22 01 00 00 06 00 20 00 00
10: 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 39 10 55 07
30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 00 00
40: 16 00 74 17 0c ff 90 e0 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 0c 80 00 00 00 00 00 00 00 00 00 00 00 00 21 10
80: 00 00 00 00 00 00 14 c8 00 00 00 10 00 03 00 02
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 d0 30 00 07 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 30 0f 01 00 00 00 00 00 00 00 00 00
c0: 00 08 18 00 02 88 45 28 00 00 00 00 00 01 00 00
d0: 08 f0 20 01 60 00 11 11 d0 00 77 77 22 05 35 00
e0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 08 00 00 80 44 01 99 f8 00 00 00 00 77 77 33 00

00:01.0 PCI bridge: Silicon Integrated Systems [SiS] SG86C202 (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 99
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=32
	Memory behind bridge: e6000000-e8ffffff
	Prefetchable memory behind bridge: e4000000-e5ffffff
	BridgeCtl: Parity- SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B-
00: 39 10 02 00 07 01 20 02 00 00 04 06 00 63 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 20 f0 00 20 22
20: 00 e6 f0 e8 00 e4 f0 e5 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0e 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 02 40 00 00 09 00 80 00 08 00 00 00 00 00 00 00
60: 30 02 60 60 aa 10 00 00 23 23 98 15 00 00 08 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 15 18 15 18

00:02.0 ISA bridge: Silicon Integrated Systems [SiS] SiS963 [MuTIOL Media IO] (rev 25)
	Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
00: 39 10 63 09 0f 00 00 02 25 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: d2 03 07 0b 0c 40 3d dd 10 00 00 00 11 20 04 03
50: 11 28 02 01 60 0b 20 0b a9 04 12 00 d2 00 00 00
60: 0c 0b 80 09 ff c1 0a 12 09 80 00 46 97 00 02 14
70: 05 00 ff ff 00 10 00 2e 20 00 20 80 f2 00 00 40
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 00 00 40 00 00 00 00 0c 80 00 00 00 00 00 41
d0: 20 0c 00 01 22 62 32 00 85 00 04 2a aa aa aa aa
e0: 40 00 00 f8 42 20 44 00 bd 42 00 00 00 00 00 00
f0: 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.1 SMBus: Silicon Integrated Systems [SiS]: Unknown device 0016
	Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Interrupt: pin B routed to IRQ 17
	Region 4: I/O ports at 10c0 [size=32]
00: 39 10 16 00 01 00 80 02 00 00 05 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: c1 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00
40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.5 IDE interface: Silicon Integrated Systems [SiS] 5513 [IDE] (prog-if 80 [Master])
	Subsystem: Silicon Integrated Systems [SiS] SiS5513 EIDE Controller (A,B step)
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 128
	Region 4: I/O ports at 4000 [size=16]
00: 39 10 13 55 05 00 00 02 00 80 01 01 00 80 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 40 00 00 00 00 00 00 00 00 00 00 39 10 13 55
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 06 00 00 00 00 00
50: f2 07 f2 07 2a 96 d5 c0 00 00 00 00 00 00 00 00
60: fb aa fb aa 00 00 00 00 00 00 00 00 00 00 00 00
70: 1e 32 09 05 56 23 06 04 1e 32 09 05 00 60 1c 1e
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.7 Multimedia audio controller: Silicon Integrated Systems [SiS] Sound Controller (rev a0)
	Subsystem: Unknown device 16f3:473d
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (13000ns min, 2750ns max)
	Interrupt: pin C routed to IRQ 18
	Region 0: I/O ports at c000
	Region 1: I/O ports at c400 [size=128]
	Capabilities: [48] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=55mA PME(D0-,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 39 10 12 70 05 00 90 02 a0 00 01 04 00 20 00 00
10: 01 c0 00 00 01 c4 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 f3 16 3d 47
30: 00 00 00 00 48 00 00 00 00 00 00 00 0b 03 34 0b
40: 04 00 00 00 00 00 00 00 01 00 42 c6 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:03.0 USB Controller: Silicon Integrated Systems [SiS] USB 1.0 Controller (rev 0f) (prog-if 10 [OHCI])
	Subsystem: Silicon Integrated Systems [SiS] USB 1.0 Controller
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (20000ns max), Cache Line Size 08
	Interrupt: pin A routed to IRQ 20
	Region 0: Memory at ea003000 (32-bit, non-prefetchable)
00: 39 10 01 70 07 00 80 02 0f 10 03 0c 08 20 80 00
10: 00 30 00 ea 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 39 10 01 70
30: 00 00 00 00 00 00 00 00 00 00 00 00 0c 01 00 50
40: 00 00 00 00 5c ae 01 00 0f 02 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 c2 c9
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:03.1 USB Controller: Silicon Integrated Systems [SiS] USB 1.0 Controller (rev 0f) (prog-if 10 [OHCI])
	Subsystem: Silicon Integrated Systems [SiS] USB 1.0 Controller
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (20000ns max), Cache Line Size 08
	Interrupt: pin B routed to IRQ 21
	Region 0: Memory at ea000000 (32-bit, non-prefetchable)
00: 39 10 01 70 07 00 80 02 0f 10 03 0c 08 20 00 00
10: 00 00 00 ea 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 39 10 01 70
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 02 00 50
40: 00 00 00 00 5c ae 01 00 0f 02 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 c2 c9
e0: 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:03.3 USB Controller: Silicon Integrated Systems [SiS] USB 2.0 Controller (prog-if 20 [EHCI])
	Subsystem: Silicon Integrated Systems [SiS] USB 2.0 Controller
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (20000ns max)
	Interrupt: pin D routed to IRQ 23
	Region 0: Memory at ea001000 (32-bit, non-prefetchable)
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 39 10 02 70 06 00 90 02 00 20 03 0c 00 20 00 00
10: 00 10 00 ea 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 39 10 02 70
30: 00 00 00 00 50 00 00 00 00 00 00 00 09 04 00 50
40: 80 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 c9 00 00 00 00 0a 00 00 21 00 00 00 00
60: 20 20 7f 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 01 00 00 00 00 00 08 c0 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:04.0 Ethernet controller: Silicon Integrated Systems [SiS] SiS900 PCI Fast Ethernet (rev 90)
	Subsystem: Silicon Integrated Systems [SiS] SiS900 10/100 Ethernet Adapter
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (13000ns min, 2750ns max)
	Interrupt: pin A routed to IRQ 19
	Region 0: I/O ports at c800
	Region 1: Memory at ea002000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [40] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 39 10 00 09 07 00 90 02 90 00 00 02 00 20 00 00
10: 01 c8 00 00 00 20 00 ea 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 39 10 00 09
30: 00 00 00 00 40 00 00 00 00 00 00 00 0c 01 34 0b
40: 01 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:08.0 SCSI storage controller: LSI Logic / Symbios Logic 53c875 (rev 03)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 144 (4250ns min, 16000ns max), Cache Line Size 10
	Interrupt: pin A routed to IRQ 18
	Region 0: I/O ports at cc00
	Region 1: Memory at ea004000 (32-bit, non-prefetchable) [size=256]
	Region 2: Memory at ea005000 (32-bit, non-prefetchable) [size=4K]
00: 00 10 0f 00 17 00 00 02 03 00 00 01 10 90 00 00
10: 01 cc 00 00 00 40 00 ea 00 50 00 ea 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 11 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: ca 00 00 05 47 00 00 0f 00 00 00 00 80 00 08 02
90: ff d0 f6 3f 00 ff ff ff 20 f0 31 31 a0 53 00 ea
a0: 00 08 24 00 00 00 00 50 b8 53 00 ea c0 53 00 ea
b0: 00 50 00 ea 00 c0 f6 3f 46 6d 00 81 c0 a3 00 ea
c0: 8f 05 00 00 00 00 70 0e 0c 00 80 00 07 0c 02 80
d0: 00 00 02 80 00 00 02 80 00 00 02 80 00 84 00 40
e0: 5e 56 a0 06 6e d5 cf de 20 10 95 c8 f6 fe ca 3b
f0: 00 81 08 49 57 9d b7 ac 27 25 45 a0 f5 d7 f7 fd

00:0a.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10)
	Subsystem: Unex Technology Corp. ND010
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (8000ns min, 16000ns max)
	Interrupt: pin A routed to IRQ 16
	Region 0: I/O ports at d000
	Region 1: Memory at ea006000 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 d0 00 00 00 60 00 ea 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 29 14 10 d0
30: 00 00 00 00 50 00 00 00 00 00 00 00 03 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 02 76 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:0b.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10)
	Subsystem: Realtek Semiconductor Co., Ltd. RT8139
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (8000ns min, 16000ns max)
	Interrupt: pin A routed to IRQ 17
	Region 0: I/O ports at d400
	Region 1: Memory at ea007000 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 d4 00 00 00 70 00 ea 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 20 40
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:0c.0 RAID bus controller: Silicon Integrated Systems [SiS]: Unknown device 0180 (prog-if 85)
	Subsystem: Silicon Integrated Systems [SiS]: Unknown device 0180
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 128
	Interrupt: pin A routed to IRQ 19
	Region 0: I/O ports at d800
	Region 1: I/O ports at dc00 [size=4]
	Region 2: I/O ports at e000 [size=8]
	Region 3: I/O ports at e400 [size=4]
	Region 4: I/O ports at e800 [size=16]
	Region 5: I/O ports at <unassigned>
00: 39 10 80 01 07 00 20 02 00 85 04 01 00 80 00 00
10: 01 d8 00 00 01 dc 00 00 01 e0 00 00 01 e4 00 00
20: 01 e8 00 00 01 00 00 00 00 00 00 00 39 10 80 01
30: 00 00 00 00 00 00 00 00 00 00 00 00 0c 01 00 00
40: 56 23 06 04 56 23 06 04 00 00 00 00 00 00 00 00
50: 82 20 82 00 2a 96 00 03 00 00 00 00 00 00 00 00
60: ff aa 00 00 d9 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: bd 33 72 40 bd 33 72 40 00 00 00 00 00 00 00 00
90: 34 00 00 03 01 00 00 00 cc 04 0c 10 c0 05 c0 05
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 01 00 18 00 00 03 00 00 00 00 00 00
d0: 00 00 00 00 01 00 18 00 00 03 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Capabilities: [80] #08 [2101]
00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00
40: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00
50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00
60: 00 00 00 00 e4 00 00 00 0f cc 00 0f 0c 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 08 00 01 21 20 00 11 11 22 05 75 80 02 00 00 00
90: 56 04 51 02 00 00 ff 00 07 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 03 00 00 00 00 00 3f 00 00 00 40 00 01 00 00 00
50: 00 00 40 00 02 00 00 00 00 00 40 00 03 00 00 00
60: 00 00 40 00 04 00 00 00 00 00 40 00 05 00 00 00
70: 00 00 40 00 06 00 00 00 00 00 40 00 07 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00
b0: 03 0a 00 00 00 0b 00 00 03 00 40 00 00 ff ff 00
c0: 00 00 00 00 00 00 00 00 13 10 00 00 00 f0 0f 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 01 00 00 00 01 00 00 01 01 00 00 02 01 00 00 03
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 fe e0 00 00 fe e0 00 00 fe e0 00 00 fe e0 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 33 00 00 00 00 00 00 00 45 34 e2 13 31 0b 00 00
90: 00 8c 0c 08 06 06 7b 3e 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 21 fc 20 1e de 00 00 00 8f e3 03 10 89 80 1f 0c
c0: 00 00 03 00 00 20 00 00 00 00 00 00 00 00 00 00
d0: 71 8d d2 81 5d 89 81 b6 8a cc 31 92 e4 78 0a 09
e0: 08 a6 f9 45 69 6a 02 56 d9 0f 59 bb 80 39 e9 c5
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 NorthBridge
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: ff 3b 00 00 40 00 00 00 00 00 00 00 00 00 00 00
50: 20 80 07 00 42 00 00 00 00 00 00 00 80 a3 e3 48
60: c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00
80: 00 23 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 03 00 00 00 70 00 00 00 00 fc 01 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 1b 00 00 40 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 02 00 71 02 10 27 00 20 00 00 00 00
e0: 00 00 00 00 20 07 61 00 08 01 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

01:00.0 VGA compatible controller: Matrox Graphics, Inc. MGA G400 AGP (rev 04) (prog-if 00 [VGA])
	Subsystem: Matrox Graphics, Inc. Millennium G400 32Mb SDRAM
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (4000ns min, 8000ns max), Cache Line Size 08
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at e4000000 (32-bit, prefetchable)
	Region 1: Memory at e6000000 (32-bit, non-prefetchable) [size=16K]
	Region 2: Memory at e7000000 (32-bit, non-prefetchable) [size=8M]
	Capabilities: [dc] Power Management version 2
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [f0] AGP version 2.0
		Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4
		Command: RQ=32 ArqSz=0 Cal=0 SBA+ AGP+ GART64- 64bit- FW- Rate=x1
00: 2b 10 25 05 07 00 90 02 04 00 00 03 08 20 00 00
10: 08 00 00 e4 00 00 00 e6 00 00 00 e7 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 2b 10 78 03
30: 00 00 00 00 dc 00 00 00 00 00 00 00 03 01 10 20
40: 20 0d 04 50 08 3c 00 00 00 00 00 00 00 00 00 00
50: 00 30 00 01 21 a4 90 01 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 f0 22 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 02 00 20 00 07 02 00 1f 01 03 00 1f 00 00 00 00


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-05 21:27           ` Nicola
@ 2004-07-07  5:36             ` Jeff Garzik
  2004-07-07  9:54               ` Bartlomiej Zolnierkiewicz
  0 siblings, 1 reply; 19+ messages in thread
From: Jeff Garzik @ 2004-07-07  5:36 UTC (permalink / raw)
  To: Nicola; +Cc: Uwe Koziolek, linux-ide

Nicola wrote:
> 00:02.5 IDE interface: Silicon Integrated Systems [SiS] 5513 [IDE] (prog-if 80 [Master])
> 	Subsystem: Silicon Integrated Systems [SiS] SiS5513 EIDE Controller (A,B step)
> 	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
> 	Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-

> 00:0c.0 RAID bus controller: Silicon Integrated Systems [SiS]: Unknown device 0180 (prog-if 85)
> 	Subsystem: Silicon Integrated Systems [SiS]: Unknown device 0180
> 	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
> 	Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-


It certainly looks like IDE and SATA devices are separate to me?


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-07  5:36             ` Jeff Garzik
@ 2004-07-07  9:54               ` Bartlomiej Zolnierkiewicz
  2004-07-07 10:02                 ` Bartlomiej Zolnierkiewicz
  0 siblings, 1 reply; 19+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2004-07-07  9:54 UTC (permalink / raw)
  To: Jeff Garzik, Nicola; +Cc: Uwe Koziolek, linux-ide

On Wednesday 07 of July 2004 07:36, Jeff Garzik wrote:
> Nicola wrote:
> > 00:02.5 IDE interface: Silicon Integrated Systems [SiS] 5513 [IDE]
> > (prog-if 80 [Master]) Subsystem: Silicon Integrated Systems [SiS] SiS5513
> > EIDE Controller (A,B step) Control: I/O+ Mem- BusMaster+ SpecCycle-
> > MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz-
> > UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR-
> > <PERR-
> >
> > 00:0c.0 RAID bus controller: Silicon Integrated Systems [SiS]: Unknown
> > device 0180 (prog-if 85) Subsystem: Silicon Integrated Systems [SiS]:
> > Unknown device 0180 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV-
> > VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz+ UDF-
> > FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
>
> It certainly looks like IDE and SATA devices are separate to me?

there are 4 IDE ports on this motherboard...


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-07  9:54               ` Bartlomiej Zolnierkiewicz
@ 2004-07-07 10:02                 ` Bartlomiej Zolnierkiewicz
  2004-07-07 14:18                   ` Nicola
  0 siblings, 1 reply; 19+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2004-07-07 10:02 UTC (permalink / raw)
  To: Jeff Garzik, Nicola; +Cc: Uwe Koziolek, linux-ide

On Wednesday 07 of July 2004 11:54, Bartlomiej Zolnierkiewicz wrote:
> On Wednesday 07 of July 2004 07:36, Jeff Garzik wrote:
> > Nicola wrote:
> > > 00:02.5 IDE interface: Silicon Integrated Systems [SiS] 5513 [IDE]
> > > (prog-if 80 [Master]) Subsystem: Silicon Integrated Systems [SiS]
> > > SiS5513 EIDE Controller (A,B step) Control: I/O+ Mem- BusMaster+
> > > SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status:
> > > Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort-
> > > <MAbort- >SERR- <PERR-
> > >
> > > 00:0c.0 RAID bus controller: Silicon Integrated Systems [SiS]: Unknown
> > > device 0180 (prog-if 85) Subsystem: Silicon Integrated Systems [SiS]:
> > > Unknown device 0180 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV-
> > > VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz+ UDF-
> > > FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
> >
> > It certainly looks like IDE and SATA devices are separate to me?
>
> there are 4 IDE ports on this motherboard...

eh, 3 not 4 - 2 from SiS5513 and 1 from SiS180
(http://www.jetway.com.tw/evisn/product/amd/S755MAX/S755MAX.jpg)


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-07 10:02                 ` Bartlomiej Zolnierkiewicz
@ 2004-07-07 14:18                   ` Nicola
  2004-07-11 21:46                     ` Uwe Koziolek
  0 siblings, 1 reply; 19+ messages in thread
From: Nicola @ 2004-07-07 14:18 UTC (permalink / raw)
  To: Bartlomiej Zolnierkiewicz; +Cc: Jeff Garzik, Uwe Koziolek, linux-ide


> eh, 3 not 4 - 2 from SiS5513 and 1 from SiS180
> (http://www.jetway.com.tw/evisn/product/amd/S755MAX/S755MAX.jpg)
Correct. 2 pata from 5513, 1 pata and 2 sata from 180. The 180 has no bios 
cyl/head stuff entry, just on/off and if booting before or after scsi - the 
latter is not onboard.

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-07 14:18                   ` Nicola
@ 2004-07-11 21:46                     ` Uwe Koziolek
  2004-07-11 21:57                       ` Jeff Garzik
  0 siblings, 1 reply; 19+ messages in thread
From: Uwe Koziolek @ 2004-07-11 21:46 UTC (permalink / raw)
  To: jgarzik; +Cc: linux-ide, Nicola

Hello Jeff,

will you support this specific constellation?, or should i try to
implemenent master/slave support to sata_sis and hope this will solve
the problem.

regards
Uwe


> > eh, 3 not 4 - 2 from SiS5513 and 1 from SiS180
> > (http://www.jetway.com.tw/evisn/product/amd/S755MAX/S755MAX.jpg)
> Correct. 2 pata from 5513, 1 pata and 2 sata from 180. The 180 has no bios 
> cyl/head stuff entry, just on/off and if booting before or after scsi - the 
> latter is not onboard.



^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-11 21:46                     ` Uwe Koziolek
@ 2004-07-11 21:57                       ` Jeff Garzik
  2004-07-27 20:54                         ` Uwe Koziolek
  0 siblings, 1 reply; 19+ messages in thread
From: Jeff Garzik @ 2004-07-11 21:57 UTC (permalink / raw)
  To: Uwe Koziolek; +Cc: linux-ide, Nicola

Uwe Koziolek wrote:
> Hello Jeff,
> 
> will you support this specific constellation?, or should i try to
> implemenent master/slave support to sata_sis and hope this will solve
> the problem.

It is a similar problem to supporting PATA port of Promise hardware, in 
that you need to use different code paths when talking to the same 
hardware.  It isn't as easy as the solution in ata_piix unfortunately. 
I need to split struct ata_probe_ent into per-bus pieces, then both 
Promise and SIS180 PATA can be supported.

	Jeff

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-11 21:57                       ` Jeff Garzik
@ 2004-07-27 20:54                         ` Uwe Koziolek
  0 siblings, 0 replies; 19+ messages in thread
From: Uwe Koziolek @ 2004-07-27 20:54 UTC (permalink / raw)
  To: Jeff Garzik; +Cc: linux-ide, Nicola

Hello Jeff,

when do you expect, this new feature in libata will be available?

with best regards
Uwe Koziolek

> Uwe Koziolek wrote:
> > Hello Jeff,
> > 
> > will you support this specific constellation?, or should i try to
> > implemenent master/slave support to sata_sis and hope this will solve
> > the problem.
> 
> 
> It is a similar problem to supporting PATA port of Promise hardware, in 
> that you need to use different code paths when talking to the same 
> hardware.  It isn't as easy as the solution in ata_piix unfortunately. 
> I need to split struct ata_probe_ent into per-bus pieces, then both 
> Promise and SIS180 PATA can be supported.
> 
> 	Jeff
> 
> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-05 21:24         ` Uwe Koziolek
  2004-07-05 21:27           ` Nicola
@ 2004-07-05 21:30           ` Nicola
  2004-07-05 21:52             ` Uwe Koziolek
  1 sibling, 1 reply; 19+ messages in thread
From: Nicola @ 2004-07-05 21:30 UTC (permalink / raw)
  To: Uwe Koziolek; +Cc: Jeff Garzik, linux-ide

On Monday 05 July 2004 23:24, Uwe Koziolek wrote:
> Hello Nicola,
>
> please provide the complete output of lspci -vvxxx, not only the the
> device 1039:0180. I want to see, if there is a different IDE-Adapter
> to SIS5513/18 and SiS180.
> If not, the pata ports may be the slaves on SIS180.
Another thing I noticed:
when the interface has no disks, the bios labels primary and secondary master 
as SATA, other interfaces as slave (not speciified).
When I attach a pata drive, however, it is recognised from the bios as primary 
master (jumpered as master, of course).

Thanks
Nicola

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-05 21:30           ` Nicola
@ 2004-07-05 21:52             ` Uwe Koziolek
  2004-07-05 21:57               ` Nicola
  0 siblings, 1 reply; 19+ messages in thread
From: Uwe Koziolek @ 2004-07-05 21:52 UTC (permalink / raw)
  To: Nicola; +Cc: Jeff Garzik, linux-ide

Hello Nicola,

i have not found any different IDE-Hardware from SIS5513/18 and SiS180
in the lspci output. So i assume the additional PATA-ports requires a
special programming in the SiS180 Code. 
I hope that Jeff can helps. He has provided the PATA emulation in
sata_sis.c

regards 
Uwe

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: SiS 180 pata
  2004-07-05 21:52             ` Uwe Koziolek
@ 2004-07-05 21:57               ` Nicola
  0 siblings, 0 replies; 19+ messages in thread
From: Nicola @ 2004-07-05 21:57 UTC (permalink / raw)
  To: Uwe Koziolek; +Cc: Jeff Garzik, linux-ide

On Monday 05 July 2004 23:52, Uwe Koziolek wrote:
> Hello Nicola,
>
> i have not found any different IDE-Hardware from SIS5513/18 and SiS180
> in the lspci output. So i assume the additional PATA-ports requires a
> special programming in the SiS180 Code.
> I hope that Jeff can helps. He has provided the PATA emulation in
> sata_sis.c
>
> regards
> Uwe
Thanks. So if I understand correctly, we need more info from SiS? Is there any 
way one could ask them politely for more documentation?

Cheers
Nicola

^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2004-07-27 20:53 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2004-07-05 10:53 SiS 180 pata Nicola
2004-07-05 13:43 ` Jeff Garzik
2004-07-05 14:03   ` Nicola
2004-07-05 20:31     ` Uwe Koziolek
2004-07-05 20:55       ` Jeff Garzik
2004-07-05 21:15         ` Nicola
2004-07-05 21:05       ` Nicola
2004-07-05 21:24         ` Uwe Koziolek
2004-07-05 21:27           ` Nicola
2004-07-07  5:36             ` Jeff Garzik
2004-07-07  9:54               ` Bartlomiej Zolnierkiewicz
2004-07-07 10:02                 ` Bartlomiej Zolnierkiewicz
2004-07-07 14:18                   ` Nicola
2004-07-11 21:46                     ` Uwe Koziolek
2004-07-11 21:57                       ` Jeff Garzik
2004-07-27 20:54                         ` Uwe Koziolek
2004-07-05 21:30           ` Nicola
2004-07-05 21:52             ` Uwe Koziolek
2004-07-05 21:57               ` Nicola

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