Re: ATA Write Error and Time-out Notification in User Space

[Erik Slagter <erik@slagter.name>]

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On Tue, 2006-01-03 at 18:58 +0000, Alan Cox wrote:

> There is a known old bug with error handling in some cases on promise
> chips. The core kernel code tries to clean up any remaining data after
> an error (to handle chip prefetch/postwrite FIFOs) if DRQ_STAT is
> asserted. Its a nice trick, saves on resets and slow recovery but isn't
> compatible with some promise controllers.
> 
> The -mm tree has a partial but incomplete fix to this implemented, the
> base kernel does not have this fixed.
> 
> Its been known for some time so perhaps the ide maintainers have patches
> waiting for 2.6.16 now its opened ?

Is this patch supposed to fix this problem:

Promise SATAII150 TX2plus using libata_promise, when it misses one
single interrupt (or maybe it's not even missed but only delayed), it
goes crazy, kernel log is full with disk failures, and the disk is
kicked out of the md(1) array grmbl.

This happens when amd76x_pm is used, even with the irq watcher in the
utter most conservative setting.

Any clue otherwise?

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