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From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: linux-ide@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: Assorted bugs in the PIIX drivers
Date: Mon, 15 May 2006 16:59:43 +0100	[thread overview]
Message-ID: <1147708783.26686.69.camel@localhost.localdomain> (raw)
In-Reply-To: <44689A54.4020307@ru.mvista.com>

On Llu, 2006-05-15 at 19:12 +0400, Sergei Shtylyov wrote:
>     For PIO2+ actually, according to Intel's PRM (29860004.pdf), and it's said
> to have no effect in the lower modes. This is actually not very correct since
> when one issues Set Transfer Mode ATA command with the value (8 + PIOn), this
> means select PIO _flow control_ mode n, so -IORDY is assumed to be in use.

PIO2 depends on the drive (there is a drive parameter telling you the
highest timing clock you can do with/without IORDY

> > I'm also not clear if the "no MWDMA0" list has been updated correctly
> > for the newer chipsets.
> 
>     What is/was the point for keeping MW DMA 0 support anyway? On PIIX, it's
> greatly slowed down (600 vs 480 ns cycle) and was never "offically" supported
> by Intel.

Some old old drives only do MWDMA0. The Intel docs I have here don't
describe it in any way as "unsupported", merely broken on some ICH
variants.

Alan


  reply	other threads:[~2006-05-15 15:47 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2005-11-25 14:43 Assorted bugs in the PIIX drivers Alan Cox
2005-11-25 14:53 ` Alan Cox
2005-11-25 15:36 ` Marc Koschewski
2005-11-25 17:12   ` Alan Cox
2006-05-15 15:12 ` Sergei Shtylyov
2006-05-15 15:59   ` Alan Cox [this message]
2006-05-15 18:26     ` Sergei Shtylyov
  -- strict thread matches above, loose matches on Subject: below --
2005-11-25 15:44 SMALL, Timothy

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