* [PATCHSET] ahci updates regarding vt8251 support, take #2
@ 2006-10-15 22:43 Tejun Heo
2006-10-15 22:43 ` [PATCH 2/3] [PATCH] ahci: update softreset and kill AHCI_FLAG_RESET_NEEDS_CLO Tejun Heo
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Tejun Heo @ 2006-10-15 22:43 UTC (permalink / raw)
To: jgarzik, alan, aalderd.boac, linux-ide, htejun
Hello, all.
This is the second take of vt8251-ahci patchset. This patchset
updates libata and ahci to improve vt8251 EH and hotplug support.
#01 : separate out sata_port_hardreset(), to be used by vt8251 reset
#02 : update CLO handling in softreset and kill RESET_NEEDS_CLO
#03 : update vt8251 support in ahci
Changes from the last take[L] are
* rebased over the current upstream + hp-poll
* hp-poll callbacks added to ahci_vt8251_ops
This patchset is against
upstream (da54f5fe54c7d75e2db7d17961fb36a8c28a8501)
+ hp-poll patchset, take #5 [1]
This patchset has been verified by me and Aalderd Bouwman
<aalderd.boac@wanadoo.nl>.
The git tree is avilable at
http://htj.dyndns.org/git/?p=libata-tj.git;a=shortlog;h=vt8251-ahci
git://htj.dyndns.org/libata-tj vt8251-ahci
Thanks.
--
tejun
[L] http://article.gmane.org/gmane.linux.ide/13449
[1] http://article.gmane.org/gmane.linux.ide/13467
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] [PATCH] ahci: update ahci-vt8251 reset sequence
2006-10-15 22:43 [PATCHSET] ahci updates regarding vt8251 support, take #2 Tejun Heo
2006-10-15 22:43 ` [PATCH 2/3] [PATCH] ahci: update softreset and kill AHCI_FLAG_RESET_NEEDS_CLO Tejun Heo
2006-10-15 22:43 ` [PATCH 1/3] [PATCH] libata: separate out and export sata_port_hardreset() Tejun Heo
@ 2006-10-15 22:43 ` Tejun Heo
2006-10-18 4:45 ` [PATCHSET] ahci updates regarding vt8251 support, take #2 Aalderd Bouwman
2006-10-21 19:23 ` Jeff Garzik
4 siblings, 0 replies; 9+ messages in thread
From: Tejun Heo @ 2006-10-15 22:43 UTC (permalink / raw)
To: jgarzik, alan, aalderd.boac, linux-ide; +Cc: Tejun Heo
ahci-vt8251
* requires hardreset after PHY status change
* doesn't clear BSY on signature FIS after hardreset
* needs SError cleared for the port to operate after hardreset
This patch implements ahci_vt8251_hardreset() and sets
ATA_FLAG_HRST_TO_RESUME to handle the above behaviors. This fixes EH
including hotplug on vt8251.
Signed-off-by: Tejun Heo <htejun@gmail.com>
---
drivers/ata/ahci.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 79 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index f103799..584b6c6 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -213,6 +213,7 @@ static u8 ahci_check_status(struct ata_p
static void ahci_freeze(struct ata_port *ap);
static void ahci_thaw(struct ata_port *ap);
static void ahci_error_handler(struct ata_port *ap);
+static void ahci_vt8251_error_handler(struct ata_port *ap);
static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
static int ahci_port_resume(struct ata_port *ap);
@@ -274,6 +275,40 @@ static const struct ata_port_operations
.port_stop = ahci_port_stop,
};
+static const struct ata_port_operations ahci_vt8251_ops = {
+ .port_disable = ata_port_disable,
+
+ .check_status = ahci_check_status,
+ .check_altstatus = ahci_check_status,
+ .dev_select = ata_noop_dev_select,
+
+ .tf_read = ahci_tf_read,
+
+ .qc_prep = ahci_qc_prep,
+ .qc_issue = ahci_qc_issue,
+
+ .irq_handler = ahci_interrupt,
+ .irq_clear = ahci_irq_clear,
+
+ .scr_read = ahci_scr_read,
+ .scr_write = ahci_scr_write,
+
+ .freeze = ahci_freeze,
+ .thaw = ahci_thaw,
+
+ .error_handler = ahci_vt8251_error_handler,
+ .post_internal_cmd = ahci_post_internal_cmd,
+
+ .hp_poll_activate = sata_std_hp_poll_activate,
+ .hp_poll = sata_std_hp_poll,
+
+ .port_suspend = ahci_port_suspend,
+ .port_resume = ahci_port_resume,
+
+ .port_start = ahci_port_start,
+ .port_stop = ahci_port_stop,
+};
+
static const struct ata_port_info ahci_port_info[] = {
/* board_ahci */
{
@@ -290,10 +325,11 @@ static const struct ata_port_info ahci_p
.sht = &ahci_sht,
.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
- ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_NO_NCQ,
+ ATA_FLAG_SKIP_D2H_BSY |
+ ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
.pio_mask = 0x1f, /* pio0-4 */
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
- .port_ops = &ahci_ops,
+ .port_ops = &ahci_vt8251_ops,
},
};
@@ -834,6 +870,31 @@ static int ahci_hardreset(struct ata_por
return rc;
}
+static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
+{
+ void __iomem *mmio = ap->host->mmio_base;
+ void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
+ int rc;
+
+ DPRINTK("ENTER\n");
+
+ ahci_stop_engine(port_mmio);
+
+ rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
+
+ /* vt8251 needs SError cleared for the port to operate */
+ ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
+
+ ahci_start_engine(port_mmio);
+
+ DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
+
+ /* vt8251 doesn't clear BSY on signature FIS reception,
+ * request follow-up softreset.
+ */
+ return rc ?: -EAGAIN;
+}
+
static void ahci_postreset(struct ata_port *ap, unsigned int *class)
{
void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
@@ -1153,6 +1214,22 @@ static void ahci_error_handler(struct at
ahci_postreset);
}
+static void ahci_vt8251_error_handler(struct ata_port *ap)
+{
+ void __iomem *mmio = ap->host->mmio_base;
+ void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
+
+ if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
+ /* restart engine */
+ ahci_stop_engine(port_mmio);
+ ahci_start_engine(port_mmio);
+ }
+
+ /* perform recovery */
+ ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
+ ahci_postreset);
+}
+
static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
--
1.4.2.3
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] [PATCH] ahci: update softreset and kill AHCI_FLAG_RESET_NEEDS_CLO
2006-10-15 22:43 [PATCHSET] ahci updates regarding vt8251 support, take #2 Tejun Heo
@ 2006-10-15 22:43 ` Tejun Heo
2006-10-15 22:43 ` [PATCH 1/3] [PATCH] libata: separate out and export sata_port_hardreset() Tejun Heo
` (3 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Tejun Heo @ 2006-10-15 22:43 UTC (permalink / raw)
To: jgarzik, alan, aalderd.boac, linux-ide; +Cc: Tejun Heo
CLO is supposed to be automatically performed by ahci_softreset() if
BSY is set (AHCI rev1.1 10.4.1). Although the code was there, it
didn't work because Status value in D2H Reg area, which is zeroed on
initialization, was used to determine whether BSY is set.
This patch updates ahci_softreset() to use TFDATA area to determine
Status and kill now unnecessary AHCI_FLAG_RESET_NEEDS_CLO.
Signed-off-by: Tejun Heo <htejun@gmail.com>
---
drivers/ata/ahci.c | 22 ++++------------------
1 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index d95d99b..f103799 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -166,8 +166,7 @@ enum {
AHCI_FLAG_MSI = (1 << 0),
/* ap->flags bits */
- AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
- AHCI_FLAG_NO_NCQ = (1 << 25),
+ AHCI_FLAG_NO_NCQ = (1 << 24),
};
struct ahci_cmd_hdr {
@@ -291,8 +290,7 @@ static const struct ata_port_info ahci_p
.sht = &ahci_sht,
.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
- ATA_FLAG_SKIP_D2H_BSY |
- AHCI_FLAG_RESET_NEEDS_CLO | AHCI_FLAG_NO_NCQ,
+ ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_NO_NCQ,
.pio_mask = 0x1f, /* pio0-4 */
.udma_mask = 0x7f, /* udma0-6 ; FIXME */
.port_ops = &ahci_ops,
@@ -699,17 +697,6 @@ static int ahci_clo(struct ata_port *ap)
return 0;
}
-static int ahci_prereset(struct ata_port *ap)
-{
- if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
- (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
- /* ATA_BUSY hasn't cleared, so send a CLO */
- ahci_clo(ap);
- }
-
- return ata_std_prereset(ap);
-}
-
static int ahci_softreset(struct ata_port *ap, unsigned int *class)
{
struct ahci_port_priv *pp = ap->private_data;
@@ -738,8 +725,7 @@ static int ahci_softreset(struct ata_por
}
/* check BUSY/DRQ, perform Command List Override if necessary */
- ahci_tf_read(ap, &tf);
- if (tf.command & (ATA_BUSY | ATA_DRQ)) {
+ if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
rc = ahci_clo(ap);
if (rc == -EOPNOTSUPP) {
@@ -1163,7 +1149,7 @@ static void ahci_error_handler(struct at
}
/* perform recovery */
- ata_do_eh(ap, ahci_prereset, ahci_softreset, ahci_hardreset,
+ ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
ahci_postreset);
}
--
1.4.2.3
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 1/3] [PATCH] libata: separate out and export sata_port_hardreset()
2006-10-15 22:43 [PATCHSET] ahci updates regarding vt8251 support, take #2 Tejun Heo
2006-10-15 22:43 ` [PATCH 2/3] [PATCH] ahci: update softreset and kill AHCI_FLAG_RESET_NEEDS_CLO Tejun Heo
@ 2006-10-15 22:43 ` Tejun Heo
2006-10-15 22:43 ` [PATCH 3/3] [PATCH] ahci: update ahci-vt8251 reset sequence Tejun Heo
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Tejun Heo @ 2006-10-15 22:43 UTC (permalink / raw)
To: jgarzik, alan, aalderd.boac, linux-ide; +Cc: Tejun Heo
Separate out sata_port_hardreset() from sata_std_hardreset(). This
wil be used by LLD hardreset implementation and later by PMP.
Signed-off-by: Tejun Heo <htejun@gmail.com>
---
drivers/ata/libata-core.c | 52 ++++++++++++++++++++++++++++++++++++---------
include/linux/libata.h | 2 ++
2 files changed, 44 insertions(+), 10 deletions(-)
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 006ab12..519e616 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -2777,9 +2777,9 @@ int ata_std_softreset(struct ata_port *a
}
/**
- * sata_std_hardreset - reset host port via SATA phy reset
+ * sata_port_hardreset - reset port via SATA phy reset
* @ap: port to reset
- * @class: resulting class of attached device
+ * @timing: timing parameters { interval, duratinon, timeout } in msec
*
* SATA phy-reset host port using DET bits of SControl register.
*
@@ -2789,10 +2789,8 @@ int ata_std_softreset(struct ata_port *a
* RETURNS:
* 0 on success, -errno otherwise.
*/
-int sata_std_hardreset(struct ata_port *ap, unsigned int *class)
+int sata_port_hardreset(struct ata_port *ap, const unsigned long *timing)
{
- struct ata_eh_context *ehc = &ap->eh_context;
- const unsigned long *timing = sata_ehc_deb_timing(ehc);
u32 scontrol;
int rc;
@@ -2805,24 +2803,24 @@ int sata_std_hardreset(struct ata_port *
* and Sil3124.
*/
if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
- return rc;
+ goto out;
scontrol = (scontrol & 0x0f0) | 0x304;
if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
- return rc;
+ goto out;
sata_set_spd(ap);
}
/* issue phy wake/reset */
if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
- return rc;
+ goto out;
scontrol = (scontrol & 0x0f0) | 0x301;
if ((rc = sata_scr_write_flush(ap, SCR_CONTROL, scontrol)))
- return rc;
+ goto out;
/* Couldn't find anything in SATA I/II specs, but AHCI-1.1
* 10.4.2 says at least 1 ms.
@@ -2830,7 +2828,40 @@ int sata_std_hardreset(struct ata_port *
msleep(1);
/* bring phy back */
- sata_phy_resume(ap, timing);
+ rc = sata_phy_resume(ap, timing);
+ out:
+ DPRINTK("EXIT, rc=%d\n", rc);
+ return rc;
+}
+
+/**
+ * sata_std_hardreset - reset host port via SATA phy reset
+ * @ap: port to reset
+ * @class: resulting class of attached device
+ *
+ * SATA phy-reset host port using DET bits of SControl register,
+ * wait for !BSY and classify the attached device.
+ *
+ * LOCKING:
+ * Kernel thread context (may sleep)
+ *
+ * RETURNS:
+ * 0 on success, -errno otherwise.
+ */
+int sata_std_hardreset(struct ata_port *ap, unsigned int *class)
+{
+ const unsigned long *timing = sata_ehc_deb_timing(&ap->eh_context);
+ int rc;
+
+ DPRINTK("ENTER\n");
+
+ /* do hardreset */
+ rc = sata_port_hardreset(ap, timing);
+ if (rc) {
+ ata_port_printk(ap, KERN_ERR,
+ "COMRESET failed (errno=%d)\n", rc);
+ return rc;
+ }
/* TODO: phy layer with polling, timeouts, etc. */
if (ata_port_offline(ap)) {
@@ -6202,6 +6233,7 @@ EXPORT_SYMBOL_GPL(__sata_phy_reset);
EXPORT_SYMBOL_GPL(ata_bus_reset);
EXPORT_SYMBOL_GPL(ata_std_prereset);
EXPORT_SYMBOL_GPL(ata_std_softreset);
+EXPORT_SYMBOL_GPL(sata_port_hardreset);
EXPORT_SYMBOL_GPL(sata_std_hardreset);
EXPORT_SYMBOL_GPL(ata_std_postreset);
EXPORT_SYMBOL_GPL(sata_std_hp_poll_activate);
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 4fc74c4..832c500 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -708,6 +708,8 @@ extern int sata_phy_debounce(struct ata_
extern int sata_phy_resume(struct ata_port *ap, const unsigned long *param);
extern int ata_std_prereset(struct ata_port *ap);
extern int ata_std_softreset(struct ata_port *ap, unsigned int *classes);
+extern int sata_port_hardreset(struct ata_port *ap,
+ const unsigned long *timing);
extern int sata_std_hardreset(struct ata_port *ap, unsigned int *class);
extern void ata_std_postreset(struct ata_port *ap, unsigned int *classes);
extern void sata_std_hp_poll_activate(struct ata_port *ap);
--
1.4.2.3
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCHSET] ahci updates regarding vt8251 support, take #2
2006-10-15 22:43 [PATCHSET] ahci updates regarding vt8251 support, take #2 Tejun Heo
` (2 preceding siblings ...)
2006-10-15 22:43 ` [PATCH 3/3] [PATCH] ahci: update ahci-vt8251 reset sequence Tejun Heo
@ 2006-10-18 4:45 ` Aalderd Bouwman
2006-10-18 11:50 ` Tejun Heo
2006-10-21 19:23 ` Jeff Garzik
4 siblings, 1 reply; 9+ messages in thread
From: Aalderd Bouwman @ 2006-10-18 4:45 UTC (permalink / raw)
To: Tejun Heo; +Cc: jgarzik, alan, linux-ide
Hello Tejun,
I now have received the message in dmesg:
spurious 8259A interrupt: IRQ7.
What does it mean? And is it a problem for the properly working of the
system?
Aalderd.
On Mon, 2006-10-16 at 07:43 +0900, Tejun Heo wrote:
> Hello, all.
>
> This is the second take of vt8251-ahci patchset. This patchset
> updates libata and ahci to improve vt8251 EH and hotplug support.
>
> #01 : separate out sata_port_hardreset(), to be used by vt8251 reset
> #02 : update CLO handling in softreset and kill RESET_NEEDS_CLO
> #03 : update vt8251 support in ahci
>
> Changes from the last take[L] are
>
> * rebased over the current upstream + hp-poll
> * hp-poll callbacks added to ahci_vt8251_ops
>
> This patchset is against
> upstream (da54f5fe54c7d75e2db7d17961fb36a8c28a8501)
> + hp-poll patchset, take #5 [1]
>
> This patchset has been verified by me and Aalderd Bouwman
> <aalderd.boac@wanadoo.nl>.
>
> The git tree is avilable at
>
> http://htj.dyndns.org/git/?p=libata-tj.git;a=shortlog;h=vt8251-ahci
> git://htj.dyndns.org/libata-tj vt8251-ahci
>
> Thanks.
>
> --
> tejun
>
> [L] http://article.gmane.org/gmane.linux.ide/13449
> [1] http://article.gmane.org/gmane.linux.ide/13467
>
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCHSET] ahci updates regarding vt8251 support, take #2
2006-10-18 4:45 ` [PATCHSET] ahci updates regarding vt8251 support, take #2 Aalderd Bouwman
@ 2006-10-18 11:50 ` Tejun Heo
2006-10-18 17:02 ` Aalderd Bouwman
0 siblings, 1 reply; 9+ messages in thread
From: Tejun Heo @ 2006-10-18 11:50 UTC (permalink / raw)
To: aalderd.boac; +Cc: jgarzik, alan, linux-ide
Aalderd Bouwman wrote:
> Hello Tejun,
>
> I now have received the message in dmesg:
> spurious 8259A interrupt: IRQ7.
>
> What does it mean? And is it a problem for the properly working of the
> system?
Can you post full dmesg?
--
tejun
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCHSET] ahci updates regarding vt8251 support, take #2
2006-10-18 11:50 ` Tejun Heo
@ 2006-10-18 17:02 ` Aalderd Bouwman
0 siblings, 0 replies; 9+ messages in thread
From: Aalderd Bouwman @ 2006-10-18 17:02 UTC (permalink / raw)
To: Tejun Heo; +Cc: linux-ide
Oct 14 08:48:18 server 0: 0000000000100000 - 000000001f7b0000 (usable)
Oct 14 08:48:18 server BIOS-e820: 000000001f7b0000 - 000000001f7be000
(ACPI data)
Oct 14 08:48:18 server BIOS-e820: 000000001f7be000 - 000000001f7e0000
(ACPI NVS)
Oct 14 08:48:18 server BIOS-e820: 000000001f7e0000 - 000000001f800000
(reserved)
Oct 14 08:48:18 server BIOS-e820: 00000000e0000000 - 00000000f0000000
(reserved)
Oct 14 08:48:18 server BIOS-e820: 00000000fec00000 - 00000000fec01000
(reserved)
Oct 14 08:48:18 server BIOS-e820: 00000000ff7c0000 - 0000000100000000
(reserved)
Oct 14 08:48:18 server 503MB LOWMEM available.
Oct 14 08:48:18 server Entering add_active_range(0, 0, 128944) 0 entries
of 256 used
Oct 14 08:48:18 server Zone PFN ranges:
Oct 14 08:48:18 server DMA 0 -> 4096
Oct 14 08:48:18 server Normal 4096 -> 128944
Oct 14 08:48:18 server early_node_map[1] active PFN ranges
Oct 14 08:48:18 server 0: 0 -> 128944
Oct 14 08:48:18 server On node 0 totalpages: 128944
Oct 14 08:48:18 server DMA zone: 32 pages used for memmap
Oct 14 08:48:18 server DMA zone: 0 pages reserved
Oct 14 08:48:18 server DMA zone: 4064 pages, LIFO batch:0
Oct 14 08:48:18 server Normal zone: 975 pages used for memmap
Oct 14 08:48:18 server Normal zone: 123873 pages, LIFO batch:31
Oct 14 08:48:18 server DMI 2.3 present.
Oct 14 08:48:18 server ACPI: RSDP (v002
ACPIAM ) @ 0x000fac60
Oct 14 08:48:18 server ACPI: XSDT (v001 A M I OEMXSDT 0x09000505 MSFT
0x00000097) @ 0x1f7b0100
Oct 14 08:48:18 server ACPI: FADT (v003 A M I OEMFACP 0x09000505 MSFT
0x00000097) @ 0x1f7b0290
Oct 14 08:48:18 server ACPI: MADT (v001 A M I OEMAPIC 0x09000505 MSFT
0x00000097) @ 0x1f7b0390
Oct 14 08:48:18 server ACPI: OEMB (v001 A M I AMI_OEM 0x09000505 MSFT
0x00000097) @ 0x1f7be040
Oct 14 08:48:18 server ACPI: DSDT (v001 A0347 A0347001 0x00000001 INTL
0x02002026) @ 0x00000000
Oct 14 08:48:18 server ACPI: PM-Timer IO Port: 0x808
Oct 14 08:48:18 server Allocating PCI resources starting at 20000000
(gap: 1f800000:c0800000)
Oct 14 08:48:18 server Detected 1800.130 MHz processor.
Oct 14 08:48:18 server Built 1 zonelists. Total pages: 127937
Oct 14 08:48:18 server Kernel command line: root=/dev/sda3
Oct 14 08:48:18 server Enabling fast FPU save and restore... done.
Oct 14 08:48:18 server Enabling unmasked SIMD FPU exception support...
done.
Oct 14 08:48:18 server Initializing CPU#0
Oct 14 08:48:18 server PID hash table entries: 2048 (order: 11, 8192
bytes)
Oct 14 08:48:18 server Console: colour VGA+ 80x25
Oct 14 08:48:18 server Dentry cache hash table entries: 65536 (order: 6,
262144 bytes)
Oct 14 08:48:18 server Inode-cache hash table entries: 32768 (order: 5,
131072 bytes)
Oct 14 08:48:18 server Memory: 507932k/515776k available (1895k kernel
code, 7356k reserved, 712k data, 136k init,
0k highmem)
Oct 14 08:48:18 server virtual kernel memory layout:
Oct 14 08:48:18 server fixmap : 0xffff8000 - 0xfffff000 ( 28 kB)
Oct 14 08:48:18 server vmalloc : 0xe0000000 - 0xffff6000 ( 511 MB)
Oct 14 08:48:18 server lowmem : 0xc0000000 - 0xdf7b0000 ( 503 MB)
Oct 14 08:48:18 server .init : 0xc038e000 - 0xc03b0000 ( 136 kB)
Oct 14 08:48:18 server .data : 0xc02d9d36 - 0xc038beec ( 712 kB)
Oct 14 08:48:18 server .text : 0xc0100000 - 0xc02d9d36 (1895 kB)
Oct 14 08:48:18 server Checking if this processor honours the WP bit
even in supervisor mode... Ok.
Oct 14 08:48:18 server Calibrating delay using timer specific routine..
3602.34 BogoMIPS (lpj=7204688)
Oct 14 08:48:18 server Mount-cache hash table entries: 512
Oct 14 08:48:18 server CPU: After generic identify, caps: 078bfbff
e3d3fbff 00000000 00000000 00000001 00000000 00000001
Oct 14 08:48:18 server CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K
(64 bytes/line)
Oct 14 08:48:18 server CPU: L2 Cache: 1024K (64 bytes/line)
Oct 14 08:48:18 server CPU: After all inits, caps: 078bfbff e3d3fbff
00000000 00000410 00000001 00000000 00000001
Oct 14 08:48:18 server Intel machine check architecture supported.
Oct 14 08:48:18 server Intel machine check reporting enabled on CPU#0.
Oct 14 08:48:18 server Compat vDSO mapped to ffffe000.
Oct 14 08:48:18 server CPU: AMD Opteron(tm) Processor 144 stepping 01
Oct 14 08:48:18 server Checking 'hlt' instruction... OK.
Oct 14 08:48:18 server ACPI: Core revision 20060707
Oct 14 08:48:18 server ACPI: setting ELCR to 0200 (from 0c28)
Oct 14 08:48:18 server NET: Registered protocol family 16
Oct 14 08:48:18 server ACPI: bus type pci registered
Oct 14 08:48:18 server PCI: PCI BIOS revision 3.00 entry at 0xf0031,
last bus=4
Oct 14 08:48:18 server PCI: Using configuration type 1
Oct 14 08:48:18 server Setting up standard PCI resources
Oct 14 08:48:18 server ACPI: Interpreter enabled
Oct 14 08:48:18 server ACPI: Using PIC for interrupt routing
Oct 14 08:48:18 server ACPI: PCI Root Bridge [PCI0] (0000:00)
Oct 14 08:48:18 server PCI: Probing PCI hardware (bus 00)
Oct 14 08:48:18 server Boot video device is 0000:01:00.0
Oct 14 08:48:18 server ACPI: PCI Interrupt Routing Table
[\_SB_.PCI0._PRT]
Oct 14 08:48:18 server ACPI: PCI Interrupt Routing Table
[\_SB_.PCI0.P0P1._PRT]
Oct 14 08:48:18 server ACPI: PCI Interrupt Routing Table
[\_SB_.PCI0.P0P7._PRT]
Oct 14 08:48:18 server ACPI: PCI Interrupt Routing Table
[\_SB_.PCI0.P0P7.P7P9._PRT]
Oct 14 08:48:18 server ACPI: PCI Interrupt Routing Table
[\_SB_.PCI0.P0P7.P7P8._PRT]
Oct 14 08:48:18 server ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7
10 *11 12 14 15)
Oct 14 08:48:18 server ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7
*10 11 12 14 15)
Oct 14 08:48:18 server ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 7
10 11 12 14 15)
Oct 14 08:48:18 server ACPI: PCI Interrupt Link [LNKD] (IRQs *3 4 5 6 7
10 11 12 14 15)
Oct 14 08:48:18 server ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7
10 11 12 14 15) *0, disabled.
Oct 14 08:48:18 server ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7
10 11 12 14 15) *0, disabled.
Oct 14 08:48:18 server ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7
10 11 12 14 15) *0, disabled.
Oct 14 08:48:18 server ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7
10 11 12 14 15) *0, disabled.
Oct 14 08:48:18 server Linux Plug and Play Support v0.97 (c) Adam Belay
Oct 14 08:48:18 server pnp: PnP ACPI init
Oct 14 08:48:18 server pnp: PnP ACPI: found 13 devices
Oct 14 08:48:18 server SCSI subsystem initialized
Oct 14 08:48:18 server usbcore: registered new interface driver usbfs
Oct 14 08:48:18 server usbcore: registered new interface driver hub
Oct 14 08:48:18 server usbcore: registered new device driver usb
Oct 14 08:48:18 server PCI: Using ACPI for IRQ routing
Oct 14 08:48:18 server PCI: If a device doesn't work, try
"pci=routeirq". If it helps, post a report
Oct 14 08:48:18 server pnp: 00:07: ioport range 0x290-0x297 has been
reserved
Oct 14 08:48:18 server PCI: Bridge: 0000:00:01.0
Oct 14 08:48:18 server IO window: disabled.
Oct 14 08:48:18 server MEM window: fca00000-feafffff
Oct 14 08:48:18 server PREFETCH window: cff00000-d7efffff
Oct 14 08:48:18 server PCI: Bridge: 0000:02:00.0
Oct 14 08:48:18 server IO window: disabled.
Oct 14 08:48:18 server MEM window: disabled.
Oct 14 08:48:18 server PREFETCH window: disabled.
Oct 14 08:48:18 server PCI: Bridge: 0000:02:00.1
Oct 14 08:48:18 server IO window: disabled.
Oct 14 08:48:18 server MEM window: disabled.
Oct 14 08:48:18 server PREFETCH window: disabled.
Oct 14 08:48:18 server PCI: Bridge: 0000:00:13.0
Oct 14 08:48:18 server IO window: disabled.
Oct 14 08:48:18 server MEM window: disabled.
Oct 14 08:48:18 server PREFETCH window: disabled.
Oct 14 08:48:18 server PCI: Setting latency timer of device 0000:00:01.0
to 64
Oct 14 08:48:18 server PCI: Setting latency timer of device 0000:00:13.0
to 64
Oct 14 08:48:18 server PCI: Setting latency timer of device 0000:02:00.0
to 64
Oct 14 08:48:18 server PCI: Setting latency timer of device 0000:02:00.1
to 64
Oct 14 08:48:18 server NET: Registered protocol family 2
Oct 14 08:48:18 server IP route cache hash table entries: 4096 (order:
2, 16384 bytes)
Oct 14 08:48:18 server TCP established hash table entries: 16384 (order:
4, 65536 bytes)
Oct 14 08:48:18 server TCP bind hash table entries: 8192 (order: 3,
32768 bytes)
Oct 14 08:48:18 server TCP: Hash tables configured (established 16384
bind 8192)
Oct 14 08:48:18 server TCP reno registered
Oct 14 08:48:18 server Machine check exception polling timer started.
Oct 14 08:48:18 server audit: initializing netlink socket (disabled)
Oct 14 08:48:18 server audit(1160815666.396:1): initialized
Oct 14 08:48:18 server Installing knfsd (copyright (C) 1996
okir@monad.swb.de).
Oct 14 08:48:18 server io scheduler noop registered
Oct 14 08:48:18 server io scheduler anticipatory registered (default)
Oct 14 08:48:18 server io scheduler deadline registered
Oct 14 08:48:18 server io scheduler cfq registered
Oct 14 08:48:18 server ACPI: Power Button (FF) [PWRF]
Oct 14 08:48:18 server ACPI: Sleep Button (CM) [SLPB]
Oct 14 08:48:18 server ACPI: Power Button (CM) [PWRB]
Oct 14 08:48:18 server ACPI: Processor [CPU1] (supports 16 throttling
states)
Oct 14 08:48:18 server ACPI: Getting cpuindex for acpiid 0x2
Oct 14 08:48:18 server Serial: 8250/16550 driver $Revision: 1.90 $ 4
ports, IRQ sharing disabled
Oct 14 08:48:18 server serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a
16550A
Oct 14 08:48:18 server 00:0a: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
Oct 14 08:48:18 server Floppy drive(s): fd0 is 1.44M
Oct 14 08:48:18 server FDC 0 is a post-1991 82077
Oct 14 08:48:18 server via-rhine.c:v1.10-LK1.4.2 Sept-11-2006 Written by
Donald Becker
Oct 14 08:48:18 server ACPI: PCI Interrupt Link [LNKA] enabled at IRQ 11
Oct 14 08:48:18 server PCI: setting IRQ 11 as level-triggered
Oct 14 08:48:18 server ACPI: PCI Interrupt 0000:00:12.0[A] -> Link
[LNKA] -> GSI 11 (level, low) -> IRQ 11
Oct 14 08:48:18 server eth0: VIA Rhine II at 0xfebff000,
00:13:d4:a7:82:e5, IRQ 11.
Oct 14 08:48:18 server eth0: MII PHY found at address 1, status 0x786d
advertising 01e1 Link 41e1.
Oct 14 08:48:18 server Uniform Multi-Platform E-IDE driver Revision:
7.00alpha2
Oct 14 08:48:18 server ide: Assuming 33MHz system bus speed for PIO
modes; override with idebus=xx
Oct 14 08:48:18 server VP_IDE: IDE controller at PCI slot 0000:00:0f.1
Oct 14 08:48:18 server PCI: VIA IRQ fixup for 0000:00:0f.1, from 255 to
0
Oct 14 08:48:18 server VP_IDE: chipset revision 7
Oct 14 08:48:18 server VP_IDE: not 100% native mode: will probe irqs
later
Oct 14 08:48:18 server VP_IDE: VIA vt8251 (rev 00) IDE UDMA133
controller on pci0000:00:0f.1
Oct 14 08:48:18 server ide0: BM-DMA at 0xfc00-0xfc07, BIOS settings:
hda:pio, hdb:DMA
Oct 14 08:48:18 server ide1: BM-DMA at 0xfc08-0xfc0f, BIOS settings:
hdc:DMA, hdd:pio
Oct 14 08:48:18 server Probing IDE interface ide0...
Oct 14 08:48:18 server hdb: Pioneer DVD-ROM ATAPIModel DVD-104S 012,
ATAPI CD/DVD-ROM drive
Oct 14 08:48:18 server ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
Oct 14 08:48:18 server Probing IDE interface ide1...
Oct 14 08:48:18 server hdc: ST3160021A, ATA DISK drive
Oct 14 08:48:18 server ide1 at 0x170-0x177,0x376 on irq 15
Oct 14 08:48:18 server hdc: max request size: 512KiB
Oct 14 08:48:18 server hdc: 312581808 sectors (160041 MB) w/2048KiB
Cache, CHS=19457/255/63, UDMA(100)
Oct 14 08:48:18 server hdc: cache flushes supported
Oct 14 08:48:18 server hdc: hdc1 hdc2 < hdc5 hdc6 hdc7 hdc8 hdc9 >
Oct 14 08:48:18 server hdb: ATAPI DVD-ROM drive, 512kB Cache, UDMA(33)
Oct 14 08:48:18 server Uniform CD-ROM driver Revision: 3.20
Oct 14 08:48:18 server libata version 2.00 loaded.
Oct 14 08:48:18 server ahci 0000:00:0f.0: version 2.0
Oct 14 08:48:18 server ACPI: PCI Interrupt Link [LNKB] enabled at IRQ 10
Oct 14 08:48:18 server PCI: setting IRQ 10 as level-triggered
Oct 14 08:48:18 server ACPI: PCI Interrupt 0000:00:0f.0[B] -> Link
[LNKB] -> GSI 10 (level, low) -> IRQ 10
Oct 14 08:48:18 server ahci 0000:00:0f.0: AHCI 0001.0000 32 slots 4
ports 3 Gbps 0xf impl SATA mode
Oct 14 08:48:18 server ahci 0000:00:0f.0: flags: 64bit ncq pm led clo
pmp pio slum part
Oct 14 08:48:18 server ata1: SATA max UDMA/133 cmd 0xE0006D00 ctl 0x0
bmdma 0x0 irq 10
Oct 14 08:48:18 server ata2: SATA max UDMA/133 cmd 0xE0006D80 ctl 0x0
bmdma 0x0 irq 10
Oct 14 08:48:18 server ata3: SATA max UDMA/133 cmd 0xE0006E00 ctl 0x0
bmdma 0x0 irq 10
Oct 14 08:48:18 server ata4: SATA max UDMA/133 cmd 0xE0006E80 ctl 0x0
bmdma 0x0 irq 10
Oct 14 08:48:18 server scsi0 : ahci
Oct 14 08:48:18 server ata1: SATA link up 3.0 Gbps (SStatus 123 SControl
300)
Oct 14 08:48:18 server ata1.00: ATA-7, max UDMA/133, 156301488 sectors:
LBA48 NCQ (depth 0/32)
Oct 14 08:48:18 server ata1.00: ata1: dev 0 multi count 16
Oct 14 08:48:18 server ata1.00: configured for UDMA/133
Oct 14 08:48:18 server scsi1 : ahci
Oct 14 08:48:18 server ata2: SATA link down (SStatus 0 SControl 300)
Oct 14 08:48:18 server scsi2 : ahci
Oct 14 08:48:18 server ata3: SATA link down (SStatus 0 SControl 300)
Oct 14 08:48:18 server scsi3 : ahci
Oct 14 08:48:18 server ata4: SATA link down (SStatus 0 SControl 300)
Oct 14 08:48:18 server scsi 0:0:0:0: Direct-Access ATA
ST3808110AS 3.AA PQ: 0 ANSI: 5
Oct 14 08:48:18 server SCSI device sda: 156301488 512-byte hdwr sectors
(80026 MB)
Oct 14 08:48:18 server sda: Write Protect is off
Oct 14 08:48:18 server sda: Mode Sense: 00 3a 00 00
Oct 14 08:48:18 server SCSI device sda: drive cache: write back
Oct 14 08:48:18 server SCSI device sda: 156301488 512-byte hdwr sectors
(80026 MB)
Oct 14 08:48:18 server sda: Write Protect is off
Oct 14 08:48:18 server sda: Mode Sense: 00 3a 00 00
Oct 14 08:48:18 server SCSI device sda: drive cache: write back
Oct 14 08:48:18 server sda: sda1 sda2 sda3 sda4 < sda5 sda6 sda7 >
Oct 14 08:48:18 server sd 0:0:0:0: Attached scsi disk sda
Oct 14 08:48:18 server sd 0:0:0:0: Attached scsi generic sg0 type 0
Oct 14 08:48:18 server ACPI: PCI Interrupt Link [LNKC] enabled at IRQ 5
Oct 14 08:48:18 server PCI: setting IRQ 5 as level-triggered
Oct 14 08:48:18 server ACPI: PCI Interrupt 0000:00:10.4[C] -> Link
[LNKC] -> GSI 5 (level, low) -> IRQ 5
Oct 14 08:48:18 server ehci_hcd 0000:00:10.4: EHCI Host Controller
Oct 14 08:48:18 server ehci_hcd 0000:00:10.4: new USB bus registered,
assigned bus number 1
Oct 14 08:48:18 server ehci_hcd 0000:00:10.4: debug port 1
Oct 14 08:48:18 server ehci_hcd 0000:00:10.4: irq 5, io mem 0xfebff400
Oct 14 08:48:18 server ehci_hcd 0000:00:10.4: USB 2.0 started, EHCI
1.00, driver 10 Dec 2004
Oct 14 08:48:18 server usb usb1: configuration #1 chosen from 1 choice
Oct 14 08:48:18 server hub 1-0:1.0: USB hub found
Oct 14 08:48:18 server hub 1-0:1.0: 8 ports detected
Oct 14 08:48:18 server USB Universal Host Controller Interface driver
v3.0
Oct 14 08:48:18 server ACPI: PCI Interrupt 0000:00:10.0[A] -> Link
[LNKA] -> GSI 11 (level, low) -> IRQ 11
Oct 14 08:48:18 server uhci_hcd 0000:00:10.0: UHCI Host Controller
Oct 14 08:48:18 server uhci_hcd 0000:00:10.0: new USB bus registered,
assigned bus number 2
Oct 14 08:48:18 server uhci_hcd 0000:00:10.0: irq 11, io base 0x0000e000
Oct 14 08:48:18 server usb usb2: configuration #1 chosen from 1 choice
Oct 14 08:48:18 server hub 2-0:1.0: USB hub found
Oct 14 08:48:18 server hub 2-0:1.0: 2 ports detected
Oct 14 08:48:18 server ACPI: PCI Interrupt 0000:00:10.1[C] -> Link
[LNKC] -> GSI 5 (level, low) -> IRQ 5
Oct 14 08:48:18 server uhci_hcd 0000:00:10.1: UHCI Host Controller
Oct 14 08:48:18 server uhci_hcd 0000:00:10.1: new USB bus registered,
assigned bus number 3
Oct 14 08:48:18 server uhci_hcd 0000:00:10.1: irq 5, io base 0x0000dc00
Oct 14 08:48:18 server usb usb3: configuration #1 chosen from 1 choice
Oct 14 08:48:18 server hub 3-0:1.0: USB hub found
Oct 14 08:48:18 server hub 3-0:1.0: 2 ports detected
Oct 14 08:48:18 server ACPI: PCI Interrupt 0000:00:10.2[B] -> Link
[LNKB] -> GSI 10 (level, low) -> IRQ 10
Oct 14 08:48:18 server uhci_hcd 0000:00:10.2: UHCI Host Controller
Oct 14 08:48:18 server uhci_hcd 0000:00:10.2: new USB bus registered,
assigned bus number 4
Oct 14 08:48:18 server uhci_hcd 0000:00:10.2: irq 10, io base 0x0000d880
Oct 14 08:48:18 server usb usb4: configuration #1 chosen from 1 choice
Oct 14 08:48:18 server hub 4-0:1.0: USB hub found
Oct 14 08:48:18 server hub 4-0:1.0: 2 ports detected
Oct 14 08:48:18 server ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 3
Oct 14 08:48:18 server PCI: setting IRQ 3 as level-triggered
Oct 14 08:48:18 server ACPI: PCI Interrupt 0000:00:10.3[D] -> Link
[LNKD] -> GSI 3 (level, low) -> IRQ 3
Oct 14 08:48:18 server uhci_hcd 0000:00:10.3: UHCI Host Controller
Oct 14 08:48:18 server uhci_hcd 0000:00:10.3: new USB bus registered,
assigned bus number 5
Oct 14 08:48:18 server uhci_hcd 0000:00:10.3: irq 3, io base 0x0000d800
Oct 14 08:48:18 server usb usb5: configuration #1 chosen from 1 choice
Oct 14 08:48:18 server hub 5-0:1.0: USB hub found
Oct 14 08:48:18 server hub 5-0:1.0: 2 ports detected
Oct 14 08:48:18 server Initializing USB Mass Storage driver...
Oct 14 08:48:18 server usbcore: registered new interface driver
usb-storage
Oct 14 08:48:18 server USB Mass Storage support registered.
Oct 14 08:48:18 server PNP: No PS/2 controller found. Probing ports
directly.
Oct 14 08:48:18 server serio: i8042 KBD port at 0x60,0x64 irq 1
Oct 14 08:48:18 server serio: i8042 AUX port at 0x60,0x64 irq 12
Oct 14 08:48:18 server mice: PS/2 mouse device common for all mice
Oct 14 08:48:18 server input: PC Speaker as /class/input/input0
Oct 14 08:48:18 server ip_conntrack version 2.4 (4029 buckets, 32232
max) - 212 bytes per conntrack
Oct 14 08:48:18 server TCP cubic registered
Oct 14 08:48:18 server NET: Registered protocol family 1
Oct 14 08:48:18 server NET: Registered protocol family 17
Oct 14 08:48:18 server Using IPI Shortcut mode
Oct 14 08:48:18 server ACPI: (supports S0 S1 S3 S4 S5)
Oct 14 08:48:18 server Time: tsc clocksource has been installed.
<snip> FS mount - dmesg </snip>
Oct 14 08:48:18 server ACPI: PCI Interrupt 0000:00:0c.0[A] -> Link
[LNKB] -> GSI 10 (level, low) -> IRQ 10
Oct 14 08:48:18 server 3c59x: Donald Becker and others.
www.scyld.com/network/vortex.html
Oct 14 08:48:18 server 0000:00:0c.0: 3Com PCI 3c905B Cyclone 100baseTx
at e00c0800.
<snip> FS mount - dmesg </snip>
The dmesg when turning the drive on/of is already posted
Spurious part:
Oct 18 06:34:34 server xinetd[5919]: START: vmware-authd pid=19719
from=xx.xx.xx.xx
Oct 18 06:34:34 server vmware-authd[19719]: login from xx.xx.xx.xx as
aalderd
Oct 18 06:34:35 server spurious 8259A interrupt: IRQ7.
Oct 18 06:34:36 server xinetd[5919]: EXIT: vmware-authd status=0
pid=19719 duration=2(sec)
Oct 18 06:34:52 server vmware-authd[19752]: The
"/opt/vmware/server/lib/bin/vmware-vmx" process did not start properly.
Exit 0x100
Oct 18 06:35:05 server vmware-authd[19766]: The
"/opt/vmware/server/lib/bin/vmware-vmx" process did not start properly.
Exit 0x100
Oct 18 06:36:23 server vmware-authd[19770]: The
"/opt/vmware/server/lib/bin/vmware-vmx" process did not start properly.
Exit 0x100
As you see it happened when I start a vmware-server-session.
The vmware-server-session failed due the missed vmware-modules by the
way.
Aalderd
On Wed, 2006-10-18 at 20:50 +0900, Tejun Heo wrote:
> Aalderd Bouwman wrote:
> > Hello Tejun,
> >
> > I now have received the message in dmesg:
> > spurious 8259A interrupt: IRQ7.
> >
> > What does it mean? And is it a problem for the properly working of the
> > system?
>
> Can you post full dmesg?
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCHSET] ahci updates regarding vt8251 support, take #2
2006-10-15 22:43 [PATCHSET] ahci updates regarding vt8251 support, take #2 Tejun Heo
` (3 preceding siblings ...)
2006-10-18 4:45 ` [PATCHSET] ahci updates regarding vt8251 support, take #2 Aalderd Bouwman
@ 2006-10-21 19:23 ` Jeff Garzik
2006-10-23 2:29 ` Tejun Heo
4 siblings, 1 reply; 9+ messages in thread
From: Jeff Garzik @ 2006-10-21 19:23 UTC (permalink / raw)
To: Tejun Heo; +Cc: alan, aalderd.boac, linux-ide
Patchset looks OK to me, with a few notes:
1) might want to separate out this change and forward it to #upstream-fixes:
- ahci_tf_read(ap, &tf);
- if (tf.command & (ATA_BUSY | ATA_DRQ)) {
+ if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
2) In general, it's a good idea to clear SError after twiddling with the
phy. Not just on vt8521.
3) Any positive test results yet?
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCHSET] ahci updates regarding vt8251 support, take #2
2006-10-21 19:23 ` Jeff Garzik
@ 2006-10-23 2:29 ` Tejun Heo
0 siblings, 0 replies; 9+ messages in thread
From: Tejun Heo @ 2006-10-23 2:29 UTC (permalink / raw)
To: Jeff Garzik; +Cc: alan, aalderd.boac, linux-ide
Hello, Jeff.
Jeff Garzik wrote:
> Patchset looks OK to me, with a few notes:
>
> 1) might want to separate out this change and forward it to
> #upstream-fixes:
> - ahci_tf_read(ap, &tf);
> - if (tf.command & (ATA_BUSY | ATA_DRQ)) {
> + if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
Okay, will do that.
> 2) In general, it's a good idea to clear SError after twiddling with the
> phy. Not just on vt8521.
It's done in ->post_reset() after a successful soft/hard reset, so the
issue occurs only when the controller needs follow-up SRST after
hardreset and the softreset doesn't work unless SError isn't cleared.
And, vt8251 is the only such controller at the moment (heh heh
surprise!), so I think we can leave it there for the time being.
> 3) Any positive test results yet?
Aalderd confirmed the change. He has reported a spurious IRQ problem
but it's emitted when loading vmware modules and doesn't seem to be
related to libata at all. My vt8251 also does hotplug happily with the
change, so we have two positive test results.
Thanks.
--
tejun
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2006-10-23 2:29 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2006-10-15 22:43 [PATCHSET] ahci updates regarding vt8251 support, take #2 Tejun Heo
2006-10-15 22:43 ` [PATCH 2/3] [PATCH] ahci: update softreset and kill AHCI_FLAG_RESET_NEEDS_CLO Tejun Heo
2006-10-15 22:43 ` [PATCH 1/3] [PATCH] libata: separate out and export sata_port_hardreset() Tejun Heo
2006-10-15 22:43 ` [PATCH 3/3] [PATCH] ahci: update ahci-vt8251 reset sequence Tejun Heo
2006-10-18 4:45 ` [PATCHSET] ahci updates regarding vt8251 support, take #2 Aalderd Bouwman
2006-10-18 11:50 ` Tejun Heo
2006-10-18 17:02 ` Aalderd Bouwman
2006-10-21 19:23 ` Jeff Garzik
2006-10-23 2:29 ` Tejun Heo
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