From: Jens Axboe <jens.axboe@oracle.com>
To: Peer Chen <peerchen@gmail.com>
Cc: linux-kernel <linux-kernel@vger.kernel.org>,
jeff <jeff@garzik.org>, akpm <akpm@linux-foundation.org>,
linux-ide <linux-ide@vger.kernel.org>
Subject: Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR
Date: Fri, 21 Sep 2007 12:31:20 +0200 [thread overview]
Message-ID: <20070921103120.GK2367@kernel.dk> (raw)
In-Reply-To: <200709211327569648280@gmail.com>
On Fri, Sep 21 2007, Peer Chen wrote:
> According to the description of section 5.2.2.1 and 10.1.2 of AHCI specification rev1_1/rev1_2, GHC.HR shall only be set to ¡®1¡¯
> by software when GHC.AE is set to ¡®1¡¯.
>
> Signed-off-by: Peer Chen <peerchen@gmail.com>
> ---
> --- linux-2.6.23-rc7/drivers/ata/ahci.c.orig 2007-09-20 11:01:55.000000000 -0400
> +++ linux-2.6.23-rc7/drivers/ata/ahci.c 2007-09-20 11:07:31.000000000 -0400
> @@ -834,6 +834,10 @@ static int ahci_reset_controller(struct
> void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
> u32 tmp;
>
> + /* turn on AHCI mode before controller reset*/
> + writel(HOST_AHCI_EN, mmio + HOST_CTL);
> + (void) readl(mmio + HOST_CTL); /* flush */
> +
> /* global controller reset */
> tmp = readl(mmio + HOST_CTL);
> if ((tmp & HOST_RESET) == 0) {
I appreciate the readl() flushes, but in this particular case we end up
reading the exact offset again below.
--
Jens Axboe
next prev parent reply other threads:[~2007-09-21 10:30 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-09-21 5:28 [PATCH] ahci: enable GHC.AE bit before set GHC.HR Peer Chen
2007-09-21 10:29 ` Andrew Morton
2007-09-21 10:31 ` Jens Axboe [this message]
2007-09-21 11:27 ` Alan Cox
2007-09-21 11:34 ` Jens Axboe
2007-09-26 4:03 ` Jeff Garzik
2007-09-26 11:23 ` Alan Cox
2007-09-26 11:41 ` Jeff Garzik
2007-09-26 14:30 ` Alan Cox
2007-09-26 14:33 ` Jeff Garzik
2007-09-26 16:10 ` Alan Cox
2007-09-26 16:20 ` Jeff Garzik
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