* [PATCH] ahci: enable GHC.AE bit before set GHC.HR
@ 2007-09-21 5:28 Peer Chen
2007-09-21 10:29 ` Andrew Morton
` (2 more replies)
0 siblings, 3 replies; 12+ messages in thread
From: Peer Chen @ 2007-09-21 5:28 UTC (permalink / raw)
To: linux-kernel; +Cc: jeff, akpm, linux-ide
According to the description of section 5.2.2.1 and 10.1.2 of AHCI specification rev1_1/rev1_2, GHC.HR shall only be set to ¡®1¡¯
by software when GHC.AE is set to ¡®1¡¯.
Signed-off-by: Peer Chen <peerchen@gmail.com>
---
--- linux-2.6.23-rc7/drivers/ata/ahci.c.orig 2007-09-20 11:01:55.000000000 -0400
+++ linux-2.6.23-rc7/drivers/ata/ahci.c 2007-09-20 11:07:31.000000000 -0400
@@ -834,6 +834,10 @@ static int ahci_reset_controller(struct
void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
u32 tmp;
+ /* turn on AHCI mode before controller reset*/
+ writel(HOST_AHCI_EN, mmio + HOST_CTL);
+ (void) readl(mmio + HOST_CTL); /* flush */
+
/* global controller reset */
tmp = readl(mmio + HOST_CTL);
if ((tmp & HOST_RESET) == 0) {
-
--------------
Peer Chen
2007-09-21
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR
2007-09-21 5:28 [PATCH] ahci: enable GHC.AE bit before set GHC.HR Peer Chen
@ 2007-09-21 10:29 ` Andrew Morton
2007-09-21 10:31 ` Jens Axboe
2007-09-26 4:03 ` Jeff Garzik
2 siblings, 0 replies; 12+ messages in thread
From: Andrew Morton @ 2007-09-21 10:29 UTC (permalink / raw)
To: Peer Chen; +Cc: linux-kernel, jeff, linux-ide
On Fri, 21 Sep 2007 13:28:01 +0800 "Peer Chen" <peerchen@gmail.com> wrote:
> According to the description of section 5.2.2.1 and 10.1.2 of AHCI specification rev1_1/rev1_2, GHC.HR shall only be set to __1__
> by software when GHC.AE is set to __1__.
This text contained non-ascii garbage which came through as __1__.
I'll assume that you actually meant "1".
> --- linux-2.6.23-rc7/drivers/ata/ahci.c.orig 2007-09-20 11:01:55.000000000 -0400
> +++ linux-2.6.23-rc7/drivers/ata/ahci.c 2007-09-20 11:07:31.000000000 -0400
> @@ -834,6 +834,10 @@ static int ahci_reset_controller(struct
> void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
> u32 tmp;
>
> + /* turn on AHCI mode before controller reset*/
> + writel(HOST_AHCI_EN, mmio + HOST_CTL);
> + (void) readl(mmio + HOST_CTL); /* flush */
> +
> /* global controller reset */
> tmp = readl(mmio + HOST_CTL);
> if ((tmp & HOST_RESET) == 0) {
>
We don't normally do that (void) cast.
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR
2007-09-21 5:28 [PATCH] ahci: enable GHC.AE bit before set GHC.HR Peer Chen
2007-09-21 10:29 ` Andrew Morton
@ 2007-09-21 10:31 ` Jens Axboe
2007-09-21 11:27 ` Alan Cox
2007-09-26 4:03 ` Jeff Garzik
2 siblings, 1 reply; 12+ messages in thread
From: Jens Axboe @ 2007-09-21 10:31 UTC (permalink / raw)
To: Peer Chen; +Cc: linux-kernel, jeff, akpm, linux-ide
On Fri, Sep 21 2007, Peer Chen wrote:
> According to the description of section 5.2.2.1 and 10.1.2 of AHCI specification rev1_1/rev1_2, GHC.HR shall only be set to ¡®1¡¯
> by software when GHC.AE is set to ¡®1¡¯.
>
> Signed-off-by: Peer Chen <peerchen@gmail.com>
> ---
> --- linux-2.6.23-rc7/drivers/ata/ahci.c.orig 2007-09-20 11:01:55.000000000 -0400
> +++ linux-2.6.23-rc7/drivers/ata/ahci.c 2007-09-20 11:07:31.000000000 -0400
> @@ -834,6 +834,10 @@ static int ahci_reset_controller(struct
> void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
> u32 tmp;
>
> + /* turn on AHCI mode before controller reset*/
> + writel(HOST_AHCI_EN, mmio + HOST_CTL);
> + (void) readl(mmio + HOST_CTL); /* flush */
> +
> /* global controller reset */
> tmp = readl(mmio + HOST_CTL);
> if ((tmp & HOST_RESET) == 0) {
I appreciate the readl() flushes, but in this particular case we end up
reading the exact offset again below.
--
Jens Axboe
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR
2007-09-21 10:31 ` Jens Axboe
@ 2007-09-21 11:27 ` Alan Cox
2007-09-21 11:34 ` Jens Axboe
0 siblings, 1 reply; 12+ messages in thread
From: Alan Cox @ 2007-09-21 11:27 UTC (permalink / raw)
To: Jens Axboe; +Cc: Peer Chen, linux-kernel, jeff, akpm, linux-ide
On Fri, 21 Sep 2007 12:31:20 +0200
Jens Axboe <jens.axboe@oracle.com> wrote:
> On Fri, Sep 21 2007, Peer Chen wrote:
> > According to the description of section 5.2.2.1 and 10.1.2 of AHCI specification rev1_1/rev1_2, GHC.HR shall only be set to ¡®1¡¯
> > by software when GHC.AE is set to ¡®1¡¯.
> >
> > Signed-off-by: Peer Chen <peerchen@gmail.com>
> > ---
> > --- linux-2.6.23-rc7/drivers/ata/ahci.c.orig 2007-09-20 11:01:55.000000000 -0400
> > +++ linux-2.6.23-rc7/drivers/ata/ahci.c 2007-09-20 11:07:31.000000000 -0400
> > @@ -834,6 +834,10 @@ static int ahci_reset_controller(struct
> > void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
> > u32 tmp;
> >
> > + /* turn on AHCI mode before controller reset*/
> > + writel(HOST_AHCI_EN, mmio + HOST_CTL);
> > + (void) readl(mmio + HOST_CTL); /* flush */
> > +
> > /* global controller reset */
> > tmp = readl(mmio + HOST_CTL);
> > if ((tmp & HOST_RESET) == 0) {
>
> I appreciate the readl() flushes, but in this particular case we end up
> reading the exact offset again below.
The code above is wrong btw - it is an iomap so both the new and existing
code should be using ioread* not readl
Alan
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR
2007-09-21 11:27 ` Alan Cox
@ 2007-09-21 11:34 ` Jens Axboe
0 siblings, 0 replies; 12+ messages in thread
From: Jens Axboe @ 2007-09-21 11:34 UTC (permalink / raw)
To: Alan Cox; +Cc: Peer Chen, linux-kernel, jeff, akpm, linux-ide
On Fri, Sep 21 2007, Alan Cox wrote:
> On Fri, 21 Sep 2007 12:31:20 +0200
> Jens Axboe <jens.axboe@oracle.com> wrote:
>
> > On Fri, Sep 21 2007, Peer Chen wrote:
> > > According to the description of section 5.2.2.1 and 10.1.2 of AHCI specification rev1_1/rev1_2, GHC.HR shall only be set to ¡®1¡¯
> > > by software when GHC.AE is set to ¡®1¡¯.
> > >
> > > Signed-off-by: Peer Chen <peerchen@gmail.com>
> > > ---
> > > --- linux-2.6.23-rc7/drivers/ata/ahci.c.orig 2007-09-20 11:01:55.000000000 -0400
> > > +++ linux-2.6.23-rc7/drivers/ata/ahci.c 2007-09-20 11:07:31.000000000 -0400
> > > @@ -834,6 +834,10 @@ static int ahci_reset_controller(struct
> > > void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
> > > u32 tmp;
> > >
> > > + /* turn on AHCI mode before controller reset*/
> > > + writel(HOST_AHCI_EN, mmio + HOST_CTL);
> > > + (void) readl(mmio + HOST_CTL); /* flush */
> > > +
> > > /* global controller reset */
> > > tmp = readl(mmio + HOST_CTL);
> > > if ((tmp & HOST_RESET) == 0) {
> >
> > I appreciate the readl() flushes, but in this particular case we end up
> > reading the exact offset again below.
>
> The code above is wrong btw - it is an iomap so both the new and existing
> code should be using ioread* not readl
Happy converting :-)
--
Jens Axboe
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR
2007-09-21 5:28 [PATCH] ahci: enable GHC.AE bit before set GHC.HR Peer Chen
2007-09-21 10:29 ` Andrew Morton
2007-09-21 10:31 ` Jens Axboe
@ 2007-09-26 4:03 ` Jeff Garzik
2007-09-26 11:23 ` Alan Cox
2 siblings, 1 reply; 12+ messages in thread
From: Jeff Garzik @ 2007-09-26 4:03 UTC (permalink / raw)
To: Peer Chen; +Cc: linux-kernel, akpm, linux-ide
[-- Attachment #1: Type: text/plain, Size: 755 bytes --]
Peer Chen wrote:
> According to the description of section 5.2.2.1 and 10.1.2 of AHCI specification rev1_1/rev1_2, GHC.HR shall only be set to ¡®1¡¯
> by software when GHC.AE is set to ¡®1¡¯.
>
> Signed-off-by: Peer Chen <peerchen@gmail.com>
> ---
> --- linux-2.6.23-rc7/drivers/ata/ahci.c.orig 2007-09-20 11:01:55.000000000 -0400
> +++ linux-2.6.23-rc7/drivers/ata/ahci.c 2007-09-20 11:07:31.000000000 -0400
> @@ -834,6 +834,10 @@ static int ahci_reset_controller(struct
> void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
> u32 tmp;
>
> + /* turn on AHCI mode before controller reset*/
> + writel(HOST_AHCI_EN, mmio + HOST_CTL);
> + (void) readl(mmio + HOST_CTL); /* flush */
applied the attached patch, inspired by yours.
[-- Attachment #2: patch --]
[-- Type: text/plain, Size: 1180 bytes --]
commit 5fca365d6109b51cfeb3515ca660cd2dc6e8822c
Author: Jeff Garzik <jeff@garzik.org>
Date: Wed Sep 26 00:02:41 2007 -0400
[libata] AHCI: enable AHCI mode, before using AHCI reset
AHCI spec says host-reset bit may only be set when the ahci-enable bit
is also set.
Noticed by Peer Chen <peerchen@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
drivers/ata/ahci.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
5fca365d6109b51cfeb3515ca660cd2dc6e8822c
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 9f3c591..b615390 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -827,8 +827,14 @@ static int ahci_reset_controller(struct ata_host *host)
void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
u32 tmp;
- /* global controller reset */
+ /* we must be in AHCI mode, before using anything
+ * AHCI-specific, such as HOST_RESET.
+ */
tmp = readl(mmio + HOST_CTL);
+ if (!(tmp & HOST_AHCI_EN))
+ writel(tmp | HOST_AHCI_EN, mmio + HOST_CTL);
+
+ /* global controller reset */
if ((tmp & HOST_RESET) == 0) {
writel(tmp | HOST_RESET, mmio + HOST_CTL);
readl(mmio + HOST_CTL); /* flush */
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR
2007-09-26 4:03 ` Jeff Garzik
@ 2007-09-26 11:23 ` Alan Cox
2007-09-26 11:41 ` Jeff Garzik
0 siblings, 1 reply; 12+ messages in thread
From: Alan Cox @ 2007-09-26 11:23 UTC (permalink / raw)
To: Jeff Garzik; +Cc: Peer Chen, linux-kernel, akpm, linux-ide
On Wed, 26 Sep 2007 00:03:19 -0400
Jeff Garzik <jeff@garzik.org> wrote:
> Peer Chen wrote:
> > According to the description of section 5.2.2.1 and 10.1.2 of AHCI specification rev1_1/rev1_2, GHC.HR shall only be set to ¡®1¡¯
> > by software when GHC.AE is set to ¡®1¡¯.
> >
> > Signed-off-by: Peer Chen <peerchen@gmail.com>
> > ---
> > --- linux-2.6.23-rc7/drivers/ata/ahci.c.orig 2007-09-20 11:01:55.000000000 -0400
> > +++ linux-2.6.23-rc7/drivers/ata/ahci.c 2007-09-20 11:07:31.000000000 -0400
> > @@ -834,6 +834,10 @@ static int ahci_reset_controller(struct
> > void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
> > u32 tmp;
> >
> > + /* turn on AHCI mode before controller reset*/
> > + writel(HOST_AHCI_EN, mmio + HOST_CTL);
> > + (void) readl(mmio + HOST_CTL); /* flush */
>
> applied the attached patch, inspired by yours.
NAK - mmio is an iomap so writel and readl are the wrong things to use
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR
2007-09-26 11:23 ` Alan Cox
@ 2007-09-26 11:41 ` Jeff Garzik
2007-09-26 14:30 ` Alan Cox
0 siblings, 1 reply; 12+ messages in thread
From: Jeff Garzik @ 2007-09-26 11:41 UTC (permalink / raw)
To: Alan Cox; +Cc: Peer Chen, linux-kernel, akpm, linux-ide
Alan Cox wrote:
> On Wed, 26 Sep 2007 00:03:19 -0400
> Jeff Garzik <jeff@garzik.org> wrote:
>
>> Peer Chen wrote:
>>> According to the description of section 5.2.2.1 and 10.1.2 of AHCI specification rev1_1/rev1_2, GHC.HR shall only be set to ¡®1¡¯
>>> by software when GHC.AE is set to ¡®1¡¯.
>>>
>>> Signed-off-by: Peer Chen <peerchen@gmail.com>
>>> ---
>>> --- linux-2.6.23-rc7/drivers/ata/ahci.c.orig 2007-09-20 11:01:55.000000000 -0400
>>> +++ linux-2.6.23-rc7/drivers/ata/ahci.c 2007-09-20 11:07:31.000000000 -0400
>>> @@ -834,6 +834,10 @@ static int ahci_reset_controller(struct
>>> void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
>>> u32 tmp;
>>>
>>> + /* turn on AHCI mode before controller reset*/
>>> + writel(HOST_AHCI_EN, mmio + HOST_CTL);
>>> + (void) readl(mmio + HOST_CTL); /* flush */
>> applied the attached patch, inspired by yours.
>
>
> NAK - mmio is an iomap so writel and readl are the wrong things to use
The patch is consistent with the rest of the driver.
You are welcome to submit a patch to convert ahci to using ioremap.
Jeff
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR
2007-09-26 11:41 ` Jeff Garzik
@ 2007-09-26 14:30 ` Alan Cox
2007-09-26 14:33 ` Jeff Garzik
0 siblings, 1 reply; 12+ messages in thread
From: Alan Cox @ 2007-09-26 14:30 UTC (permalink / raw)
To: Jeff Garzik; +Cc: Peer Chen, linux-kernel, akpm, linux-ide
> > NAK - mmio is an iomap so writel and readl are the wrong things to use
>
> The patch is consistent with the rest of the driver.
> You are welcome to submit a patch to convert ahci to using ioremap.
You could just flip the relevant function to use ioread while you are
tidying it up, instead of spreading new bugs into the code.
Alan
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR
2007-09-26 14:30 ` Alan Cox
@ 2007-09-26 14:33 ` Jeff Garzik
2007-09-26 16:10 ` Alan Cox
0 siblings, 1 reply; 12+ messages in thread
From: Jeff Garzik @ 2007-09-26 14:33 UTC (permalink / raw)
To: Alan Cox; +Cc: Peer Chen, linux-kernel, akpm, linux-ide
Alan Cox wrote:
>>> NAK - mmio is an iomap so writel and readl are the wrong things to use
>> The patch is consistent with the rest of the driver.
>> You are welcome to submit a patch to convert ahci to using ioremap.
>
> You could just flip the relevant function to use ioread while you are
> tidying it up, instead of spreading new bugs into the code.
No, as I just noted above, the proper fix for this driver is to use
ioremap rather than pci_iomap.
Adding support to ahci for legacy PIO is completely pointless.
Jeff
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR
2007-09-26 14:33 ` Jeff Garzik
@ 2007-09-26 16:10 ` Alan Cox
2007-09-26 16:20 ` Jeff Garzik
0 siblings, 1 reply; 12+ messages in thread
From: Alan Cox @ 2007-09-26 16:10 UTC (permalink / raw)
To: Jeff Garzik; +Cc: Peer Chen, linux-kernel, akpm, linux-ide
On Wed, 26 Sep 2007 10:33:28 -0400
Jeff Garzik <jeff@garzik.org> wrote:
> Alan Cox wrote:
> >>> NAK - mmio is an iomap so writel and readl are the wrong things to use
> >> The patch is consistent with the rest of the driver.
> >> You are welcome to submit a patch to convert ahci to using ioremap.
> >
> > You could just flip the relevant function to use ioread while you are
> > tidying it up, instead of spreading new bugs into the code.
>
> No, as I just noted above, the proper fix for this driver is to use
> ioremap rather than pci_iomap.
>
> Adding support to ahci for legacy PIO is completely pointless.
iomap isn't just for legacy PIO. It allows us to handle future weird
mappings in ways ioremap cannot.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] ahci: enable GHC.AE bit before set GHC.HR
2007-09-26 16:10 ` Alan Cox
@ 2007-09-26 16:20 ` Jeff Garzik
0 siblings, 0 replies; 12+ messages in thread
From: Jeff Garzik @ 2007-09-26 16:20 UTC (permalink / raw)
To: Alan Cox; +Cc: Peer Chen, linux-kernel, akpm, linux-ide
Alan Cox wrote:
> On Wed, 26 Sep 2007 10:33:28 -0400
> Jeff Garzik <jeff@garzik.org> wrote:
>
>> Alan Cox wrote:
>>>>> NAK - mmio is an iomap so writel and readl are the wrong things to use
>>>> The patch is consistent with the rest of the driver.
>>>> You are welcome to submit a patch to convert ahci to using ioremap.
>>> You could just flip the relevant function to use ioread while you are
>>> tidying it up, instead of spreading new bugs into the code.
>> No, as I just noted above, the proper fix for this driver is to use
>> ioremap rather than pci_iomap.
>>
>> Adding support to ahci for legacy PIO is completely pointless.
>
> iomap isn't just for legacy PIO. It allows us to handle future weird
> mappings in ways ioremap cannot.
Well, when needs dictate, we can re-evaluate.
Until some future date arrives where it matters for all these MMIO-only
drivers and hardware, it's just a bunch of pointless overhead for ahci
and many other drivers. It's also just not the Linux way to punish
everybody for some edge case that so far only exists in email conversations.
The beauty of libata is that you don't have to enforce such a pogrom
across all libata drivers. The libata high level API is completely free
from ioread/iowrite junk, leaving each driver to make its own decision.
Jeff
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2007-09-26 16:20 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2007-09-21 5:28 [PATCH] ahci: enable GHC.AE bit before set GHC.HR Peer Chen
2007-09-21 10:29 ` Andrew Morton
2007-09-21 10:31 ` Jens Axboe
2007-09-21 11:27 ` Alan Cox
2007-09-21 11:34 ` Jens Axboe
2007-09-26 4:03 ` Jeff Garzik
2007-09-26 11:23 ` Alan Cox
2007-09-26 11:41 ` Jeff Garzik
2007-09-26 14:30 ` Alan Cox
2007-09-26 14:33 ` Jeff Garzik
2007-09-26 16:10 ` Alan Cox
2007-09-26 16:20 ` Jeff Garzik
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).