From: Tejun Heo <htejun@gmail.com>
To: Jeff Garzik <jeff@garzik.org>,
linux-ide@vger.kernel.org, ethanhsiao@jmicron.com
Subject: [PATCH] jmicron: update quirk for JMB361/3/5/6
Date: Tue, 23 Oct 2007 15:27:31 +0900 [thread overview]
Message-ID: <20071023062731.GC18322@htj.dyndns.org> (raw)
Set bits 0, 4, 5 and 7 of PCI configuration register 0x40 in the
quirk. This has the following effects and is recommended by the
vendor.
* Force enable of IDE channels (used to be left alone as BIOS
configured)
* Change initial phase behavior of PIO cycle such that the host pulls
down the bus instead of tristating it. Vendor recommends this
setting.
The above settings are better for the current generation of
controllers and needed for the upcoming next generation.
Tested on JMB363.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Cc: Ethan Hsiao <ethanhsiao@jmicron.com>
---
drivers/pci/quirks.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index: work/drivers/pci/quirks.c
===================================================================
--- work.orig/drivers/pci/quirks.c
+++ work/drivers/pci/quirks.c
@@ -1230,7 +1230,7 @@ static void quirk_jmicron_ata(struct pci
case PCI_DEVICE_ID_JMICRON_JMB363:
/* Enable dual function mode, AHCI on fn 0, IDE fn1 */
/* Set the class codes correctly and then direct IDE 0 */
- conf1 |= 0x00C2A102; /* Set 1, 8, 13, 15, 17, 22, 23 */
+ conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
break;
case PCI_DEVICE_ID_JMICRON_JMB368:
next reply other threads:[~2007-10-23 6:27 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-10-23 6:27 Tejun Heo [this message]
2007-10-24 1:25 ` [PATCH] jmicron: update quirk for JMB361/3/5/6 Jeff Garzik
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