Re: Multiple MSI, take 3

[Matthew Wilcox <matthew@wil.cx>]

On Fri, Jul 11, 2008 at 03:06:33AM -0700, Eric W. Biederman wrote:
> Matthew Wilcox <matthew@wil.cx> writes:
> 
> > I'd like to thank Michael Ellerman for his feedback.  This is a much
> > better patchset than it used to be.
> 
> There is a reason we don't have an API to support this.  Linux can not
> reasonably support this, especially not on current X86.  The designers
> of the of the AHCI were idiots and should have used MSI-X.

Thank you for your constructive feedback, Eric.  Unfortunately, we have
to deal with the world as it is, not how we would like it to be.  Since
I have it running, I'd like to know what is unreasonable about the
implementation.

> mask/unmask is will likely break because the mask bit is optional
> and when it is not present we disable the msi capability.

I believe this is fixable.  I will attempt to do so.

> We can not set the affinity individually so we can not allow
> different queues to be processed on different cores.

This is true, and yet, it is still useful.  Just not as useful as one
would want.

> So in general it seems something that we have to jump through a million
> hurdles and the result is someones twisted parody of a multiple working
> irqs, that even Intel's IOMMU can't cure.

More constructive feedback ...

> So unless the performance of the AHCI is better by a huge amount I don't
> see the point, and even then I am extremely sceptical.

I don't have performance numbers yet, but surely you can see that
avoiding a register read in the interrupt path is a large win?

-- 
Intel are signing my paycheques ... these opinions are still mine
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours.  We can't possibly take such
a retrograde step."