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From: Sascha Hauer <s.hauer@pengutronix.de>
To: Richard Zhu <richard.zhuhongxing@gmail.com>
Cc: shawn.guo@linaro.org, linux-arm-kernel@lists.infradead.org,
	jgarzik@pobox.com, avorontsov@ru.mvista.com,
	rob.herring@calxeda.com, linux-ide@vger.kernel.org,
	Richard Zhu <r65037@freescale.com>
Subject: Re: [v2 2/4] imx: ahci: enable ahci sata on imx6q platforms
Date: Mon, 1 Jul 2013 14:55:08 +0200	[thread overview]
Message-ID: <20130701125508.GX516@pengutronix.de> (raw)
In-Reply-To: <1372672975-2997-3-git-send-email-r65037@freescale.com>

On Mon, Jul 01, 2013 at 06:02:53PM +0800, Richard Zhu wrote:
> Only the imx6q contains the ahci sata controller,
> other imx6 SoCs don't have it.
> 
> Enable the ahci sata only on imx6q platforms
> 
> Signed-off-by: Richard Zhu <r65037@freescale.com>
> ---
>  arch/arm/mach-imx/mach-imx6q.c |   85 +++++++++++++++++++++++++++++++++++++++-
> +/* imx6q ahci module initialization. */
> +static int imx6q_sata_phy_clk(struct device *dev, int enable)
> +{
> +	int ret = 0;
> +	struct clk *sata_ref_clk;
> +
> +	sata_ref_clk = devm_clk_get(dev, "sata_ref_100m");
> +	if (IS_ERR(sata_ref_clk)) {
> +		dev_err(dev, "can't get sata_ref clock.\n");
> +		return PTR_ERR(sata_ref_clk);
> +	}

devm_clk_get takes a reference to the clock. That's not something you
want to do each time you enable/disable a clock.

> +	if (enable) {
> +		/* Enable PHY clock */
> +		ret = clk_prepare_enable(sata_ref_clk);
> +		if (ret < 0) {
> +			dev_err(dev, "can't prepare-enable sata_ref clock\n");
> +			clk_put(sata_ref_clk);
> +			ret = PTR_ERR(sata_ref_clk);

What are you intending by converting a valid pointer to an error code?

> +		}
> +	} else {
> +		/* Disable PHY clock */
> +		clk_disable_unprepare(sata_ref_clk);
> +	}
> +
> +	return ret;
> +}
> +
> +static int imx6q_sata_init(struct device *dev, void __iomem *addr)
> +{
> +	int ret = 0;
> +	struct regmap *gpr;
> +
> +	ret = imx6q_sata_phy_clk(dev, true);
> +	if (ret < 0)
> +		return ret;
> +
> +	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> +	if (IS_ERR(gpr)) {
> +		pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
> +		return PTR_ERR(gpr);
> +	}
> +
> +	/*
> +	 * set PHY Paremeters, two steps to configure the GPR13,
> +	 * one write for rest of parameters, mask of first write
> +	 * is 0x07fffffd, and the other one write for setting
> +	 * the mpll_clk_en.
> +	 */
> +	regmap_update_bits(gpr, 0x34, 0x07fffffd, 0x0593e4c4);

You are adding the register defines in the next patch. Wouldn't it make
sense to use them?

Sascha

-- 
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  reply	other threads:[~2013-07-01 12:55 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-07-01 10:02 [PATCH v2 0/4] ahci: enable ahci sata support on imx6q Richard Zhu
2013-07-01 10:02 ` [v2 1/4] ARM: dtsi: enable ahci sata on imx6q platforms Richard Zhu
2013-07-01 14:37   ` Shawn Guo
2013-07-01 14:48     ` Zhu Richard-R65037
2013-07-01 10:02 ` [v2 2/4] imx: ahci: " Richard Zhu
2013-07-01 12:55   ` Sascha Hauer [this message]
2013-07-01 14:48     ` Zhu Richard-R65037
2013-07-01 14:53   ` Shawn Guo
2013-07-01 10:02 ` [v2 3/4] ARM: imx6q: update the sata bits definitions of gpr13 Richard Zhu
2013-07-01 10:02 ` [v2 4/4] sata: imx: add ahci sata support on imx platforms Richard Zhu
2013-07-01 11:27   ` Girish K S
2013-07-01 14:48     ` Shawn Guo
2013-07-01 15:04       ` Girish K S
2013-07-01 15:17         ` Shawn Guo
2013-07-01 12:44   ` Sascha Hauer
2013-07-01 15:29     ` Shawn Guo
2013-07-02  2:24       ` Zhu Richard-R65037
2013-07-01 12:49   ` Rob Herring
2013-07-01 13:03     ` Sascha Hauer
2013-07-01 13:22     ` Girish K S
2013-07-01 13:36   ` Tejun Heo
2013-07-01 14:58     ` Zhu Richard-R65037
2013-07-01 15:21     ` Shawn Guo

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