From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.1 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5BD6C433FF for ; Sat, 10 Aug 2019 07:43:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 691292166E for ; Sat, 10 Aug 2019 07:43:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="hofYnX5G" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725862AbfHJHnS (ORCPT ); Sat, 10 Aug 2019 03:43:18 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:56150 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725468AbfHJHnS (ORCPT ); Sat, 10 Aug 2019 03:43:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=In-Reply-To:Content-Type:MIME-Version :References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=6TITaBDZzMYcxlmvixdUZyeuqA25uLCScJvSgm58UkA=; b=hofYnX5GVsR+TrdLOvUBmQwsD ZnOmpzcyGQk5VT0z96cj3/oqetjnc4NO/mEdcN6zAY20C4exWfMTP+D91H6WM3f8uQOw7N8NAiPgj 1/8fMOPBzRsCglJEjO2YAACp26ATBjI6h44dOSmsKnnPqocq0N62Mff3hdw9zd/h7xJspFvuabO3Q 1fKdCbTcNIGTS5Ol3FVz0XgcwGPdBmg2sYYPMzP78tguPqqmCSFilLjcHtMQC9ktFch3tk1CLNVUd 74r9zZfndKU1IY75cbZ985/JJS7LJQYf8VfqLxRiYcGXOTeUBY5I1okh7P81We7SNp8LOrrE0lK9q F0FHYwQYQ==; Received: from hch by bombadil.infradead.org with local (Exim 4.92 #3 (Red Hat Linux)) id 1hwM21-0006Aw-8w; Sat, 10 Aug 2019 07:43:17 +0000 Date: Sat, 10 Aug 2019 00:43:17 -0700 From: Christoph Hellwig To: Stephen Douthit Cc: Jens Axboe , "linux-ide@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Dan Williams Subject: Re: [PATCH] ata: ahci: Lookup PCS register offset based on PCI device ID Message-ID: <20190810074317.GA18582@infradead.org> References: <20190808202415.25166-1-stephend@silicom-usa.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190808202415.25166-1-stephend@silicom-usa.com> User-Agent: Mutt/1.11.4 (2019-03-13) X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org On Thu, Aug 08, 2019 at 08:24:31PM +0000, Stephen Douthit wrote: > Intel moved the PCS register from 0x92 to 0x94 on Denverton for some > reason, so now we get to check the device ID before poking it on reset. And now you just match on the new IDs, which means we'll perpetually catch up on any new device. Dan, can you reach out inside Intel to figure out if there is a way to find out the PCS register location without the PCI ID check? > static int ahci_pci_reset_controller(struct ata_host *host) > { > struct pci_dev *pdev = to_pci_dev(host->dev); > @@ -634,13 +669,14 @@ static int ahci_pci_reset_controller(struct ata_host *host) > > if (pdev->vendor == PCI_VENDOR_ID_INTEL) { > struct ahci_host_priv *hpriv = host->private_data; > + int pcs = ahci_pcs_offset(host); > u16 tmp16; > > /* configure PCS */ > - pci_read_config_word(pdev, 0x92, &tmp16); > + pci_read_config_word(pdev, pcs, &tmp16); > if ((tmp16 & hpriv->port_map) != hpriv->port_map) { > - tmp16 |= hpriv->port_map; > - pci_write_config_word(pdev, 0x92, tmp16); > + tmp16 |= hpriv->port_map & 0xff; > + pci_write_config_word(pdev, pcs, tmp16); > } > } And Stephen, while you are at it, can you split this Intel-specific quirk into a separate helper?