Re: [PATCH 1/2] MIPS: octeon: Fix cvmx_writeq_csr/cvmx_readq_csr on 32-bit builds

[Thomas Bogendoerfer <tsbogend@alpha.franken.de>]

On Wed, Jun 14, 2023 at 11:36:31AM -0600, Rob Herring wrote:
> Test 32-bit builds have an error in cvmx_writeq_csr/cvmx_readq_csr:
> 
> arch/mips/include/asm/octeon/cvmx.h:282:24: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
> 
> As the default for allyesconfig/allmodconfig is 32-bit, fixing these
> functions for 32-bit is needed to enable Cavium Octeon drivers for
> COMPILE_TEST.
> 
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
>  arch/mips/include/asm/octeon/cvmx.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
> index 72e775bf31e6..2265a92995a8 100644
> --- a/arch/mips/include/asm/octeon/cvmx.h
> +++ b/arch/mips/include/asm/octeon/cvmx.h
> @@ -279,7 +279,7 @@ static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
>  
>  static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val)
>  {
> -	cvmx_write_csr((__force uint64_t)csr_addr, val);
> +	cvmx_write_csr((__force uintptr_t)csr_addr, val);
>  }
>  
>  static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
> @@ -296,7 +296,7 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
>  
>  static inline uint64_t cvmx_readq_csr(void __iomem *csr_addr)
>  {
> -	return cvmx_read_csr((__force uint64_t) csr_addr);
> +	return cvmx_read_csr((__force uintptr_t) csr_addr);
>  }
>  
>  static inline void cvmx_send_single(uint64_t data)
> -- 
> 2.39.2

Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

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