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[144.49.247.23]) by smtp-relay.gmail.com with ESMTPS id a92af1059eb24-198a2a59770sm71628c88.17.2026.10.26.12.18.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 26 Oct 2026 12:18:11 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qv1-f69.google.com with SMTP id 6a1803df08f44-91b529a8610so79804976d6.0 for ; Mon, 26 Oct 2026 12:18:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1793042290; x=1793647090; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=eG9L8JoEnV2/AJh4IZs2XwE9uOcVbAGkOowIPsI/5ZY=; b=H0/Y/cJN7a7qauIF7IdrLCml7qvQ06gT9GI2jIst243tn4hvmjbpGyj0KfD4TmTkhj ZZ98Z2ZGRJDRfojvzaC9e0Vf5+ZbvD+a1irJ5vgjfMP8MZ+I0wKX3ibADwAKEq4VvJjZ 03+AfNWRUeTih2PLMBYeDViIEub4amKWjOWhA= X-Forwarded-Encrypted: i=1; AKwUvBwVq9o4Rbb7AnVce7u/g1RQm7ct57AxbtA1eGDC1Nf474T//yeaBt2y+MuQNcR14M4J+3O0CBKvhhY=@vger.kernel.org X-Received: by 2002:ad4:5d42:0:b0:91c:6d30:7c2c with SMTP id 6a1803df08f44-91c6d307d76mr12445256d6.52.1793042289913; Mon, 26 Oct 2026 12:18:09 -0700 (PDT) X-Received: by 2002:ad4:5d42:0:b0:91c:6d30:7c2c with SMTP id 6a1803df08f44-91c6d307d76mr12444746d6.52.1793042289436; Mon, 26 Oct 2026 12:18:09 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-91c62063dacsm33430996d6.37.2026.10.26.12.18.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 12:18:08 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Damien Le Moal , Niklas Cassel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ray Jui , Scott Branden , Broadcom internal kernel review list , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Kishon Vijay Abraham I , Tejun Heo , Yendapally Reddy Dhananjaya Reddy , linux-ide@vger.kernel.org (open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-phy@lists.infradead.org (open list:GENERIC PHY FRAMEWORK) Subject: [PATCH v3 3/6] ata: ahci_brcm: Initialize the NSP interface clock and reset Date: Mon, 26 Oct 2026 12:16:15 -0700 Message-ID: <20261026191618.3178830-4-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261026191618.3178830-1-florian.fainelli@broadcom.com> References: <20261026191618.3178830-1-florian.fainelli@broadcom.com> X-Mailing-List: linux-ide@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e The NSP probe path assumes firmware has enabled the SATA IDM interface clock and released the core reset. The downstream iProc config_AHCI() sequence explicitly performs both operations before accessing AHCI. Without that setup, a cold boot can access an inactive controller. Map the optional NSP IDM register region and enable the interface clock before releasing reset, retaining the downstream settling intervals. Perform the sequence at probe and resume before reconfiguring SATA. Keep the resource optional so older device trees continue to rely on firmware initialization. Fixes: 3ee2e6dcaa35 ("ata: ahci_brcm: Add support for Broadcom NSP SoC") Signed-off-by: Florian Fainelli --- drivers/ata/ahci_brcm.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c index 29be74fedcf0..3b6ed56f3e95 100644 --- a/drivers/ata/ahci_brcm.c +++ b/drivers/ata/ahci_brcm.c @@ -6,7 +6,9 @@ */ #include +#include #include +#include #include #include #include @@ -83,6 +85,7 @@ enum brcm_ahci_quirks { struct brcm_ahci_priv { struct device *dev; void __iomem *top_ctrl; + void __iomem *idm; u32 port_mask; u32 quirks; enum brcm_ahci_version version; @@ -230,6 +233,25 @@ static u32 brcm_ahci_get_portmask(struct ahci_host_priv *hpriv, return impl; } +static void brcm_sata_init_idm(struct brcm_ahci_priv *priv) +{ + u32 data; + + if (!priv->idm) + return; + + /* Enable the interface clock before releasing the SATA core reset. */ + data = readl(priv->idm + BCMA_IOCTL); + writel(data | BCMA_IOCTL_CLK, priv->idm + BCMA_IOCTL); + readl(priv->idm + BCMA_IOCTL); + usleep_range(1000, 2000); + + data = readl(priv->idm + BCMA_RESET_CTL); + writel(data & ~BCMA_RESET_CTL_RESET, priv->idm + BCMA_RESET_CTL); + readl(priv->idm + BCMA_RESET_CTL); + usleep_range(1000, 2000); +} + static void brcm_sata_init(struct brcm_ahci_priv *priv) { void __iomem *ctrl = priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL; @@ -376,6 +398,9 @@ static int __maybe_unused brcm_ahci_resume(struct device *dev) if (ret) return ret; + /* Initialize the IDM before enabling the controller clocks. */ + brcm_sata_init_idm(priv); + /* Make sure clocks are turned on before re-configuration */ ret = ahci_platform_enable_clks(hpriv); if (ret) @@ -453,6 +478,14 @@ static int brcm_ahci_probe(struct platform_device *pdev) priv->version = (unsigned long)of_id->data; priv->dev = dev; + /* Older NSP device trees rely on firmware to initialize the IDM. */ + if (priv->version == BRCM_SATA_NSP && + platform_get_resource_byname(pdev, IORESOURCE_MEM, "idm")) { + priv->idm = devm_platform_ioremap_resource_byname(pdev, "idm"); + if (IS_ERR(priv->idm)) + return PTR_ERR(priv->idm); + } + priv->top_ctrl = devm_platform_ioremap_resource_byname(pdev, "top-ctrl"); if (IS_ERR(priv->top_ctrl)) return PTR_ERR(priv->top_ctrl); @@ -493,6 +526,9 @@ static int brcm_ahci_probe(struct platform_device *pdev) if (ret) return ret; + /* Initialize the IDM before enabling the controller clocks. */ + brcm_sata_init_idm(priv); + ret = ahci_platform_enable_clks(hpriv); if (ret) goto out_reset; -- 2.53.0