Re: SATA ATAPI work in progress

[Jeff Garzik <jgarzik@pobox.com>]

Pat LaVarre wrote:
> I'll first try keeping only the ata_exec_command_pio of
> ata_bmdma_start_pio.

A bit busy today, I'll ponder a bit and respond to your previous mail.


> I'm thinking we want the bus mastering DMA set up to reliably catch the
> rising edge of a potentially rapid device INTRQ before we write the last
> "word" of Command Out.

Your basic statement is correct, but remember in the new world of SATA 
FIS's, you must concentrate on when the HBA transmits the H2D Register 
FIS (command FIS) to the device, and when the device responds in some 
manner (either with DMA setup and Data FIS conversations, for which the 
DMA engine must be armed, or with an error via D2H Register FIS)

An interrupt will not be asserted until the command FIS has been sent, 
and some sort of response is received from the device.

Further, and perhaps more importantly, everything is inside 
spin_lock_irqsave(), so interrupts will be handled after the lock is 
released.

	Jeff