Re: [PATCH] updates to Vitesse SATA driver

[Jeff Garzik <jgarzik@pobox.com>]

Dave wrote:
> I believe waiting for you to comment on whether to put in a hook for
> controllers that do not support ATA_NIEN so it can mask/unmask IRQ
> with a fixup.  Even though the spec for this particular SATA
> controller says the bit is reserved, it seems to work just fine. From
> my understanding, the registers are actually on the drives, and the
> ones we write to the HBAs are just shadow registers right? I suppose
> either we can use the "undocumented" reserved bit for ATA_NIEN, or
> provide some sort of special hook in lib_ata core to clear the
> interrupt bit....


Close.

The shadow registers are an entity that exists solely on the host 
controller.  The entire register block is converted internally by the 
silicon to a SATA Host-to-Device Register FIS, and the FIS is what is 
sent to the SATA device.

As you can see in the SATA specification (www.serialata.org), each SATA 
FIS contains an interrupt bit.  The decision about when and how to set 
this interrupt bit is highly controller-specific.  Sometimes it is 
mapped to nIEN in the Device Control register.  Sometimes it is 
completely ignored (as with AHCI), and the controller sends interrupts 
based on various bits set in an interrupt-status register.

In any case, it is still not clear what you are trying to achieve :(

In what way is sata_vsc's current ATA_NIEN handling code deficient?

	Jeff