* PDC20269: Limit on number of controllers?
@ 2005-02-21 22:32 Winstel, Drew
2005-02-22 7:28 ` Albert Lee
0 siblings, 1 reply; 7+ messages in thread
From: Winstel, Drew @ 2005-02-21 22:32 UTC (permalink / raw)
To: Linux-Ide (E-mail)
Is there a limit on the number of Promise Ultra133TX2 (PDC20269
chip) PATA interface cards that can be present on a system?
Judging from my efforts to get a test PC running with the
configuration below, it would appear that there is a maximum
of two cards that can be installed. After much trial and error,
I have determined that the errors listed below occur only on
UDMA(100) drives that are connected to ide6 and later (that
is, the 3rd card). Master/slave jumper settings have no
visible effect.
I tried using three Highpoint Rocket 133 cards to see if they
performed any better, and they were not vulnerable to the DMA
limitation, but I must have gotten a bad card or two since they
left the drives in an unstable condition (/var/log/messages
grew to 343M!).
Steps to reproduce:
1) Set up a system with at least 3 Promise Ultra133TX2 cards in
addition to having on-board primary and secondary IDE enabled.
2) Populate the primary master of the third controller with a
drive supporting UDMA 5 or better. It appears to have no
bearing whether or not the first two controllers are populated
or not.
3) Check dmesg for errors akin to the ones below.
This dmesg output is from 2.6.7, but the problem also exists
in 2.6.11-rc4.
Oh, and before anyone asks me why in the world I would have a
need for a system capable of addressing 16 drives attached to
one PC, the machine's entire purpose is stressing the IDE drives
to the limit before they are declared safe for production use.
Ordinarily, I would say this isn't much of a problem, but during
one of the stress runs, these problems force the drives to drop
to PIO mode, thereby killing any resemblance of speed.
Thanks for any help!
Drew Winstel
P.S. dmesg output follows:
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
NFORCE2: IDE controller at PCI slot 0000:00:09.0
NFORCE2: chipset revision 162
NFORCE2: not 100%% native mode: will probe irqs later
NFORCE2: 0000:00:09.0 (rev a2) UDMA133 controller
ide0: BM-DMA at 0xf000-0xf007, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0xf008-0xf00f, BIOS settings: hdc:DMA, hdd:DMA
hda: TOSHIBA MK4019GAX, ATA DISK drive
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
hdc: DVD-ROM DDU1621, ATAPI CD/DVD-ROM drive
ide1 at 0x170-0x177,0x376 on irq 15
PDC20269: IDE controller at PCI slot 0000:01:07.0
PDC20269: chipset revision 2
PDC20269: 100%% native mode on irq 10
ide2: BM-DMA at 0x5c00-0x5c07, BIOS settings: hde:pio, hdf:pio
ide3: BM-DMA at 0x5c08-0x5c0f, BIOS settings: hdg:pio, hdh:pio
hde: TOSHIBA MK8025GAS, ATA DISK drive
ide2 at 0x4c00-0x4c07,0x5002 on irq 10
hdg: TOSHIBA MK8025GAS, ATA DISK drive
ide3 at 0x5400-0x5407,0x5802 on irq 10
PDC20269: IDE controller at PCI slot 0000:01:08.0
PDC20269: chipset revision 2
PDC20269: 100%% native mode on irq 11
ide4: BM-DMA at 0x7000-0x7007, BIOS settings: hdi:pio, hdj:pio
ide5: BM-DMA at 0x7008-0x700f, BIOS settings: hdk:pio, hdl:pio
hdi: TOSHIBA MK8025GAS, ATA DISK drive
ide4 at 0x6000-0x6007,0x6402 on irq 11
hdk: TOSHIBA MK8025GAS, ATA DISK drive
ide5 at 0x6800-0x6807,0x6c02 on irq 11
PDC20269: IDE controller at PCI slot 0000:01:09.0
PDC20269: chipset revision 2
PDC20269: 100%% native mode on irq 5
ide6: BM-DMA at 0x8400-0x8407, BIOS settings: hdm:pio, hdn:pio
ide7: BM-DMA at 0x8408-0x840f, BIOS settings: hdo:pio, hdp:pio
hdm: TOSHIBA MK8025GAS, ATA DISK drive
ide6 at 0x7400-0x7407,0x7802 on irq 5
hdo: TOSHIBA MK8025GAS, ATA DISK drive
ide7 at 0x7c00-0x7c07,0x8002 on irq 5
PDC20269: IDE controller at PCI slot 0000:01:0a.0
PDC20269: chipset revision 2
PDC20269: 100%% native mode on irq 12
ide8: BM-DMA at 0x9800-0x9807, BIOS settings: hdq:pio, hdr:pio
ide9: BM-DMA at 0x9808-0x980f, BIOS settings: hds:pio, hdt:pio
hdq: TOSHIBA MK8025GAS, ATA DISK drive
ide8 at 0x8800-0x8807,0x8c02 on irq 12
hds: TOSHIBA MK8025GAS, ATA DISK drive
ide9 at 0x9000-0x9007,0x9402 on irq 12
hda: max request size: 128KiB
hda: Host Protected Area detected.
hda: 78138047 sectors (40006 MB), CHS=65535/16/63, UDMA(33)
hda: hda1 hda2 hda3
hde: max request size: 128KiB
hde: 156301488 sectors (80026 MB), CHS=65535/16/63, UDMA(100)
hde: unknown partition table
hdg: max request size: 128KiB
hdg: 156301488 sectors (80026 MB), CHS=65535/16/63, UDMA(100)
hdg: unknown partition table
hdi: max request size: 128KiB
hdi: 156301488 sectors (80026 MB), CHS=65535/16/63, UDMA(100)
hdi: unknown partition table
hdk: max request size: 128KiB
hdk: 156301488 sectors (80026 MB), CHS=65535/16/63, UDMA(100)
hdk: unknown partition table
hdm: max request size: 128KiB
hdm: 156301488 sectors (80026 MB), CHS=65535/16/63, UDMA(100)
hdm:hdm: dma_intr: status=0x51 { DriveReady SeekComplete Error }
hdm: dma_intr: error=0x84 { DriveStatusError BadCRC }
hdm: dma_timer_expiry: dma status == 0x21
hdm: DMA timeout error
hdm: dma timeout error: status=0x51 { DriveReady SeekComplete Error }
hdm: dma timeout error: error=0x84 { DriveStatusError BadCRC }
unknown partition table
hdo: max request size: 128KiB
hdo: 156301488 sectors (80026 MB), CHS=65535/16/63, UDMA(100)
hdo:hdo: dma_intr: status=0x51 { DriveReady SeekComplete Error }
hdo: dma_intr: error=0x84 { DriveStatusError BadCRC }
hdo: dma_intr: status=0x51 { DriveReady SeekComplete Error }
hdo: dma_intr: error=0x84 { DriveStatusError BadCRC }
hdo: dma_intr: status=0x51 { DriveReady SeekComplete Error }
hdo: dma_intr: error=0x84 { DriveStatusError BadCRC }
hdo: dma_intr: status=0x51 { DriveReady SeekComplete Error }
hdo: dma_intr: error=0x84 { DriveStatusError BadCRC }
PDC202XX: Secondary channel reset.
ide7: reset: success
unknown partition table
hdq: max request size: 128KiB
hdq: 156301488 sectors (80026 MB), CHS=65535/16/63, UDMA(100)
hdq:hdq: dma_intr: status=0x51 { DriveReady SeekComplete Error }
hdq: dma_intr: error=0x84 { DriveStatusError BadCRC }
hdq: dma_timer_expiry: dma status == 0x21
hdq: DMA timeout error
hdq: dma timeout error: status=0x51 { DriveReady SeekComplete Error }
hdq: dma timeout error: error=0x84 { DriveStatusError BadCRC }
unknown partition table
hds: max request size: 128KiB
hds: 156301488 sectors (80026 MB), CHS=65535/16/63, UDMA(100)
hds:hds: dma_intr: status=0x51 { DriveReady SeekComplete Error }
hds: dma_intr: error=0x84 { DriveStatusError BadCRC }
hds: dma_timer_expiry: dma status == 0x21
hds: DMA timeout error
hds: dma timeout error: status=0x51 { DriveReady SeekComplete Error }
hds: dma timeout error: error=0x84 { DriveStatusError BadCRC }
unknown partition table
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: PDC20269: Limit on number of controllers?
2005-02-21 22:32 Winstel, Drew
@ 2005-02-22 7:28 ` Albert Lee
0 siblings, 0 replies; 7+ messages in thread
From: Albert Lee @ 2005-02-22 7:28 UTC (permalink / raw)
To: Winstel, Drew; +Cc: IDE Linux
[-- Attachment #1: Type: text/plain, Size: 2163 bytes --]
> Is there a limit on the number of Promise Ultra133TX2 (PDC20269
> chip) PATA interface cards that can be present on a system?
>
> Judging from my efforts to get a test PC running with the
> configuration below, it would appear that there is a maximum
> of two cards that can be installed. After much trial and error,
> I have determined that the errors listed below occur only on
> UDMA(100) drives that are connected to ide6 and later (that
> is, the 3rd card). Master/slave jumper settings have no
> visible effect.
>
> I tried using three Highpoint Rocket 133 cards to see if they
> performed any better, and they were not vulnerable to the DMA
> limitation, but I must have gotten a bad card or two since they
> left the drives in an unstable condition (/var/log/messages
> grew to 343M!).
>
> Steps to reproduce:
> 1) Set up a system with at least 3 Promise Ultra133TX2 cards in
> addition to having on-board primary and secondary IDE enabled.
> 2) Populate the primary master of the third controller with a
> drive supporting UDMA 5 or better. It appears to have no
> bearing whether or not the first two controllers are populated
> or not.
> 3) Check dmesg for errors akin to the ones below.
>
> This dmesg output is from 2.6.7, but the problem also exists
> in 2.6.11-rc4.
>
> Oh, and before anyone asks me why in the world I would have a
> need for a system capable of addressing 16 drives attached to
> one PC, the machine's entire purpose is stressing the IDE drives
> to the limit before they are declared safe for production use.
> Ordinarily, I would say this isn't much of a problem, but during
> one of the stress runs, these problems force the drives to drop
> to PIO mode, thereby killing any resemblance of speed.
>
> Thanks for any help!
>
> Drew Winstel
>
Hi,
Maybe the PLL on the 3rd pdc20269 adapter not initialized by the firmware.
Could you help to test it with the attached libata pdc2027x driver patch with kernel 2.6.10 or above?
When configuring the kernel, please select "N" for pdc202xx_new driver and
select "Y" for the attached pata_pdc2027x driver instead. Thanks.
Albert
[-- Attachment #2: pdc20269_debug.diff --]
[-- Type: application/octet-stream, Size: 26502 bytes --]
diff -Nru linux-2.6.10/drivers/scsi/Kconfig linux-2.6.10-mod/drivers/scsi/Kconfig
--- linux-2.6.10/drivers/scsi/Kconfig 2004-12-25 05:35:28.000000000 +0800
+++ linux-2.6.10-mod/drivers/scsi/Kconfig 2005-02-22 15:11:57.000000000 +0800
@@ -441,6 +441,14 @@
If unsure, say N.
+config SCSI_PATA_PDC2027X
+ tristate "Promise PATA 2027x support"
+ depends on SCSI_SATA && PCI
+ help
+ This option enables support for Promise PATA pdc20268 to pdc20277 host adapters.
+
+ If unsure, say N.
+
config SCSI_SATA_PROMISE
tristate "Promise SATA TX2/TX4 support"
depends on SCSI_SATA && PCI
diff -Nru linux-2.6.10/drivers/scsi/Makefile linux-2.6.10-mod/drivers/scsi/Makefile
--- linux-2.6.10/drivers/scsi/Makefile 2004-12-25 05:35:24.000000000 +0800
+++ linux-2.6.10-mod/drivers/scsi/Makefile 2005-02-22 15:12:18.000000000 +0800
@@ -124,6 +124,7 @@
obj-$(CONFIG_SCSI_SATA_AHCI) += libata.o ahci.o
obj-$(CONFIG_SCSI_SATA_SVW) += libata.o sata_svw.o
obj-$(CONFIG_SCSI_ATA_PIIX) += libata.o ata_piix.o
+obj-$(CONFIG_SCSI_PATA_PDC2027X)+= libata.o pata_pdc2027x.o
obj-$(CONFIG_SCSI_SATA_PROMISE) += libata.o sata_promise.o
obj-$(CONFIG_SCSI_SATA_SIL) += libata.o sata_sil.o
obj-$(CONFIG_SCSI_SATA_VIA) += libata.o sata_via.o
diff -Nru linux-2.6.10/drivers/scsi/pata_pdc2027x.c linux-2.6.10-mod/drivers/scsi/pata_pdc2027x.c
--- linux-2.6.10/drivers/scsi/pata_pdc2027x.c 1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.10-mod/drivers/scsi/pata_pdc2027x.c 2005-02-22 15:13:00.000000000 +0800
@@ -0,0 +1,767 @@
+/*
+ * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Ported to libata by:
+ * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
+ *
+ * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
+ * Portions Copyright (C) 1999 Promise Technology, Inc.
+ *
+ * Author: Frank Tiernan (frankt@promise.com)
+ * Released under terms of General Public License
+ *
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include "scsi.h"
+#include <scsi/scsi_host.h>
+#include <linux/libata.h>
+#include <asm/io.h>
+
+#define DRV_NAME "pata_pdc2027x"
+#define DRV_VERSION "0.56"
+#define PDC_DEBUG
+
+#ifdef PDC_DEBUG
+#define PDPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__, ## args)
+#else
+#define PDPRINTK(fmt, args...)
+#endif
+
+enum {
+ PDC_UDMA_100 = 0,
+ PDC_UDMA_133 = 1,
+
+ PDC_100_MHZ = 100000000,
+ PDC_133_MHZ = 133333333,
+};
+
+static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
+static void pdc2027x_remove_one(struct pci_dev *pdev);
+static void pdc2027x_phy_reset(struct ata_port *ap);
+static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
+static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
+static void pdc2027x_post_set_mode(struct ata_port *ap);
+static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
+
+/*
+ * ATA Timing Tables based on 133MHz controller clock.
+ * These tables are only used when the controller is in 133MHz clock.
+ * If the controller is in 100MHz clock, the ASIC hardware will
+ * set the timing registers automatically when "set feature" command
+ * is issued to the device. However, if the controller clock is 133MHz,
+ * the following tables must be used.
+ */
+static struct pdc2027x_pio_timing {
+ u8 value0, value1, value2;
+} pdc2027x_pio_timing_tbl [] = {
+ { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
+ { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
+ { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
+ { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
+ { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
+};
+
+static struct pdc2027x_mdma_timing {
+ u8 value0, value1;
+} pdc2027x_mdma_timing_tbl [] = {
+ { 0xdf, 0x5f }, /* MDMA mode 0 */
+ { 0x6b, 0x27 }, /* MDMA mode 1 */
+ { 0x69, 0x25 }, /* MDMA mode 2 */
+};
+
+static struct pdc2027x_udma_timing {
+ u8 value0, value1, value2;
+} pdc2027x_udma_timing_tbl [] = {
+ { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
+ { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
+ { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
+ { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
+ { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
+ { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
+ { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
+};
+
+static struct pci_device_id pdc2027x_pci_tbl[] = {
+#ifdef ATA_ENABLE_PATA
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_100 },
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_100 },
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
+#endif
+ { } /* terminate list */
+};
+
+static struct pci_driver pdc2027x_pci_driver = {
+ .name = DRV_NAME,
+ .id_table = pdc2027x_pci_tbl,
+ .probe = pdc2027x_init_one,
+ .remove = __devexit_p(pdc2027x_remove_one),
+};
+
+static Scsi_Host_Template pdc2027x_sht = {
+ .module = THIS_MODULE,
+ .name = DRV_NAME,
+ .queuecommand = ata_scsi_queuecmd,
+ .eh_strategy_handler = ata_scsi_error,
+ .can_queue = ATA_DEF_QUEUE,
+ .this_id = ATA_SHT_THIS_ID,
+ .sg_tablesize = LIBATA_MAX_PRD,
+ .max_sectors = ATA_MAX_SECTORS,
+ .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
+ .emulated = ATA_SHT_EMULATED,
+ .use_clustering = ATA_SHT_USE_CLUSTERING,
+ .proc_name = DRV_NAME,
+ .dma_boundary = ATA_DMA_BOUNDARY,
+ .slave_configure = ata_scsi_slave_config,
+ .bios_param = ata_std_bios_param,
+};
+
+static struct ata_port_operations pdc2027x_pata100_ops = {
+ .port_disable = ata_port_disable,
+
+ .tf_load = ata_tf_load,
+ .tf_read = ata_tf_read,
+ .check_status = ata_check_status,
+ .exec_command = ata_exec_command,
+ .dev_select = ata_std_dev_select,
+
+ .phy_reset = pdc2027x_phy_reset,
+
+ .check_atapi_dma = pdc2027x_check_atapi_dma,
+ .bmdma_setup = ata_bmdma_setup,
+ .bmdma_start = ata_bmdma_start,
+ .qc_prep = ata_qc_prep,
+ .qc_issue = ata_qc_issue_prot,
+ .eng_timeout = ata_eng_timeout,
+
+ .irq_handler = ata_interrupt,
+ .irq_clear = ata_bmdma_irq_clear,
+
+ .port_start = ata_port_start,
+ .port_stop = ata_port_stop,
+};
+
+static struct ata_port_operations pdc2027x_pata133_ops = {
+ .port_disable = ata_port_disable,
+ .set_piomode = pdc2027x_set_piomode,
+ .set_dmamode = pdc2027x_set_dmamode,
+
+ .tf_load = ata_tf_load,
+ .tf_read = ata_tf_read,
+ .check_status = ata_check_status,
+ .exec_command = ata_exec_command,
+ .dev_select = ata_std_dev_select,
+
+ .phy_reset = pdc2027x_phy_reset,
+ .post_set_mode = pdc2027x_post_set_mode,
+
+ .check_atapi_dma = pdc2027x_check_atapi_dma,
+ .bmdma_setup = ata_bmdma_setup,
+ .bmdma_start = ata_bmdma_start,
+ .qc_prep = ata_qc_prep,
+ .qc_issue = ata_qc_issue_prot,
+ .eng_timeout = ata_eng_timeout,
+
+ .irq_handler = ata_interrupt,
+ .irq_clear = ata_bmdma_irq_clear,
+
+ .port_start = ata_port_start,
+ .port_stop = ata_port_stop,
+};
+
+static struct ata_port_info pdc2027x_port_info[] = {
+ /* PDC_UDMA_100 */
+ {
+ .sht = &pdc2027x_sht,
+ .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
+ ATA_FLAG_SRST,
+ .pio_mask = 0x1f, /* pio0-4 */
+ .mwdma_mask = 0x07, /* mwdma0-2 */
+ .udma_mask = ATA_UDMA5, /* udma0-5 */
+ .port_ops = &pdc2027x_pata100_ops,
+ },
+ /* PDC_UDMA_133 */
+ {
+ .sht = &pdc2027x_sht,
+ .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
+ ATA_FLAG_SRST,
+ .pio_mask = 0x1f, /* pio0-4 */
+ .mwdma_mask = 0x07, /* mwdma0-2 */
+ .udma_mask = ATA_UDMA6, /* udma0-6 */
+ .port_ops = &pdc2027x_pata133_ops,
+ },
+};
+
+MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
+MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
+MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
+
+/**
+ * pdc_get_indexed_reg - Set pdc202xx extended register
+ * @ap: Port to which the extended register is set
+ * @index: index of the extended register
+ */
+static u8 pdc_get_indexed_reg(struct ata_port *ap, u8 index)
+{
+ u8 tmp8;
+
+ outb(index, ap->ioaddr.bmdma_addr + 1);
+ tmp8 = inb(ap->ioaddr.bmdma_addr + 3);
+
+ PDPRINTK("Get index reg%X[%X] \n", index, tmp8);
+ return tmp8;
+}
+/**
+ * pdc_set_indexed_reg - Read pdc202xx extended register
+ * @ap: Port to which the extended register is read
+ * @index: index of the extended register
+ */
+static void pdc_set_indexed_reg(struct ata_port *ap, u8 index, u8 value)
+{
+ outb(index, ap->ioaddr.bmdma_addr + 1);
+ outb(value, ap->ioaddr.bmdma_addr + 3);
+ PDPRINTK("Set index reg%X[%X] \n", index, value);
+}
+/**
+ * pdc2027x_pata_cbl_detect - Probe host controller cable detect info
+ * @ap: Port for which cable detect info is desired
+ *
+ * Read 80c cable indicator from Promise extended register.
+ * This register is latched when the system is reset.
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+static void pdc2027x_cbl_detect(struct ata_port *ap)
+{
+ u8 cbl40c;
+
+ /* check cable detect results */
+ cbl40c = pdc_get_indexed_reg(ap, 0x0b) & 0x04;
+
+ if (cbl40c)
+ goto cbl40;
+
+ PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
+
+ ap->cbl = ATA_CBL_PATA80;
+ return;
+
+cbl40:
+ printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
+ ap->cbl = ATA_CBL_PATA40;
+ ap->udma_mask &= ATA_UDMA_MASK_40C;
+}
+/**
+ * pdc2027x_port_enabled - Check extended register at 0x04 to see whether the port is enabled.
+ * @ap: Port to check
+ */
+static inline int pdc2027x_port_enabled(struct ata_port *ap)
+{
+ return pdc_get_indexed_reg(ap, 0x04) & 0x02;
+}
+/**
+ * pdc2027x_phy_reset - Probe specified port on PATA host controller
+ * @ap: Port to probe
+ *
+ * Probe PATA phy.
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+static void pdc2027x_phy_reset(struct ata_port *ap)
+{
+ /* Check whether port enabled */
+ if (!pdc2027x_port_enabled(ap)) {
+ ata_port_disable(ap);
+ printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
+ return;
+ }
+
+ pdc2027x_cbl_detect(ap);
+ ata_port_probe(ap);
+ ata_bus_reset(ap);
+}
+/**
+ * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
+ * @ap: Port to configure
+ * @adev: um
+ * @pio: PIO mode, 0 - 4
+ *
+ * Set PIO mode for device.
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+ unsigned int pio = adev->pio_mode - XFER_PIO_0;
+ unsigned int drive_dn = (ap->port_no ? 2 : 0) + adev->devno;
+ u8 adj = (drive_dn%2) ? 0x08 : 0x00;
+
+ PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
+
+ /* Sanity check */
+ if(pio > 4) {
+ printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
+ return;
+
+ }
+
+ /* Set the PIO timing registers using value table for 133MHz */
+ PDPRINTK("Set pio regs... \n");
+
+ pdc_set_indexed_reg(ap, 0x0c + adj, pdc2027x_pio_timing_tbl[pio].value0);
+ pdc_set_indexed_reg(ap, 0x0d + adj, pdc2027x_pio_timing_tbl[pio].value1);
+ pdc_set_indexed_reg(ap, 0x13 + adj, pdc2027x_pio_timing_tbl[pio].value2);
+
+ PDPRINTK("Set pio regs done\n");
+
+ PDPRINTK("Set to pio mode[%u] \n", pio);
+}
+/**
+ * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
+ * @ap: Port to configure
+ * @adev: um
+ * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
+ *
+ * Set UDMA mode for device.
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
+{
+ unsigned int dma_mode = adev->dma_mode;
+ unsigned int drive_dn = (ap->port_no ? 2 : 0) + adev->devno;
+ u8 adj = (drive_dn%2) ? 0x08 : 0x00;
+ u8 tmp8;
+
+ if((dma_mode >= XFER_UDMA_0) &&
+ (dma_mode <= XFER_UDMA_6)) {
+ /* Set the UDMA timing registers with value table for 133MHz */
+ unsigned int udma_mode = dma_mode & 0x07;
+
+ if (dma_mode == XFER_UDMA_2) {
+ /*
+ * Turn off tHOLD.
+ * If tHOLD is '1', the hardware will add half clock for data hold time.
+ * This code segment seems to be no effect. tHOLD will be overwritten below.
+ */
+ tmp8 = pdc_get_indexed_reg(ap, 0x10 + adj);
+ pdc_set_indexed_reg(ap, 0x10 + adj, tmp8 & 0x7f);
+ }
+
+ PDPRINTK("Set udma regs... \n");
+ pdc_set_indexed_reg(ap, 0x10 + adj, pdc2027x_udma_timing_tbl[udma_mode].value0);
+ pdc_set_indexed_reg(ap, 0x11 + adj, pdc2027x_udma_timing_tbl[udma_mode].value1);
+ pdc_set_indexed_reg(ap, 0x12 + adj, pdc2027x_udma_timing_tbl[udma_mode].value2);
+ PDPRINTK("Set udma regs done\n");
+
+ PDPRINTK("Set to udma mode[%u] \n", udma_mode);
+
+ } else if((dma_mode >= XFER_MW_DMA_0) &&
+ (dma_mode <= XFER_MW_DMA_2)) {
+ /* Set the MDMA timing registers with value table for 133MHz */
+ unsigned int mdma_mode = dma_mode & 0x07;
+
+ PDPRINTK("Set mdma regs... \n");
+ pdc_set_indexed_reg(ap, 0x0e + adj, pdc2027x_mdma_timing_tbl[mdma_mode].value0);
+ pdc_set_indexed_reg(ap, 0x0f + adj, pdc2027x_mdma_timing_tbl[mdma_mode].value1);
+ PDPRINTK("Set mdma regs done\n");
+
+ PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
+ } else {
+ printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
+ }
+}
+
+/**
+ * pdc2027x_post_set_mode - Set the timing registers back to correct values.
+ * @ap: Port to configure
+ *
+ * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
+ * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
+ * This function overwrites the possibly incorrect values set by the hardware to be correct.
+ */
+static void pdc2027x_post_set_mode(struct ata_port *ap)
+{
+ int i;
+
+ for (i = 0; i < ATA_MAX_DEVICES; i++) {
+ struct ata_device *dev = &ap->device[i];
+
+ if (ata_dev_present(dev)) {
+ u8 adj = (i % 2) ? 0x08 : 0x00;
+ u8 tmp8;
+
+ pdc2027x_set_piomode(ap, dev);
+
+ /*
+ * Enable prefetch if the device support PIO only.
+ */
+ if (dev->xfer_shift == ATA_SHIFT_PIO) {
+ tmp8 = pdc_get_indexed_reg(ap, 0x13 + adj);
+ pdc_set_indexed_reg(ap, 0x13 + adj, tmp8 | 0x02);
+
+ PDPRINTK("Turn on prefetch\n");
+ } else {
+ pdc2027x_set_dmamode(ap, dev);
+ }
+ }
+ }
+}
+
+/**
+ * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
+ * @qc: Metadata associated with taskfile to check
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ *
+ * RETURNS: 0 when ATAPI DMA can be used
+ * 1 otherwise
+ */
+static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
+{
+ struct scsi_cmnd *cmd = qc->scsicmd;
+ int rc = 0;
+
+ /* pdc2027x can only do ATAPI DMA for specific buffer size */
+ if (cmd->request_bufflen % 256)
+ rc = 1;
+
+ return rc;
+}
+
+/**
+ * adjust_pll - Adjust the PLL input clock in Hz.
+ *
+ * @pdc_controller: controller specific information
+ * @probe_ent: For the port address
+ * @pll_clock: The input of PLL in HZ
+ */
+static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsigned int board_idx)
+{
+
+ u8 pll_ctl0, pll_ctl1;
+ long pll_clock_khz = pll_clock / 1000;
+ long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
+ long ratio = pout_required / pll_clock_khz;
+ int F, R;
+
+
+ /* Sanity check */
+ if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
+ printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
+ return;
+ }
+
+#ifdef PDC_DEBUG
+ PDPRINTK("pout_required is %ld\n", pout_required);
+
+ /* Show the current clock value of PLL control register
+ * (maybe already configured by the firmware)
+ */
+ outb(0x02, probe_ent->port[1].bmdma_addr + 0x01);
+ pll_ctl0 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+ outb(0x03, probe_ent->port[1].bmdma_addr + 0x01);
+ pll_ctl1 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+
+ PDPRINTK("pll_ctl[%X][%X]\n", pll_ctl0, pll_ctl1);
+#endif
+
+ /*
+ * Calculate the ratio of F, R and OD
+ * POUT = (F + 2) / (( R + 2) * NO)
+ */
+ if (ratio < 8600L) { // 8.6x
+ /* Using NO = 0x01, R = 0x0D */
+ R = 0x0d;
+ } else if (ratio < 12900L) { // 12.9x
+ /* Using NO = 0x01, R = 0x08 */
+ R = 0x08;
+ } else if (ratio < 16100L) { // 16.1x
+ /* Using NO = 0x01, R = 0x06 */
+ R = 0x06;
+ } else if (ratio < 64000L) { // 64x
+ R = 0x00;
+ } else {
+ /* Invalid ratio */
+ printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
+ return;
+ }
+
+ F = (ratio * (R+2)) / 1000 - 2;
+
+ if (unlikely(F < 0 || F > 127)) {
+ /* Invalid F */
+ printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
+ return;
+ }
+
+ PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
+
+ pll_ctl0 = (u8) F;
+ pll_ctl1 = (u8) R;
+
+ PDPRINTK("Writing pll_ctl[%X][%X]\n", pll_ctl0, pll_ctl1);
+
+ outb(0x02, probe_ent->port[1].bmdma_addr + 0x01);
+ outb(pll_ctl0, probe_ent->port[1].bmdma_addr + 0x03);
+ outb(0x03, probe_ent->port[1].bmdma_addr + 0x01);
+ outb(pll_ctl1, probe_ent->port[1].bmdma_addr + 0x03);
+
+ /* Wait the PLL circuit to be stable */
+ mdelay(30);
+
+#ifdef PDC_DEBUG
+ /*
+ * Show the current clock value of PLL control register
+ * (maybe configured by the firmware)
+ */
+ outb(0x02, probe_ent->port[1].bmdma_addr + 0x01);
+ pll_ctl0 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+ outb(0x03, probe_ent->port[1].bmdma_addr + 0x01);
+ pll_ctl1 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+
+ PDPRINTK("pll_ctl[%X][%X]\n", pll_ctl0, pll_ctl1);
+#endif
+
+ return;
+}
+/**
+ * detect_pll_input_clock - Detect the PLL input clock in Hz.
+ * @probe_ent: for the port address
+ * Ex. 16949000 on 33MHz PCI bus for pdc20275.
+ * Half of the PCI clock.
+ */
+static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent)
+{
+ u8 scr1;
+ unsigned long ctr0;
+ unsigned long ctr1;
+ unsigned long ctr2 = 0;
+ unsigned long ctr3 = 0;
+
+ unsigned long start_count, end_count;
+ long pll_clock;
+
+ /* Read current counter value */
+ outb(0x20, probe_ent->port[0].bmdma_addr + 0x01);
+ ctr0 = inb(probe_ent->port[0].bmdma_addr + 0x03);
+ outb(0x21, probe_ent->port[0].bmdma_addr + 0x01);
+ ctr1 = inb(probe_ent->port[0].bmdma_addr + 0x03);
+
+ outb(0x20, probe_ent->port[1].bmdma_addr + 0x01);
+ ctr2 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+ outb(0x21, probe_ent->port[1].bmdma_addr + 0x01);
+ ctr3 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+
+ start_count = (ctr3 << 23 ) | (ctr2 << 15) | (ctr1 << 8) | ctr0;
+
+ PDPRINTK("ctr0[%lX] ctr1[%lX] ctr2 [%lX] ctr3 [%lX]\n", ctr0, ctr1, ctr2, ctr3);
+
+ /* Start the test mode */
+ outb(0x01, probe_ent->port[0].bmdma_addr + 0x01);
+ scr1 = inb(probe_ent->port[0].bmdma_addr + 0x03);
+ PDPRINTK("scr1[%X]\n", scr1);
+ outb(scr1 | 0x40, probe_ent->port[0].bmdma_addr + 0x03);
+
+ /* Let the counter run for 1000 us. */
+ udelay(1000);
+
+ /* Read the counter values again */
+ outb(0x20, probe_ent->port[0].bmdma_addr + 0x01);
+ ctr0 = inb(probe_ent->port[0].bmdma_addr + 0x03);
+ outb(0x21, probe_ent->port[0].bmdma_addr + 0x01);
+ ctr1 = inb(probe_ent->port[0].bmdma_addr + 0x03);
+
+ outb(0x20, probe_ent->port[1].bmdma_addr + 0x01);
+ ctr2 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+ outb(0x21, probe_ent->port[1].bmdma_addr + 0x01);
+ ctr3 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+
+ end_count = (ctr3 << 23 ) | (ctr2 << 15) | (ctr1 << 8) | ctr0;
+
+ PDPRINTK("ctr0[%lX] ctr1[%lX] ctr2 [%lX] ctr3 [%lX]\n", ctr0, ctr1, ctr2, ctr3);
+
+ /* Stop the test mode */
+ outb(0x01, probe_ent->port[0].bmdma_addr + 0x01);
+ scr1 = inb(probe_ent->port[0].bmdma_addr + 0x03);
+ PDPRINTK("scr1[%X]\n", scr1);
+ outb(scr1 & 0xBF, probe_ent->port[0].bmdma_addr + 0x03);
+
+ /* calculate the input clock in Hz */
+ pll_clock = (long) ((start_count - end_count) * 1000);
+
+ PDPRINTK("start[%lu] end[%lu] \n", start_count, end_count);
+ PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
+
+ return pll_clock;
+}
+/**
+ * pdc_hardware_init - Initialize the hardware.
+ * @pdev: instance of pci_dev found
+ * @pdc_controller: controller specific information
+ * @pe: for the port address
+ */
+static int pdc_hardware_init(struct pci_dev *pdev, struct ata_probe_ent *pe, unsigned int board_idx)
+{
+ long pll_clock;
+
+ /*
+ * Detect PLL input clock rate.
+ * On some system, where PCI bus is running at non-standard clock rate.
+ * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
+ * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
+ */
+ pll_clock = pdc_detect_pll_input_clock(pe);
+
+ if(pll_clock < 0) /* counter overflow? Try again. */
+ pll_clock = pdc_detect_pll_input_clock(pe);
+
+ printk(KERN_INFO DRV_NAME ": PLL input clock %ld kHz\n", pll_clock/1000);
+
+ /* Adjust PLL control register */
+ pdc_adjust_pll(pe, pll_clock, board_idx);
+
+ return 0;
+}
+/**
+ * pdc2027x_init_one - PCI probe function
+ * Called when an instance of PCI adapter is inserted.
+ * This function checks whether the hardware is supported,
+ * initialize hardware and register an instance of ata_host_set to
+ * libata by providing struct ata_probe_ent and ata_device_add().
+ * (implements struct pci_driver.probe() )
+ *
+ * @pdev: instance of pci_dev found
+ * @ent: matching entry in the id_tbl[]
+ */
+static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ static int printed_version;
+ unsigned int board_idx = (unsigned int) ent->driver_data;
+
+ struct ata_probe_ent *probe_ent = NULL;
+ int rc;
+
+ if (!printed_version++)
+ printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
+
+ rc = pci_enable_device(pdev);
+ if (rc)
+ return rc;
+
+ rc = pci_request_regions(pdev, DRV_NAME);
+ if (rc)
+ goto err_out;
+
+ rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
+ if (rc)
+ goto err_out_regions;
+
+ rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
+ if (rc)
+ goto err_out_regions;
+
+ /* Prepare the probe entry */
+ probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
+ if (probe_ent == NULL) {
+ rc = -ENOMEM;
+ goto err_out_regions;
+ }
+
+ memset(probe_ent, 0, sizeof(*probe_ent));
+ probe_ent->dev = pci_dev_to_dev(pdev);
+ INIT_LIST_HEAD(&probe_ent->node);
+
+ probe_ent->sht = pdc2027x_port_info[board_idx].sht;
+ probe_ent->host_flags = pdc2027x_port_info[board_idx].host_flags;
+ probe_ent->pio_mask = pdc2027x_port_info[board_idx].pio_mask;
+ probe_ent->udma_mask = pdc2027x_port_info[board_idx].udma_mask;
+ probe_ent->port_ops = pdc2027x_port_info[board_idx].port_ops;
+
+ probe_ent->irq = pdev->irq;
+ probe_ent->irq_flags = SA_SHIRQ;
+
+ probe_ent->port[0].cmd_addr = pci_resource_start(pdev, 0);
+ ata_std_ports(&probe_ent->port[0]);
+ probe_ent->port[0].altstatus_addr =
+ probe_ent->port[0].ctl_addr =
+ pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS;
+ probe_ent->port[0].bmdma_addr = pci_resource_start(pdev, 4);
+
+ probe_ent->port[1].cmd_addr = pci_resource_start(pdev, 2);
+ ata_std_ports(&probe_ent->port[1]);
+ probe_ent->port[1].altstatus_addr =
+ probe_ent->port[1].ctl_addr =
+ pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS;
+ probe_ent->port[1].bmdma_addr = pci_resource_start(pdev, 4) + 8;
+
+ probe_ent->n_ports = 2;
+
+ pci_set_master(pdev);
+ //pci_enable_intx(pdev);
+
+ /* initialize adapter */
+ if(pdc_hardware_init(pdev, probe_ent, board_idx) != 0)
+ goto err_out_free_ent;
+
+ ata_device_add(probe_ent);
+ kfree(probe_ent);
+
+ return 0;
+
+err_out_free_ent:
+ kfree(probe_ent);
+err_out_regions:
+ pci_release_regions(pdev);
+err_out:
+ pci_disable_device(pdev);
+ return rc;
+}
+/**
+ * pdc2027x_remove_one - Called to remove a single instance of the
+ * adapter.
+ *
+ * @dev: The PCI device to remove.
+ * FIXME: module load/unload not working yet
+ */
+static void __devexit pdc2027x_remove_one(struct pci_dev *pdev)
+{
+ ata_pci_remove_one(pdev);
+}
+/**
+ * pdc2027x_init - Called after this module is loaded into the kernel.
+ */
+static int __init pdc2027x_init(void)
+{
+ return pci_module_init(&pdc2027x_pci_driver);
+}
+/**
+ * pdc2027x_exit - Called before this module unloaded from the kernel
+ */
+static void __exit pdc2027x_exit(void)
+{
+ pci_unregister_driver(&pdc2027x_pci_driver);
+}
+
+module_init(pdc2027x_init);
+module_exit(pdc2027x_exit);
diff -Nru linux-2.6.10/include/linux/libata.h linux-2.6.10-mod/include/linux/libata.h
--- linux-2.6.10/include/linux/libata.h 2004-12-25 05:33:49.000000000 +0800
+++ linux-2.6.10-mod/include/linux/libata.h 2005-02-22 15:12:43.000000000 +0800
@@ -37,8 +37,8 @@
#undef ATA_VERBOSE_DEBUG /* yet more debugging output */
#undef ATA_IRQ_TRAP /* define to ack screaming irqs */
#undef ATA_NDEBUG /* define to disable quick runtime checks */
-#undef ATA_ENABLE_ATAPI /* define to enable ATAPI support */
-#undef ATA_ENABLE_PATA /* define to enable PATA support in some
+#define ATA_ENABLE_ATAPI /* define to enable ATAPI support */
+#define ATA_ENABLE_PATA /* define to enable PATA support in some
* low-level drivers */
#undef ATAPI_ENABLE_DMADIR /* enables ATAPI DMADIR bridge support */
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: PDC20269: Limit on number of controllers?
@ 2005-02-22 20:29 Winstel, Drew
2005-02-23 7:09 ` Albert Lee
0 siblings, 1 reply; 7+ messages in thread
From: Winstel, Drew @ 2005-02-22 20:29 UTC (permalink / raw)
To: Albert Lee; +Cc: IDE Linux
[-- Attachment #1: Type: text/plain, Size: 675 bytes --]
Albert,
Thanks for the driver. I am not sure whether you are
correct about the PLL being initialized (I don't know
enough about the internals to say for certain), but I
have attached the dmesg output from 2.6.10 compiled
with your patch and one other change to libata.h--inserted
at line 342:
int (*check_atapi_dma) (struct ata_queued_cmd *qc);
This was done entirely so it would compile cleanly. I
have yet to test ATAPI devices on it.
However, the good news is that all eight drives have been
detected and configured at UDMA 5. I will do the stress
tests on the drive overnight and let you know how things
work out.
Thanks again,
Drew
[-- Attachment #2: dmesg --]
[-- Type: application/octet-stream, Size: 32440 bytes --]
Linux version 2.6.10 (root@vets6.localdomain) (gcc version 3.2.3 20030502 (Red Hat Linux 3.2.3-20)) #2 Tue Feb 22 14:11:21 CST 2005
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 000000000fff0000 (usable)
BIOS-e820: 000000000fff0000 - 000000000fff3000 (ACPI NVS)
BIOS-e820: 000000000fff3000 - 0000000010000000 (ACPI data)
BIOS-e820: 00000000fec00000 - 00000000fec01000 (reserved)
BIOS-e820: 00000000fee00000 - 00000000fee01000 (reserved)
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
255MB LOWMEM available.
On node 0 totalpages: 65520
DMA zone: 4096 pages, LIFO batch:1
Normal zone: 61424 pages, LIFO batch:14
HighMem zone: 0 pages, LIFO batch:1
DMI 2.3 present.
ACPI: RSDP (v000 Nvidia ) @ 0x000f6b60
ACPI: RSDT (v001 Nvidia AWRDACPI 0x42302e31 AWRD 0x01010101) @ 0x0fff3000
ACPI: FADT (v001 Nvidia AWRDACPI 0x42302e31 AWRD 0x01010101) @ 0x0fff3040
ACPI: MADT (v001 Nvidia AWRDACPI 0x42302e31 AWRD 0x01010101) @ 0x0fff75c0
ACPI: DSDT (v001 NVIDIA AWRDACPI 0x00001000 MSFT 0x0100000c) @ 0x00000000
Built 1 zonelists
Kernel command line: ro root=/dev/hda8 LABEL=/ vga=792 video=vesafb:1024x768@72,ywrap,mtrr
Initializing CPU#0
CPU 0 irqstacks, hard=c04a6000 soft=c04a5000
PID hash table entries: 1024 (order: 10, 16384 bytes)
Detected 1243.452 MHz processor.
Using tsc for high-res timesource
Console: colour dummy device 80x25
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 254932k/262080k available (2437k kernel code, 6580k reserved, 1098k data, 172k init, 0k highmem)
Checking if this processor honours the WP bit even in supervisor mode... Ok.
Calibrating delay loop... 2449.40 BogoMIPS (lpj=1224704)
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
CPU: After generic identify, caps: 0383fbff c1c3fbff 00000000 00000000
CPU: After vendor identify, caps: 0383fbff c1c3fbff 00000000 00000000
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 256K (64 bytes/line)
CPU: After all inits, caps: 0383fbff c1c3fbff 00000000 00000020
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
CPU: AMD Athlon(tm) stepping 01
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
ACPI: setting ELCR to 0200 (from 0e00)
NET: Registered protocol family 16
PCI: PCI BIOS revision 2.10 entry at 0xfab70, last bus=3
PCI: Using configuration type 1
ACPI: Subsystem revision 20041105
ACPI: Interpreter enabled
ACPI: Using PIC for interrupt routing
ACPI: PCI Root Bridge [PCI0] (00:00)
PCI: Probing PCI hardware (bus 00)
PCI: nForce2 C1 Halt Disconnect fixup
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.HUB0._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.AGPB._PRT]
ACPI: PCI Interrupt Link [LNK1] (IRQs 3 4 5 6 7 *10 11 12 14 15)
ACPI: PCI Interrupt Link [LNK2] (IRQs 3 4 5 6 7 10 *11 12 14 15)
ACPI: PCI Interrupt Link [LNK3] (IRQs 3 4 5 6 7 10 *11 12 14 15)
ACPI: PCI Interrupt Link [LNK4] (IRQs 3 4 5 6 7 10 11 12 14 15) *9
ACPI: PCI Interrupt Link [LNK5] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
ACPI: PCI Interrupt Link [LUBA] (IRQs 3 4 5 6 7 10 11 12 14 15) *9
ACPI: PCI Interrupt Link [LUBB] (IRQs 3 4 5 6 7 *10 11 12 14 15)
ACPI: PCI Interrupt Link [LMAC] (IRQs 3 4 5 6 7 *10 11 12 14 15)
ACPI: PCI Interrupt Link [LAPU] (IRQs 3 4 5 6 7 10 11 12 14 15) *9
ACPI: PCI Interrupt Link [LACI] (IRQs 3 4 5 6 7 10 *11 12 14 15)
ACPI: PCI Interrupt Link [LMCI] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
ACPI: PCI Interrupt Link [LSMB] (IRQs 3 4 5 6 7 10 11 12 14 15) *9
ACPI: PCI Interrupt Link [LUB2] (IRQs 3 4 5 6 7 10 *11 12 14 15)
ACPI: PCI Interrupt Link [LFIR] (IRQs 3 4 5 6 7 *10 11 12 14 15)
ACPI: PCI Interrupt Link [L3CM] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
ACPI: PCI Interrupt Link [LIDE] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
ACPI: PCI Interrupt Link [APC1] (IRQs *16), disabled.
ACPI: PCI Interrupt Link [APC2] (IRQs *17), disabled.
ACPI: PCI Interrupt Link [APC3] (IRQs *18), disabled.
ACPI: PCI Interrupt Link [APC4] (IRQs *19), disabled.
ACPI: PCI Interrupt Link [APC5] (IRQs *16), disabled.
ACPI: PCI Interrupt Link [APCF] (IRQs 20 21 22) *0, disabled.
ACPI: PCI Interrupt Link [APCG] (IRQs 20 21 22) *0, disabled.
ACPI: PCI Interrupt Link [APCH] (IRQs 20 21 22) *0, disabled.
ACPI: PCI Interrupt Link [APCI] (IRQs 20 21 22) *0, disabled.
ACPI: PCI Interrupt Link [APCJ] (IRQs 20 21 22) *0, disabled.
ACPI: PCI Interrupt Link [APCK] (IRQs 20 21 22) *0, disabled.
ACPI: PCI Interrupt Link [APCS] (IRQs *23), disabled.
ACPI: PCI Interrupt Link [APCL] (IRQs 20 21 22) *0, disabled.
ACPI: PCI Interrupt Link [APCM] (IRQs 20 21 22) *0, disabled.
ACPI: PCI Interrupt Link [AP3C] (IRQs 20 21 22) *0, disabled.
ACPI: PCI Interrupt Link [APCZ] (IRQs 20 21 22) *0, disabled.
Linux Plug and Play Support v0.97 (c) Adam Belay
pnp: PnP ACPI init
pnp: PnP ACPI: found 16 devices
SCSI subsystem initialized
usbcore: registered new driver usbfs
usbcore: registered new driver hub
PCI: Using ACPI for IRQ routing
** PCI interrupts are no longer routed automatically. If this
** causes a device to stop working, it is probably because the
** driver failed to call pci_enable_device(). As a temporary
** workaround, the "pci=routeirq" argument restores the old
** behavior. If this argument makes the device work again,
** please email the output of "lspci" to bjorn.helgaas@hp.com
** so I can fix the driver.
pnp: 00:00: ioport range 0x1000-0x107f could not be reserved
pnp: 00:00: ioport range 0x1080-0x10ff has been reserved
pnp: 00:00: ioport range 0x1400-0x147f has been reserved
pnp: 00:00: ioport range 0x1480-0x14ff could not be reserved
pnp: 00:00: ioport range 0x1800-0x187f has been reserved
pnp: 00:00: ioport range 0x1880-0x18ff has been reserved
pnp: 00:01: ioport range 0x1c00-0x1c3f has been reserved
pnp: 00:01: ioport range 0x2000-0x203f has been reserved
Machine check exception polling timer started.
audit: initializing netlink socket (disabled)
audit(1109081571.705:0): initialized
vesafb: framebuffer at 0xd0000000, mapped to 0xd0880000, using 6144k, total 131072k
vesafb: mode is 1024x768x32, linelength=4096, pages=1
vesafb: protected mode interface info at c000:f090
vesafb: pmi: set display start = c00cf0c6, set palette = c00cf130
vesafb: pmi: ports = 3b4 3b5 3ba 3c0 3c1 3c4 3c5 3c6 3c7 3c8 3c9 3cc 3ce 3cf 3d0 3d1 3d2 3d3 3d4 3d5 3da
vesafb: scrolling: ywrap using protected mode interface, yres_virtual=1536
vesafb: Truecolor: size=8:8:8:8, shift=24:16:8:0
Console: switching to colour frame buffer device 128x48
fb0: VESA VGA frame buffer device
vga16fb: initializing
vga16fb: mapped to 0xc00a0000
fb1: VGA16 VGA frame buffer device
ACPI: Power Button (FF) [PWRF]
lp: driver loaded but no devices found
Real Time Clock Driver v1.12
Linux agpgart interface v0.100 (c) Dave Jones
agpgart: Detected NVIDIA nForce2 chipset
agpgart: Maximum main memory to use for agp memory: 203M
agpgart: AGP aperture is 64M @ 0xd8000000
serio: i8042 AUX port at 0x60,0x64 irq 12
serio: i8042 KBD port at 0x60,0x64 irq 1
Serial: 8250/16550 driver $Revision: 1.90 $ 8 ports, IRQ sharing disabled
ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
parport: PnPBIOS parport detected.
parport0: PC-style at 0x378 (0x778), irq 7 [PCSPP,TRISTATE]
lp0: using parport0 (interrupt-driven).
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
elevator: using anticipatory as default io scheduler
Floppy drive(s): fd0 is 1.44M
FDC 0 is a post-1991 82077
loop: loaded (max 8 devices)
forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.30.
ACPI: PCI Interrupt Link [LMAC] enabled at IRQ 10
PCI: setting IRQ 10 as level-triggered
ACPI: PCI interrupt 0000:00:04.0[A] -> GSI 10 (level, low) -> IRQ 10
PCI: Setting latency timer of device 0000:00:04.0 to 64
eth0: forcedeth.c: subsystem: 01458:e000 bound to 0000:00:04.0
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
NFORCE2: IDE controller at PCI slot 0000:00:09.0
NFORCE2: chipset revision 162
NFORCE2: not 100% native mode: will probe irqs later
NFORCE2: BIOS didn't set cable bits correctly. Enabling workaround.
NFORCE2: 0000:00:09.0 (rev a2) UDMA133 controller
ide0: BM-DMA at 0xf000-0xf007, BIOS settings: hda:DMA, hdb:DMA
ide1: BM-DMA at 0xf008-0xf00f, BIOS settings: hdc:DMA, hdd:DMA
Probing IDE interface ide0...
hda: TOSHIBA MK4019GAX, ATA DISK drive
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
Probing IDE interface ide1...
hdc: DVD-ROM DDU1621, ATAPI CD/DVD-ROM drive
ide1 at 0x170-0x177,0x376 on irq 15
Probing IDE interface ide2...
ide2: Wait for ready failed before probe !
Probing IDE interface ide3...
ide3: Wait for ready failed before probe !
Probing IDE interface ide4...
ide4: Wait for ready failed before probe !
Probing IDE interface ide5...
ide5: Wait for ready failed before probe !
hda: max request size: 128KiB
hda: 78140160 sectors (40007 MB), CHS=65535/16/63, UDMA(100)
hda: cache flushes supported
hda: hda1 hda2 < hda5 hda6 hda7 hda8 >
QLogic Fibre Channel HBA Driver (c0299ec0)
ide-scsi is deprecated for cd burning! Use ide-cd and give dev=/dev/hdX as device
scsi0 : SCSI host adapter emulation for IDE ATAPI devices
Vendor: SONY Model: DVD-ROM DDU1621 Rev: S4.0
Type: CD-ROM ANSI SCSI revision: 02
libata version 1.10 loaded.
pata_pdc2027x version 0.56
ACPI: PCI Interrupt Link [LNK4] enabled at IRQ 11
PCI: setting IRQ 11 as level-triggered
ACPI: PCI interrupt 0000:01:07.0[A] -> GSI 11 (level, low) -> IRQ 11
pdc_detect_pll_input_clock: ctr0[DA] ctr1[B] ctr2 [0] ctr3 [7C]
pdc_detect_pll_input_clock: scr1[E]
pdc_detect_pll_input_clock: ctr0[6E] ctr1[4B] ctr2 [FF] ctr3 [7B]
pdc_detect_pll_input_clock: scr1[4E]
pdc_detect_pll_input_clock: start[1040190426] end[1040173934]
pdc_detect_pll_input_clock: PLL input clock[16492000]Hz
pata_pdc2027x: PLL input clock 16492 kHz
pdc_adjust_pll: pout_required is 133333333
pdc_adjust_pll: pll_ctl[57][D]
pdc_adjust_pll: F[119] R[13] ratio*1000[8084]
pdc_adjust_pll: Writing pll_ctl[77][D]
pdc_adjust_pll: pll_ctl[77][D]
ata1: PATA max UDMA/133 cmd 0x3C00 ctl 0x4002 bmdma 0x4C00 irq 11
ata2: PATA max UDMA/133 cmd 0x4400 ctl 0x4802 bmdma 0x4C08 irq 11
pdc_get_indexed_reg: Get index reg4[52]
pdc_get_indexed_reg: Get index regB[80]
pdc2027x_cbl_detect: No cable or 80-conductor cable on port 0
ata1: dev 0 cfg 49:2f00 82:7c6b 83:5908 84:4003 85:7c68 86:1808 87:4003 88:203f
ata1: dev 0 ATA, max UDMA/100, 78140160 sectors:
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
ata1: dev 0 configured for UDMA/100
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
scsi1 : pata_pdc2027x
pdc_get_indexed_reg: Get index reg4[52]
pdc_get_indexed_reg: Get index regB[80]
pdc2027x_cbl_detect: No cable or 80-conductor cable on port 1
ata2: dev 0 cfg 49:2f00 82:7c6b 83:5908 84:4003 85:7c68 86:1808 87:4003 88:203f
ata2: dev 0 ATA, max UDMA/100, 78140160 sectors:
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
ata2: dev 0 configured for UDMA/100
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
scsi2 : pata_pdc2027x
Vendor: ATA Model: TOSHIBA MK4019GA Rev: FA00
Type: Direct-Access ANSI SCSI revision: 05
Vendor: ATA Model: TOSHIBA MK4019GA Rev: FA00
Type: Direct-Access ANSI SCSI revision: 05
ACPI: PCI Interrupt Link [LNK1] enabled at IRQ 10
ACPI: PCI interrupt 0000:01:08.0[A] -> GSI 10 (level, low) -> IRQ 10
pdc_detect_pll_input_clock: ctr0[0] ctr1[0] ctr2 [0] ctr3 [0]
pdc_detect_pll_input_clock: scr1[E]
pdc_detect_pll_input_clock: ctr0[94] ctr1[3F] ctr2 [FF] ctr3 [7F]
pdc_detect_pll_input_clock: scr1[4E]
pdc_detect_pll_input_clock: start[0] end[1073725332]
pdc_detect_pll_input_clock: PLL input clock[16492000]Hz
pata_pdc2027x: PLL input clock 16492 kHz
pdc_adjust_pll: pout_required is 133333333
pdc_adjust_pll: pll_ctl[57][D]
pdc_adjust_pll: F[119] R[13] ratio*1000[8084]
pdc_adjust_pll: Writing pll_ctl[77][D]
pdc_adjust_pll: pll_ctl[77][D]
ata3: PATA max UDMA/133 cmd 0x5000 ctl 0x5402 bmdma 0x6000 irq 10
ata4: PATA max UDMA/133 cmd 0x5800 ctl 0x5C02 bmdma 0x6008 irq 10
pdc_get_indexed_reg: Get index reg4[52]
pdc_get_indexed_reg: Get index regB[80]
pdc2027x_cbl_detect: No cable or 80-conductor cable on port 0
ata3: dev 0 cfg 49:2f00 82:7c6b 83:5908 84:4003 85:7c68 86:1808 87:4003 88:203f
ata3: dev 0 ATA, max UDMA/100, 78140160 sectors:
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
ata3: dev 0 configured for UDMA/100
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
scsi3 : pata_pdc2027x
pdc_get_indexed_reg: Get index reg4[52]
pdc_get_indexed_reg: Get index regB[80]
pdc2027x_cbl_detect: No cable or 80-conductor cable on port 1
ata4: dev 1 cfg 49:2f00 82:7c6b 83:5908 84:4003 85:7c68 86:1808 87:4003 88:203f
ata4: dev 1 ATA, max UDMA/100, 78140160 sectors:
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index reg14[23]
pdc_set_indexed_reg: Set index reg15[9]
pdc_set_indexed_reg: Set index reg1B[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg18[1A]
pdc_set_indexed_reg: Set index reg19[2]
pdc_set_indexed_reg: Set index reg1A[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
ata4: dev 1 configured for UDMA/100
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index reg14[23]
pdc_set_indexed_reg: Set index reg15[9]
pdc_set_indexed_reg: Set index reg1B[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg18[1A]
pdc_set_indexed_reg: Set index reg19[2]
pdc_set_indexed_reg: Set index reg1A[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
scsi4 : pata_pdc2027x
Vendor: ATA Model: TOSHIBA MK4019GA Rev: FA00
Type: Direct-Access ANSI SCSI revision: 05
Vendor: ATA Model: TOSHIBA MK4021GA Rev: GA22
Type: Direct-Access ANSI SCSI revision: 05
ACPI: PCI Interrupt Link [LNK2] enabled at IRQ 11
ACPI: PCI interrupt 0000:01:09.0[A] -> GSI 11 (level, low) -> IRQ 11
pdc_detect_pll_input_clock: ctr0[0] ctr1[0] ctr2 [0] ctr3 [0]
pdc_detect_pll_input_clock: scr1[E]
pdc_detect_pll_input_clock: ctr0[94] ctr1[3F] ctr2 [FF] ctr3 [7F]
pdc_detect_pll_input_clock: scr1[4E]
pdc_detect_pll_input_clock: start[0] end[1073725332]
pdc_detect_pll_input_clock: PLL input clock[16492000]Hz
pata_pdc2027x: PLL input clock 16492 kHz
pdc_adjust_pll: pout_required is 133333333
pdc_adjust_pll: pll_ctl[58][4D]
pdc_adjust_pll: F[119] R[13] ratio*1000[8084]
pdc_adjust_pll: Writing pll_ctl[77][D]
pdc_adjust_pll: pll_ctl[77][D]
ata5: PATA max UDMA/133 cmd 0x6400 ctl 0x6802 bmdma 0x7400 irq 11
ata6: PATA max UDMA/133 cmd 0x6C00 ctl 0x7002 bmdma 0x7408 irq 11
pdc_get_indexed_reg: Get index reg4[52]
pdc_get_indexed_reg: Get index regB[80]
pdc2027x_cbl_detect: No cable or 80-conductor cable on port 0
ata5: dev 0 cfg 49:2f00 82:7c6b 83:5908 84:4003 85:7c68 86:1808 87:4003 88:003f
ata5: dev 0 ATA, max UDMA/100, 78140160 sectors:
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
ata5: dev 0 configured for UDMA/100
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
scsi5 : pata_pdc2027x
pdc_get_indexed_reg: Get index reg4[52]
pdc_get_indexed_reg: Get index regB[80]
pdc2027x_cbl_detect: No cable or 80-conductor cable on port 1
ata6: dev 0 cfg 49:2f00 82:7c6b 83:5908 84:4003 85:7c68 86:1808 87:4003 88:003f
ata6: dev 0 ATA, max UDMA/100, 78140160 sectors:
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
ata6: dev 0 configured for UDMA/100
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
scsi6 : pata_pdc2027x
Vendor: ATA Model: TOSHIBA MK4019GA Rev: FA00
Type: Direct-Access ANSI SCSI revision: 05
Vendor: ATA Model: TOSHIBA MK4019GA Rev: FA00
Type: Direct-Access ANSI SCSI revision: 05
ACPI: PCI Interrupt Link [LNK3] enabled at IRQ 11
ACPI: PCI interrupt 0000:01:0a.0[A] -> GSI 11 (level, low) -> IRQ 11
pdc_detect_pll_input_clock: ctr0[0] ctr1[0] ctr2 [0] ctr3 [0]
pdc_detect_pll_input_clock: scr1[E]
pdc_detect_pll_input_clock: ctr0[93] ctr1[3F] ctr2 [FF] ctr3 [7F]
pdc_detect_pll_input_clock: scr1[4E]
pdc_detect_pll_input_clock: start[0] end[1073725331]
pdc_detect_pll_input_clock: PLL input clock[16493000]Hz
pata_pdc2027x: PLL input clock 16493 kHz
pdc_adjust_pll: pout_required is 133333333
pdc_adjust_pll: pll_ctl[58][4D]
pdc_adjust_pll: F[119] R[13] ratio*1000[8084]
pdc_adjust_pll: Writing pll_ctl[77][D]
pdc_adjust_pll: pll_ctl[77][D]
ata7: PATA max UDMA/133 cmd 0x7800 ctl 0x7C02 bmdma 0x8800 irq 11
ata8: PATA max UDMA/133 cmd 0x8000 ctl 0x8402 bmdma 0x8808 irq 11
pdc_get_indexed_reg: Get index reg4[52]
pdc_get_indexed_reg: Get index regB[80]
pdc2027x_cbl_detect: No cable or 80-conductor cable on port 0
ata7: dev 0 cfg 49:2f00 82:7c6b 83:5908 84:4003 85:7c68 86:1808 87:4003 88:003f
ata7: dev 0 ATA, max UDMA/100, 78140160 sectors:
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
ata7: dev 0 configured for UDMA/100
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
scsi7 : pata_pdc2027x
pdc_get_indexed_reg: Get index reg4[52]
pdc_get_indexed_reg: Get index regB[80]
pdc2027x_cbl_detect: No cable or 80-conductor cable on port 1
ata8: dev 0 cfg 49:2b00 82:346b 83:5b29 84:4003 85:3468 86:1a09 87:4003 88:003f
ata8: dev 0 ATA, max UDMA/100, 156301488 sectors:
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
ata8: dev 0 configured for UDMA/100
pdc2027x_set_piomode: adev->pio_mode[C]
pdc2027x_set_piomode: Set pio regs...
pdc_set_indexed_reg: Set index regC[23]
pdc_set_indexed_reg: Set index regD[9]
pdc_set_indexed_reg: Set index reg13[25]
pdc2027x_set_piomode: Set pio regs done
pdc2027x_set_piomode: Set to pio mode[4]
pdc2027x_set_dmamode: Set udma regs...
pdc_set_indexed_reg: Set index reg10[1A]
pdc_set_indexed_reg: Set index reg11[2]
pdc_set_indexed_reg: Set index reg12[CB]
pdc2027x_set_dmamode: Set udma regs done
pdc2027x_set_dmamode: Set to udma mode[5]
scsi8 : pata_pdc2027x
Vendor: ATA Model: TOSHIBA MK4019GA Rev: FA00
Type: Direct-Access ANSI SCSI revision: 05
Vendor: ATA Model: FUJITSU MHT2080A Rev: 0021
Type: Direct-Access ANSI SCSI revision: 05
SCSI device sda: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sda: drive cache: write back
SCSI device sda: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sda: drive cache: write back
sda: unknown partition table
Attached scsi disk sda at scsi1, channel 0, id 0, lun 0
SCSI device sdb: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sdb: drive cache: write back
SCSI device sdb: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sdb: drive cache: write back
sdb: unknown partition table
Attached scsi disk sdb at scsi2, channel 0, id 0, lun 0
SCSI device sdc: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sdc: drive cache: write back
SCSI device sdc: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sdc: drive cache: write back
sdc: unknown partition table
Attached scsi disk sdc at scsi3, channel 0, id 0, lun 0
SCSI device sdd: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sdd: drive cache: write back
SCSI device sdd: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sdd: drive cache: write back
sdd: unknown partition table
Attached scsi disk sdd at scsi4, channel 0, id 1, lun 0
SCSI device sde: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sde: drive cache: write back
SCSI device sde: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sde: drive cache: write back
sde: unknown partition table
Attached scsi disk sde at scsi5, channel 0, id 0, lun 0
SCSI device sdf: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sdf: drive cache: write back
SCSI device sdf: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sdf: drive cache: write back
sdf: unknown partition table
Attached scsi disk sdf at scsi6, channel 0, id 0, lun 0
SCSI device sdg: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sdg: drive cache: write back
SCSI device sdg: 78140160 512-byte hdwr sectors (40008 MB)
SCSI device sdg: drive cache: write back
sdg: unknown partition table
Attached scsi disk sdg at scsi7, channel 0, id 0, lun 0
SCSI device sdh: 156301488 512-byte hdwr sectors (80026 MB)
SCSI device sdh: drive cache: write back
SCSI device sdh: 156301488 512-byte hdwr sectors (80026 MB)
SCSI device sdh: drive cache: write back
sdh: unknown partition table
Attached scsi disk sdh at scsi8, channel 0, id 0, lun 0
sr0: scsi3-mmc drive: 40x/40x cd/rw xa/form2 cdda tray
Uniform CD-ROM driver Revision: 3.20
Attached scsi CD-ROM sr0 at scsi0, channel 0, id 0, lun 0
Attached scsi generic sg0 at scsi0, channel 0, id 0, lun 0, type 5
Attached scsi generic sg1 at scsi1, channel 0, id 0, lun 0, type 0
Attached scsi generic sg2 at scsi2, channel 0, id 0, lun 0, type 0
Attached scsi generic sg3 at scsi3, channel 0, id 0, lun 0, type 0
Attached scsi generic sg4 at scsi4, channel 0, id 1, lun 0, type 0
Attached scsi generic sg5 at scsi5, channel 0, id 0, lun 0, type 0
Attached scsi generic sg6 at scsi6, channel 0, id 0, lun 0, type 0
Attached scsi generic sg7 at scsi7, channel 0, id 0, lun 0, type 0
Attached scsi generic sg8 at scsi8, channel 0, id 0, lun 0, type 0
Fusion MPT base driver 3.01.18
Copyright (c) 1999-2004 LSI Logic Corporation
Fusion MPT SCSI Host driver 3.01.18
usbcore: registered new driver usblp
drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
Initializing USB Mass Storage driver...
usbcore: registered new driver usb-storage
USB Mass Storage support registered.
mice: PS/2 mouse device common for all mice
input: AT Translated Set 2 keyboard on isa0060/serio0
input: ImExPS/2 Logitech Explorer Mouse on isa0060/serio1
NET: Registered protocol family 2
IP: routing cache hash table of 2048 buckets, 16Kbytes
TCP: Hash tables configured (established 16384 bind 32768)
ip_conntrack version 2.1 (2047 buckets, 16376 max) - 300 bytes per conntrack
ip_tables: (C) 2000-2002 Netfilter core team
ipt_recent v0.3.1: Stephen Frost <sfrost@snowman.net>. http://snowman.net/projects/ipt_recent/
arp_tables: (C) 2002 David S. Miller
NET: Registered protocol family 1
NET: Registered protocol family 17
kjournald starting. Commit interval 5 seconds
EXT3-fs: mounted filesystem with ordered data mode.
VFS: Mounted root (ext3 filesystem) readonly.
Freeing unused kernel memory: 172k freed
EXT3 FS on hda8, internal journal
Adding 1000400k swap on /dev/hda6. Priority:-1 extents:1
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
program scsi_unique_id is using a deprecated SCSI ioctl, please convert it to SG_IO
kjournald starting. Commit interval 5 seconds
EXT3 FS on hda5, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: PDC20269: Limit on number of controllers?
2005-02-22 20:29 Winstel, Drew
@ 2005-02-23 7:09 ` Albert Lee
0 siblings, 0 replies; 7+ messages in thread
From: Albert Lee @ 2005-02-23 7:09 UTC (permalink / raw)
To: Winstel, Drew; +Cc: IDE Linux
Winstel, Drew wrote:
> I am not sure whether you are
> correct about the PLL being initialized (I don't know
> enough about the internals to say for certain), but I
> have attached the dmesg output from 2.6.10 compiled
> with your patch
Thanks for the testing and dmesg. From the dmesg, we can see
1st adapter: pll_ctl[57][D] => PLL initialized by the firmware
2nd adapter: pll_ctl[57][D] => PLL initialized by the firmware
3rd adapter: pll_ctl[58][4D] => PLL uninitialized
4th adapter: pll_ctl[58][4D] => PLL uninitialized
So, the firmware on the pdc20269 only initialize the 1st and 2nd adapters.
PLL of adapter 3/4 are left uninitialized by the firmware.
The pdc202xx_new driver relies on the firmware to initialize the PLL.
That's why adapter 3/4 won't work.
> I have yet to test ATAPI devices on it.
With 2.6.10 + pdc20269, there is a known problem on ATAPI DMA.
Please use 2.6.11 to test ATAPI.
Albert
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: PDC20269: Limit on number of controllers?
@ 2005-02-23 20:58 Winstel, Drew
2005-02-24 5:35 ` Albert Lee
0 siblings, 1 reply; 7+ messages in thread
From: Winstel, Drew @ 2005-02-23 20:58 UTC (permalink / raw)
To: Albert Lee; +Cc: IDE Linux
Hello again,
>With 2.6.10 + pdc20269, there is a known problem on ATAPI DMA.
>Please use 2.6.11 to test ATAPI.
Easier said than done. Using 2.6.11-rc4-bk9, I get an oops
(see below) with any drives attached. This occurs whether I
use one or four controllers.
How might I get to working around this? I'll try the next
snapshot that includes the latest round of libata fixes to
see if it helps.
Thanks again,
Drew
SCSI device sda: drive cache: write back
sda:<1>Unable to handle kernel NULL pointer dereference at virtual address 00000000
printing eip:
00000000
*pde=00000000
Oops: 0000 [#1]
Modules linked in:
CPU: 0
EIP: 0060:[<00000000>] Not tainted VLI
EFLAGS: 00010093 (2.6.11-rc4-bk9)
EIP is at 0x0 c13071bc
eax: c044c1c0 ebx: c13071bc ecx: c13bd880 edx: 00000032
esi: 00000000 edi: c1307688 ebp: c13928e0 esp: c04b7f90
ds: 007b es: 0007b ss:0068
Process swapper (pid: 0, threadinfo=c04b7000 task=c03dbb20)
Stack: c02c54f6 c13071bc c0484fa0 c0484fa0 00000282 00000000 c13bd880 00000000
c0484fa0 0000000b c012be20 0000000b c13928e0 c0484fa0 00000000 0000000b
c0483cc0 c13bd880 c0484fa0 c012bf0b 0000000b c0483a00 00000001 c0484f90
Call Trace:
[<c02c54f6>] ata_interrupt+0x76/0x110
[<c012be20>] handle_IRQ_event+0x30/0x70
[<c012bf0b>] __do_IRQ_event+0xab/0x120
[<c0104162>] do_IRQ+0x42/0x70
========================
[<c0100570>] default_idle+0x0/0x30
[<c010283e>] common_interrupt+0x1a/0x20
[<c0100570>] default_idle+0x0/0x30
[<c0100594>] default_idle+0x24/0x30
[<c010062c>] cpu_idle+0x4c/0x60
[<c048575c>] start_kernel+0x13c/0x160
[<c0485330>] unknown_bootoption+0x0/0x1e0
Code: Bad EIP value.
<0>Kernel panic - not syncing: Fatal exception in interrupt
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: PDC20269: Limit on number of controllers?
2005-02-23 20:58 PDC20269: Limit on number of controllers? Winstel, Drew
@ 2005-02-24 5:35 ` Albert Lee
0 siblings, 0 replies; 7+ messages in thread
From: Albert Lee @ 2005-02-24 5:35 UTC (permalink / raw)
To: Winstel, Drew; +Cc: IDE Linux
Winstel, Drew wrote:
> Hello again,
>
>
>>With 2.6.10 + pdc20269, there is a known problem on ATAPI DMA.
>>Please use 2.6.11 to test ATAPI.
>
> Easier said than done. Using 2.6.11-rc4-bk9, I get an oops
> (see below) with any drives attached. This occurs whether I
> use one or four controllers.
>
> How might I get to working around this? I'll try the next
> snapshot that includes the latest round of libata fixes to
> see if it helps.
>
The 2.6.11-rc4 needs .bmdma_stop and .bmdma_status to be defined.
Attached please find the debug patch with the needed hooks. Thanks.
Albert
===================================================================================
diff -Nru linux-2.6.10/drivers/scsi/Kconfig linux-2.6.10-mod/drivers/scsi/Kconfig
--- linux-2.6.10/drivers/scsi/Kconfig 2004-12-25 05:35:28.000000000 +0800
+++ linux-2.6.10-mod/drivers/scsi/Kconfig 2005-02-22 15:11:57.000000000 +0800
@@ -441,6 +441,14 @@
If unsure, say N.
+config SCSI_PATA_PDC2027X
+ tristate "Promise PATA 2027x support"
+ depends on SCSI_SATA && PCI
+ help
+ This option enables support for Promise PATA pdc20268 to pdc20277 host adapters.
+
+ If unsure, say N.
+
config SCSI_SATA_PROMISE
tristate "Promise SATA TX2/TX4 support"
depends on SCSI_SATA && PCI
diff -Nru linux-2.6.10/drivers/scsi/Makefile linux-2.6.10-mod/drivers/scsi/Makefile
--- linux-2.6.10/drivers/scsi/Makefile 2004-12-25 05:35:24.000000000 +0800
+++ linux-2.6.10-mod/drivers/scsi/Makefile 2005-02-22 15:12:18.000000000 +0800
@@ -124,6 +124,7 @@
obj-$(CONFIG_SCSI_SATA_AHCI) += libata.o ahci.o
obj-$(CONFIG_SCSI_SATA_SVW) += libata.o sata_svw.o
obj-$(CONFIG_SCSI_ATA_PIIX) += libata.o ata_piix.o
+obj-$(CONFIG_SCSI_PATA_PDC2027X)+= libata.o pata_pdc2027x.o
obj-$(CONFIG_SCSI_SATA_PROMISE) += libata.o sata_promise.o
obj-$(CONFIG_SCSI_SATA_SIL) += libata.o sata_sil.o
obj-$(CONFIG_SCSI_SATA_VIA) += libata.o sata_via.o
diff -Nru linux-2.6.10/drivers/scsi/pata_pdc2027x.c linux-2.6.10-mod/drivers/scsi/pata_pdc2027x.c
--- linux-2.6.10/drivers/scsi/pata_pdc2027x.c 1970-01-01 08:00:00.000000000 +0800
+++ linux-2.6.10-mod/drivers/scsi/pata_pdc2027x.c 2005-02-24 13:17:38.000000000 +0800
@@ -0,0 +1,771 @@
+/*
+ * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Ported to libata by:
+ * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
+ *
+ * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
+ * Portions Copyright (C) 1999 Promise Technology, Inc.
+ *
+ * Author: Frank Tiernan (frankt@promise.com)
+ * Released under terms of General Public License
+ *
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include "scsi.h"
+#include <scsi/scsi_host.h>
+#include <linux/libata.h>
+#include <asm/io.h>
+
+#define DRV_NAME "pata_pdc2027x"
+#define DRV_VERSION "0.57"
+#define PDC_DEBUG
+
+#ifdef PDC_DEBUG
+#define PDPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__, ## args)
+#else
+#define PDPRINTK(fmt, args...)
+#endif
+
+enum {
+ PDC_UDMA_100 = 0,
+ PDC_UDMA_133 = 1,
+
+ PDC_100_MHZ = 100000000,
+ PDC_133_MHZ = 133333333,
+};
+
+static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
+static void pdc2027x_remove_one(struct pci_dev *pdev);
+static void pdc2027x_phy_reset(struct ata_port *ap);
+static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
+static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
+static void pdc2027x_post_set_mode(struct ata_port *ap);
+static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
+
+/*
+ * ATA Timing Tables based on 133MHz controller clock.
+ * These tables are only used when the controller is in 133MHz clock.
+ * If the controller is in 100MHz clock, the ASIC hardware will
+ * set the timing registers automatically when "set feature" command
+ * is issued to the device. However, if the controller clock is 133MHz,
+ * the following tables must be used.
+ */
+static struct pdc2027x_pio_timing {
+ u8 value0, value1, value2;
+} pdc2027x_pio_timing_tbl [] = {
+ { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
+ { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
+ { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
+ { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
+ { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
+};
+
+static struct pdc2027x_mdma_timing {
+ u8 value0, value1;
+} pdc2027x_mdma_timing_tbl [] = {
+ { 0xdf, 0x5f }, /* MDMA mode 0 */
+ { 0x6b, 0x27 }, /* MDMA mode 1 */
+ { 0x69, 0x25 }, /* MDMA mode 2 */
+};
+
+static struct pdc2027x_udma_timing {
+ u8 value0, value1, value2;
+} pdc2027x_udma_timing_tbl [] = {
+ { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
+ { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
+ { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
+ { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
+ { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
+ { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
+ { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
+};
+
+static struct pci_device_id pdc2027x_pci_tbl[] = {
+#ifdef ATA_ENABLE_PATA
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_100 },
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_100 },
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
+ { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
+#endif
+ { } /* terminate list */
+};
+
+static struct pci_driver pdc2027x_pci_driver = {
+ .name = DRV_NAME,
+ .id_table = pdc2027x_pci_tbl,
+ .probe = pdc2027x_init_one,
+ .remove = __devexit_p(pdc2027x_remove_one),
+};
+
+static Scsi_Host_Template pdc2027x_sht = {
+ .module = THIS_MODULE,
+ .name = DRV_NAME,
+ .queuecommand = ata_scsi_queuecmd,
+ .eh_strategy_handler = ata_scsi_error,
+ .can_queue = ATA_DEF_QUEUE,
+ .this_id = ATA_SHT_THIS_ID,
+ .sg_tablesize = LIBATA_MAX_PRD,
+ .max_sectors = ATA_MAX_SECTORS,
+ .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
+ .emulated = ATA_SHT_EMULATED,
+ .use_clustering = ATA_SHT_USE_CLUSTERING,
+ .proc_name = DRV_NAME,
+ .dma_boundary = ATA_DMA_BOUNDARY,
+ .slave_configure = ata_scsi_slave_config,
+ .bios_param = ata_std_bios_param,
+};
+
+static struct ata_port_operations pdc2027x_pata100_ops = {
+ .port_disable = ata_port_disable,
+
+ .tf_load = ata_tf_load,
+ .tf_read = ata_tf_read,
+ .check_status = ata_check_status,
+ .exec_command = ata_exec_command,
+ .dev_select = ata_std_dev_select,
+
+ .phy_reset = pdc2027x_phy_reset,
+
+ .check_atapi_dma = pdc2027x_check_atapi_dma,
+ .bmdma_setup = ata_bmdma_setup,
+ .bmdma_start = ata_bmdma_start,
+ .bmdma_stop = ata_bmdma_stop,
+ .bmdma_status = ata_bmdma_status,
+ .qc_prep = ata_qc_prep,
+ .qc_issue = ata_qc_issue_prot,
+ .eng_timeout = ata_eng_timeout,
+
+ .irq_handler = ata_interrupt,
+ .irq_clear = ata_bmdma_irq_clear,
+
+ .port_start = ata_port_start,
+ .port_stop = ata_port_stop,
+};
+
+static struct ata_port_operations pdc2027x_pata133_ops = {
+ .port_disable = ata_port_disable,
+ .set_piomode = pdc2027x_set_piomode,
+ .set_dmamode = pdc2027x_set_dmamode,
+
+ .tf_load = ata_tf_load,
+ .tf_read = ata_tf_read,
+ .check_status = ata_check_status,
+ .exec_command = ata_exec_command,
+ .dev_select = ata_std_dev_select,
+
+ .phy_reset = pdc2027x_phy_reset,
+ .post_set_mode = pdc2027x_post_set_mode,
+
+ .check_atapi_dma = pdc2027x_check_atapi_dma,
+ .bmdma_setup = ata_bmdma_setup,
+ .bmdma_start = ata_bmdma_start,
+ .bmdma_stop = ata_bmdma_stop,
+ .bmdma_status = ata_bmdma_status,
+ .qc_prep = ata_qc_prep,
+ .qc_issue = ata_qc_issue_prot,
+ .eng_timeout = ata_eng_timeout,
+
+ .irq_handler = ata_interrupt,
+ .irq_clear = ata_bmdma_irq_clear,
+
+ .port_start = ata_port_start,
+ .port_stop = ata_port_stop,
+};
+
+static struct ata_port_info pdc2027x_port_info[] = {
+ /* PDC_UDMA_100 */
+ {
+ .sht = &pdc2027x_sht,
+ .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
+ ATA_FLAG_SRST,
+ .pio_mask = 0x1f, /* pio0-4 */
+ .mwdma_mask = 0x07, /* mwdma0-2 */
+ .udma_mask = ATA_UDMA5, /* udma0-5 */
+ .port_ops = &pdc2027x_pata100_ops,
+ },
+ /* PDC_UDMA_133 */
+ {
+ .sht = &pdc2027x_sht,
+ .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
+ ATA_FLAG_SRST,
+ .pio_mask = 0x1f, /* pio0-4 */
+ .mwdma_mask = 0x07, /* mwdma0-2 */
+ .udma_mask = ATA_UDMA6, /* udma0-6 */
+ .port_ops = &pdc2027x_pata133_ops,
+ },
+};
+
+MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
+MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
+MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
+
+/**
+ * pdc_get_indexed_reg - Set pdc202xx extended register
+ * @ap: Port to which the extended register is set
+ * @index: index of the extended register
+ */
+static u8 pdc_get_indexed_reg(struct ata_port *ap, u8 index)
+{
+ u8 tmp8;
+
+ outb(index, ap->ioaddr.bmdma_addr + 1);
+ tmp8 = inb(ap->ioaddr.bmdma_addr + 3);
+
+ PDPRINTK("Get index reg%X[%X] \n", index, tmp8);
+ return tmp8;
+}
+/**
+ * pdc_set_indexed_reg - Read pdc202xx extended register
+ * @ap: Port to which the extended register is read
+ * @index: index of the extended register
+ */
+static void pdc_set_indexed_reg(struct ata_port *ap, u8 index, u8 value)
+{
+ outb(index, ap->ioaddr.bmdma_addr + 1);
+ outb(value, ap->ioaddr.bmdma_addr + 3);
+ PDPRINTK("Set index reg%X[%X] \n", index, value);
+}
+/**
+ * pdc2027x_pata_cbl_detect - Probe host controller cable detect info
+ * @ap: Port for which cable detect info is desired
+ *
+ * Read 80c cable indicator from Promise extended register.
+ * This register is latched when the system is reset.
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+static void pdc2027x_cbl_detect(struct ata_port *ap)
+{
+ u8 cbl40c;
+
+ /* check cable detect results */
+ cbl40c = pdc_get_indexed_reg(ap, 0x0b) & 0x04;
+
+ if (cbl40c)
+ goto cbl40;
+
+ PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
+
+ ap->cbl = ATA_CBL_PATA80;
+ return;
+
+cbl40:
+ printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
+ ap->cbl = ATA_CBL_PATA40;
+ ap->udma_mask &= ATA_UDMA_MASK_40C;
+}
+/**
+ * pdc2027x_port_enabled - Check extended register at 0x04 to see whether the port is enabled.
+ * @ap: Port to check
+ */
+static inline int pdc2027x_port_enabled(struct ata_port *ap)
+{
+ return pdc_get_indexed_reg(ap, 0x04) & 0x02;
+}
+/**
+ * pdc2027x_phy_reset - Probe specified port on PATA host controller
+ * @ap: Port to probe
+ *
+ * Probe PATA phy.
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+static void pdc2027x_phy_reset(struct ata_port *ap)
+{
+ /* Check whether port enabled */
+ if (!pdc2027x_port_enabled(ap)) {
+ ata_port_disable(ap);
+ printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
+ return;
+ }
+
+ pdc2027x_cbl_detect(ap);
+ ata_port_probe(ap);
+ ata_bus_reset(ap);
+}
+/**
+ * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
+ * @ap: Port to configure
+ * @adev: um
+ * @pio: PIO mode, 0 - 4
+ *
+ * Set PIO mode for device.
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+ unsigned int pio = adev->pio_mode - XFER_PIO_0;
+ unsigned int drive_dn = (ap->port_no ? 2 : 0) + adev->devno;
+ u8 adj = (drive_dn%2) ? 0x08 : 0x00;
+
+ PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
+
+ /* Sanity check */
+ if(pio > 4) {
+ printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
+ return;
+
+ }
+
+ /* Set the PIO timing registers using value table for 133MHz */
+ PDPRINTK("Set pio regs... \n");
+
+ pdc_set_indexed_reg(ap, 0x0c + adj, pdc2027x_pio_timing_tbl[pio].value0);
+ pdc_set_indexed_reg(ap, 0x0d + adj, pdc2027x_pio_timing_tbl[pio].value1);
+ pdc_set_indexed_reg(ap, 0x13 + adj, pdc2027x_pio_timing_tbl[pio].value2);
+
+ PDPRINTK("Set pio regs done\n");
+
+ PDPRINTK("Set to pio mode[%u] \n", pio);
+}
+/**
+ * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
+ * @ap: Port to configure
+ * @adev: um
+ * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
+ *
+ * Set UDMA mode for device.
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ */
+static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
+{
+ unsigned int dma_mode = adev->dma_mode;
+ unsigned int drive_dn = (ap->port_no ? 2 : 0) + adev->devno;
+ u8 adj = (drive_dn%2) ? 0x08 : 0x00;
+ u8 tmp8;
+
+ if((dma_mode >= XFER_UDMA_0) &&
+ (dma_mode <= XFER_UDMA_6)) {
+ /* Set the UDMA timing registers with value table for 133MHz */
+ unsigned int udma_mode = dma_mode & 0x07;
+
+ if (dma_mode == XFER_UDMA_2) {
+ /*
+ * Turn off tHOLD.
+ * If tHOLD is '1', the hardware will add half clock for data hold time.
+ * This code segment seems to be no effect. tHOLD will be overwritten below.
+ */
+ tmp8 = pdc_get_indexed_reg(ap, 0x10 + adj);
+ pdc_set_indexed_reg(ap, 0x10 + adj, tmp8 & 0x7f);
+ }
+
+ PDPRINTK("Set udma regs... \n");
+ pdc_set_indexed_reg(ap, 0x10 + adj, pdc2027x_udma_timing_tbl[udma_mode].value0);
+ pdc_set_indexed_reg(ap, 0x11 + adj, pdc2027x_udma_timing_tbl[udma_mode].value1);
+ pdc_set_indexed_reg(ap, 0x12 + adj, pdc2027x_udma_timing_tbl[udma_mode].value2);
+ PDPRINTK("Set udma regs done\n");
+
+ PDPRINTK("Set to udma mode[%u] \n", udma_mode);
+
+ } else if((dma_mode >= XFER_MW_DMA_0) &&
+ (dma_mode <= XFER_MW_DMA_2)) {
+ /* Set the MDMA timing registers with value table for 133MHz */
+ unsigned int mdma_mode = dma_mode & 0x07;
+
+ PDPRINTK("Set mdma regs... \n");
+ pdc_set_indexed_reg(ap, 0x0e + adj, pdc2027x_mdma_timing_tbl[mdma_mode].value0);
+ pdc_set_indexed_reg(ap, 0x0f + adj, pdc2027x_mdma_timing_tbl[mdma_mode].value1);
+ PDPRINTK("Set mdma regs done\n");
+
+ PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
+ } else {
+ printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
+ }
+}
+
+/**
+ * pdc2027x_post_set_mode - Set the timing registers back to correct values.
+ * @ap: Port to configure
+ *
+ * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
+ * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
+ * This function overwrites the possibly incorrect values set by the hardware to be correct.
+ */
+static void pdc2027x_post_set_mode(struct ata_port *ap)
+{
+ int i;
+
+ for (i = 0; i < ATA_MAX_DEVICES; i++) {
+ struct ata_device *dev = &ap->device[i];
+
+ if (ata_dev_present(dev)) {
+ u8 adj = (i % 2) ? 0x08 : 0x00;
+ u8 tmp8;
+
+ pdc2027x_set_piomode(ap, dev);
+
+ /*
+ * Enable prefetch if the device support PIO only.
+ */
+ if (dev->xfer_shift == ATA_SHIFT_PIO) {
+ tmp8 = pdc_get_indexed_reg(ap, 0x13 + adj);
+ pdc_set_indexed_reg(ap, 0x13 + adj, tmp8 | 0x02);
+
+ PDPRINTK("Turn on prefetch\n");
+ } else {
+ pdc2027x_set_dmamode(ap, dev);
+ }
+ }
+ }
+}
+
+/**
+ * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
+ * @qc: Metadata associated with taskfile to check
+ *
+ * LOCKING:
+ * None (inherited from caller).
+ *
+ * RETURNS: 0 when ATAPI DMA can be used
+ * 1 otherwise
+ */
+static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
+{
+ struct scsi_cmnd *cmd = qc->scsicmd;
+ int rc = 0;
+
+ /* pdc2027x can only do ATAPI DMA for specific buffer size */
+ if (cmd->request_bufflen % 256)
+ rc = 1;
+
+ return rc;
+}
+
+/**
+ * adjust_pll - Adjust the PLL input clock in Hz.
+ *
+ * @pdc_controller: controller specific information
+ * @probe_ent: For the port address
+ * @pll_clock: The input of PLL in HZ
+ */
+static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsigned int board_idx)
+{
+
+ u8 pll_ctl0, pll_ctl1;
+ long pll_clock_khz = pll_clock / 1000;
+ long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
+ long ratio = pout_required / pll_clock_khz;
+ int F, R;
+
+
+ /* Sanity check */
+ if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
+ printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
+ return;
+ }
+
+#ifdef PDC_DEBUG
+ PDPRINTK("pout_required is %ld\n", pout_required);
+
+ /* Show the current clock value of PLL control register
+ * (maybe already configured by the firmware)
+ */
+ outb(0x02, probe_ent->port[1].bmdma_addr + 0x01);
+ pll_ctl0 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+ outb(0x03, probe_ent->port[1].bmdma_addr + 0x01);
+ pll_ctl1 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+
+ PDPRINTK("pll_ctl[%X][%X]\n", pll_ctl0, pll_ctl1);
+#endif
+
+ /*
+ * Calculate the ratio of F, R and OD
+ * POUT = (F + 2) / (( R + 2) * NO)
+ */
+ if (ratio < 8600L) { // 8.6x
+ /* Using NO = 0x01, R = 0x0D */
+ R = 0x0d;
+ } else if (ratio < 12900L) { // 12.9x
+ /* Using NO = 0x01, R = 0x08 */
+ R = 0x08;
+ } else if (ratio < 16100L) { // 16.1x
+ /* Using NO = 0x01, R = 0x06 */
+ R = 0x06;
+ } else if (ratio < 64000L) { // 64x
+ R = 0x00;
+ } else {
+ /* Invalid ratio */
+ printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
+ return;
+ }
+
+ F = (ratio * (R+2)) / 1000 - 2;
+
+ if (unlikely(F < 0 || F > 127)) {
+ /* Invalid F */
+ printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
+ return;
+ }
+
+ PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
+
+ pll_ctl0 = (u8) F;
+ pll_ctl1 = (u8) R;
+
+ PDPRINTK("Writing pll_ctl[%X][%X]\n", pll_ctl0, pll_ctl1);
+
+ outb(0x02, probe_ent->port[1].bmdma_addr + 0x01);
+ outb(pll_ctl0, probe_ent->port[1].bmdma_addr + 0x03);
+ outb(0x03, probe_ent->port[1].bmdma_addr + 0x01);
+ outb(pll_ctl1, probe_ent->port[1].bmdma_addr + 0x03);
+
+ /* Wait the PLL circuit to be stable */
+ mdelay(30);
+
+#ifdef PDC_DEBUG
+ /*
+ * Show the current clock value of PLL control register
+ * (maybe configured by the firmware)
+ */
+ outb(0x02, probe_ent->port[1].bmdma_addr + 0x01);
+ pll_ctl0 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+ outb(0x03, probe_ent->port[1].bmdma_addr + 0x01);
+ pll_ctl1 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+
+ PDPRINTK("pll_ctl[%X][%X]\n", pll_ctl0, pll_ctl1);
+#endif
+
+ return;
+}
+/**
+ * detect_pll_input_clock - Detect the PLL input clock in Hz.
+ * @probe_ent: for the port address
+ * Ex. 16949000 on 33MHz PCI bus for pdc20275.
+ * Half of the PCI clock.
+ */
+static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent)
+{
+ u8 scr1;
+ unsigned long ctr0;
+ unsigned long ctr1;
+ unsigned long ctr2 = 0;
+ unsigned long ctr3 = 0;
+
+ unsigned long start_count, end_count;
+ long pll_clock;
+
+ /* Read current counter value */
+ outb(0x20, probe_ent->port[0].bmdma_addr + 0x01);
+ ctr0 = inb(probe_ent->port[0].bmdma_addr + 0x03);
+ outb(0x21, probe_ent->port[0].bmdma_addr + 0x01);
+ ctr1 = inb(probe_ent->port[0].bmdma_addr + 0x03);
+
+ outb(0x20, probe_ent->port[1].bmdma_addr + 0x01);
+ ctr2 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+ outb(0x21, probe_ent->port[1].bmdma_addr + 0x01);
+ ctr3 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+
+ start_count = (ctr3 << 23 ) | (ctr2 << 15) | (ctr1 << 8) | ctr0;
+
+ PDPRINTK("ctr0[%lX] ctr1[%lX] ctr2 [%lX] ctr3 [%lX]\n", ctr0, ctr1, ctr2, ctr3);
+
+ /* Start the test mode */
+ outb(0x01, probe_ent->port[0].bmdma_addr + 0x01);
+ scr1 = inb(probe_ent->port[0].bmdma_addr + 0x03);
+ PDPRINTK("scr1[%X]\n", scr1);
+ outb(scr1 | 0x40, probe_ent->port[0].bmdma_addr + 0x03);
+
+ /* Let the counter run for 1000 us. */
+ udelay(1000);
+
+ /* Read the counter values again */
+ outb(0x20, probe_ent->port[0].bmdma_addr + 0x01);
+ ctr0 = inb(probe_ent->port[0].bmdma_addr + 0x03);
+ outb(0x21, probe_ent->port[0].bmdma_addr + 0x01);
+ ctr1 = inb(probe_ent->port[0].bmdma_addr + 0x03);
+
+ outb(0x20, probe_ent->port[1].bmdma_addr + 0x01);
+ ctr2 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+ outb(0x21, probe_ent->port[1].bmdma_addr + 0x01);
+ ctr3 = inb(probe_ent->port[1].bmdma_addr + 0x03);
+
+ end_count = (ctr3 << 23 ) | (ctr2 << 15) | (ctr1 << 8) | ctr0;
+
+ PDPRINTK("ctr0[%lX] ctr1[%lX] ctr2 [%lX] ctr3 [%lX]\n", ctr0, ctr1, ctr2, ctr3);
+
+ /* Stop the test mode */
+ outb(0x01, probe_ent->port[0].bmdma_addr + 0x01);
+ scr1 = inb(probe_ent->port[0].bmdma_addr + 0x03);
+ PDPRINTK("scr1[%X]\n", scr1);
+ outb(scr1 & 0xBF, probe_ent->port[0].bmdma_addr + 0x03);
+
+ /* calculate the input clock in Hz */
+ pll_clock = (long) ((start_count - end_count) * 1000);
+
+ PDPRINTK("start[%lu] end[%lu] \n", start_count, end_count);
+ PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
+
+ return pll_clock;
+}
+/**
+ * pdc_hardware_init - Initialize the hardware.
+ * @pdev: instance of pci_dev found
+ * @pdc_controller: controller specific information
+ * @pe: for the port address
+ */
+static int pdc_hardware_init(struct pci_dev *pdev, struct ata_probe_ent *pe, unsigned int board_idx)
+{
+ long pll_clock;
+
+ /*
+ * Detect PLL input clock rate.
+ * On some system, where PCI bus is running at non-standard clock rate.
+ * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
+ * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
+ */
+ pll_clock = pdc_detect_pll_input_clock(pe);
+
+ if(pll_clock < 0) /* counter overflow? Try again. */
+ pll_clock = pdc_detect_pll_input_clock(pe);
+
+ printk(KERN_INFO DRV_NAME ": PLL input clock %ld kHz\n", pll_clock/1000);
+
+ /* Adjust PLL control register */
+ pdc_adjust_pll(pe, pll_clock, board_idx);
+
+ return 0;
+}
+/**
+ * pdc2027x_init_one - PCI probe function
+ * Called when an instance of PCI adapter is inserted.
+ * This function checks whether the hardware is supported,
+ * initialize hardware and register an instance of ata_host_set to
+ * libata by providing struct ata_probe_ent and ata_device_add().
+ * (implements struct pci_driver.probe() )
+ *
+ * @pdev: instance of pci_dev found
+ * @ent: matching entry in the id_tbl[]
+ */
+static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ static int printed_version;
+ unsigned int board_idx = (unsigned int) ent->driver_data;
+
+ struct ata_probe_ent *probe_ent = NULL;
+ int rc;
+
+ if (!printed_version++)
+ printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
+
+ rc = pci_enable_device(pdev);
+ if (rc)
+ return rc;
+
+ rc = pci_request_regions(pdev, DRV_NAME);
+ if (rc)
+ goto err_out;
+
+ rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
+ if (rc)
+ goto err_out_regions;
+
+ rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
+ if (rc)
+ goto err_out_regions;
+
+ /* Prepare the probe entry */
+ probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
+ if (probe_ent == NULL) {
+ rc = -ENOMEM;
+ goto err_out_regions;
+ }
+
+ memset(probe_ent, 0, sizeof(*probe_ent));
+ probe_ent->dev = pci_dev_to_dev(pdev);
+ INIT_LIST_HEAD(&probe_ent->node);
+
+ probe_ent->sht = pdc2027x_port_info[board_idx].sht;
+ probe_ent->host_flags = pdc2027x_port_info[board_idx].host_flags;
+ probe_ent->pio_mask = pdc2027x_port_info[board_idx].pio_mask;
+ probe_ent->udma_mask = pdc2027x_port_info[board_idx].udma_mask;
+ probe_ent->port_ops = pdc2027x_port_info[board_idx].port_ops;
+
+ probe_ent->irq = pdev->irq;
+ probe_ent->irq_flags = SA_SHIRQ;
+
+ probe_ent->port[0].cmd_addr = pci_resource_start(pdev, 0);
+ ata_std_ports(&probe_ent->port[0]);
+ probe_ent->port[0].altstatus_addr =
+ probe_ent->port[0].ctl_addr =
+ pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS;
+ probe_ent->port[0].bmdma_addr = pci_resource_start(pdev, 4);
+
+ probe_ent->port[1].cmd_addr = pci_resource_start(pdev, 2);
+ ata_std_ports(&probe_ent->port[1]);
+ probe_ent->port[1].altstatus_addr =
+ probe_ent->port[1].ctl_addr =
+ pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS;
+ probe_ent->port[1].bmdma_addr = pci_resource_start(pdev, 4) + 8;
+
+ probe_ent->n_ports = 2;
+
+ pci_set_master(pdev);
+ //pci_enable_intx(pdev);
+
+ /* initialize adapter */
+ if(pdc_hardware_init(pdev, probe_ent, board_idx) != 0)
+ goto err_out_free_ent;
+
+ ata_device_add(probe_ent);
+ kfree(probe_ent);
+
+ return 0;
+
+err_out_free_ent:
+ kfree(probe_ent);
+err_out_regions:
+ pci_release_regions(pdev);
+err_out:
+ pci_disable_device(pdev);
+ return rc;
+}
+/**
+ * pdc2027x_remove_one - Called to remove a single instance of the
+ * adapter.
+ *
+ * @dev: The PCI device to remove.
+ * FIXME: module load/unload not working yet
+ */
+static void __devexit pdc2027x_remove_one(struct pci_dev *pdev)
+{
+ ata_pci_remove_one(pdev);
+}
+/**
+ * pdc2027x_init - Called after this module is loaded into the kernel.
+ */
+static int __init pdc2027x_init(void)
+{
+ return pci_module_init(&pdc2027x_pci_driver);
+}
+/**
+ * pdc2027x_exit - Called before this module unloaded from the kernel
+ */
+static void __exit pdc2027x_exit(void)
+{
+ pci_unregister_driver(&pdc2027x_pci_driver);
+}
+
+module_init(pdc2027x_init);
+module_exit(pdc2027x_exit);
diff -Nru linux-2.6.10/include/linux/libata.h linux-2.6.10-mod/include/linux/libata.h
--- linux-2.6.10/include/linux/libata.h 2004-12-25 05:33:49.000000000 +0800
+++ linux-2.6.10-mod/include/linux/libata.h 2005-02-22 15:12:43.000000000 +0800
@@ -37,8 +37,8 @@
#undef ATA_VERBOSE_DEBUG /* yet more debugging output */
#undef ATA_IRQ_TRAP /* define to ack screaming irqs */
#undef ATA_NDEBUG /* define to disable quick runtime checks */
-#undef ATA_ENABLE_ATAPI /* define to enable ATAPI support */
-#undef ATA_ENABLE_PATA /* define to enable PATA support in some
+#define ATA_ENABLE_ATAPI /* define to enable ATAPI support */
+#define ATA_ENABLE_PATA /* define to enable PATA support in some
* low-level drivers */
#undef ATAPI_ENABLE_DMADIR /* enables ATAPI DMADIR bridge support */
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: PDC20269: Limit on number of controllers?
@ 2005-02-25 17:06 Winstel, Drew
0 siblings, 0 replies; 7+ messages in thread
From: Winstel, Drew @ 2005-02-25 17:06 UTC (permalink / raw)
To: Albert Lee; +Cc: IDE Linux
> The 2.6.11-rc4 needs .bmdma_stop and .bmdma_status to be defined.
>Attached please find the debug patch with the needed hooks. Thanks.
The patch did not apply cleanly (only the actual pata_promise driver
would patch) against 2.6.10, so I hand-patched both 2.6.10 and
2.6.11-rc4-bk9, and both drivers appear to work quite well.
ATAPI appears to be working in rc4 with my SONY DDU-1621 DVD-ROM drive
and a SUSE 9.2 DVD.
Is there anything you would like me to test? I currently have 6 hard
drives, the aforementioned DVD, and a SATA drive hooked up to the on-
board Silicon Image 3512.
Thanks,
Drew
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2005-02-25 17:06 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2005-02-23 20:58 PDC20269: Limit on number of controllers? Winstel, Drew
2005-02-24 5:35 ` Albert Lee
-- strict thread matches above, loose matches on Subject: below --
2005-02-25 17:06 Winstel, Drew
2005-02-22 20:29 Winstel, Drew
2005-02-23 7:09 ` Albert Lee
2005-02-21 22:32 Winstel, Drew
2005-02-22 7:28 ` Albert Lee
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