[PATCH 2.6.11.5 ] sata_sil: Fix FIFO PCI Bus Arbitration

[PATCH 2.6.11.5 ] sata_sil: Fix FIFO PCI Bus Arbitration

[Carlos Pardo]

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This patch set default values for the FIFO PCI Bus Arbitration to avoid data corruption. The root cause is due to our PCI bus master handling mismatch with the chipset PCI bridge during DMA xfer (write data to the device). The patch is to setup the DMA fifo threshold so that there is no chance for the DMA engine to change protocol. We have seen this problem only on one motherboard.

Signed-off-by: Silicon Image Corporation <cpardo@siliconimage.com>

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--- a/drivers/scsi/sata_sil.c	2005-03-22 15:28:41.000000000 -0800
+++ b/drivers/scsi/sata_sil.c	2005-03-22 15:28:42.000000000 -0800
@@ -38,12 +38,21 @@
 #include <linux/libata.h>
 
 #define DRV_NAME	"sata_sil"
-#define DRV_VERSION	"0.8"
+#define DRV_VERSION	"0.9"
 
 enum {
 	sil_3112		= 0,
 	sil_3114		= 1,
 
+	SIL_FIFO_R0		= 0x40,
+	SIL_FIFO_W0		= 0x41,
+	SIL_FIFO_R1		= 0x44,
+	SIL_FIFO_W1		= 0x45,
+	SIL_FIFO_R2		= 0x240,
+	SIL_FIFO_W2		= 0x241,
+	SIL_FIFO_R3		= 0x244,
+	SIL_FIFO_W3		= 0x245,
+
 	SIL_SYSCFG		= 0x48,
 	SIL_MASK_IDE0_INT	= (1 << 22),
 	SIL_MASK_IDE1_INT	= (1 << 23),
@@ -198,6 +207,13 @@ MODULE_LICENSE("GPL");
 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
 MODULE_VERSION(DRV_VERSION);
 
+static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
+{
+	u8 cache_line;
+	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
+	return cache_line;
+}
+
 static void sil_post_set_mode (struct ata_port *ap)
 {
 	struct ata_host_set *host_set = ap->host_set;
@@ -340,6 +356,7 @@ static int sil_init_one (struct pci_dev 
 	unsigned int i;
 	int pci_dev_busy = 0;
 	u32 tmp, irq_mask;
+	u8 cls;
 
 	if (!printed_version++)
 		printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
@@ -404,6 +421,15 @@ static int sil_init_one (struct pci_dev 
 		ata_std_ports(&probe_ent->port[i]);
 	}
 
+	/* Initialize FIFO PCI bus arbitration */
+	cls=sil_get_device_cache_line(pdev);
+	cls >>= 3;
+	cls++;  /* cls = (line_size/8)+1 */
+	writeb(cls, mmio_base + SIL_FIFO_R0);
+	writeb(cls, mmio_base + SIL_FIFO_W0);
+	writeb(cls, mmio_base + SIL_FIFO_R1);
+	writeb(cls, mmio_base + SIL_FIFO_W2);
+
 	if (ent->driver_data == sil_3114) {
 		irq_mask = SIL_MASK_4PORT;
 

Re: [PATCH 2.6.11.5 ] sata_sil: Fix FIFO PCI Bus Arbitration

[Jeff Garzik]

Carlos Pardo wrote:
> This patch set default values for the FIFO PCI Bus Arbitration to avoid data corruption. The root cause is due to our PCI bus master handling mismatch with the chipset PCI bridge during DMA xfer (write data to the device). The patch is to setup the DMA fifo threshold so that there is no chance for the DMA engine to change protocol. We have seen this problem only on one motherboard.
> 
> Signed-off-by: Silicon Image Corporation <cpardo@siliconimage.com

Thanks, Carlos.

Patch looks good, I'll merge ASAP.

	Jeff

Re: [PATCH 2.6.11.5 ] sata_sil: Fix FIFO PCI Bus Arbitration

[Jeff Garzik]

Carlos Pardo wrote:
> This patch set default values for the FIFO PCI Bus Arbitration to avoid data corruption. The root cause is due to our PCI bus master handling mismatch with the chipset PCI bridge during DMA xfer (write data to the device). The patch is to setup the DMA fifo threshold so that there is no chance for the DMA engine to change protocol. We have seen this problem only on one motherboard.
> 
> Signed-off-by: Silicon Image Corporation <cpardo@siliconimage.com

Patch applied to libata-2.4 and libata-2.6 queues, and will be sent 
upstream ASAP.  Thanks.

One slight problem with your submission:  your mailer encoded the 
plaintext patch using base64 encoding, which makes the patch difficult 
to review.

The preferred method of submitting patches is pasting them inline. 
However many Windows mailers will corrupt the whitespace in the patch, 
or wrap long lines, if you do this.

On Unix, the best way to accomplish this is described at

	http://lkml.org/lkml/2005/2/24/3

On Windows, the free (open source) Mozilla Thunderbird or Mozilla Mail 
applications should correctly attach plaintext patches without encoding 
them.

Regards,

	Jeff

RE: [PATCH 2.6.11.5 ] sata_sil: Fix FIFO PCI Bus Arbitration

[Carlos Pardo]

Thanks to you Jeff.

-----Original Message-----
From: Jeff Garzik [mailto:jgarzik@pobox.com]
Sent: Wednesday, March 23, 2005 11:13 AM
To: Carlos Pardo
Cc: linux-ide@vger.kernel.org
Subject: Re: [PATCH 2.6.11.5 ] sata_sil: Fix FIFO PCI Bus Arbitration


Carlos Pardo wrote:
> This patch set default values for the FIFO PCI Bus Arbitration to avoid data corruption. The root cause is due to our PCI bus master handling mismatch with the chipset PCI bridge during DMA xfer (write data to the device). The patch is to setup the DMA fifo threshold so that there is no chance for the DMA engine to change protocol. We have seen this problem only on one motherboard.
> 
> Signed-off-by: Silicon Image Corporation <cpardo@siliconimage.com

Thanks, Carlos.

Patch looks good, I'll merge ASAP.

	Jeff