--- 01_pdc_mmio/drivers/scsi/pata_pdc2027x.c	2005-08-03 15:43:19.000000000 +0800
+++ 02_pdc_micro/drivers/scsi/pata_pdc2027x.c	2005-08-03 15:44:16.000000000 +0800
@@ -29,7 +29,7 @@
 #include <asm/io.h>
 
 #define DRV_NAME	"pata_pdc2027x"
-#define DRV_VERSION	"0.70"
+#define DRV_VERSION	"0.71"
 #undef PDC_DEBUG
 
 #ifdef PDC_DEBUG
@@ -481,9 +481,9 @@
  * @probe_ent: for the port address
  */
 
-static unsigned long pdc_read_counter(struct ata_probe_ent *probe_ent)
+static long pdc_read_counter(struct ata_probe_ent *probe_ent)
 {
-	unsigned long counter;
+	long counter;
 	int retry = 1;
 	u32 bccrl, bccrh, bccrlv, bccrhv;
 
@@ -612,11 +612,13 @@
 static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent) 
 {
 	u32 scr;
-	unsigned long start_count, end_count;
+	long start_count, end_count, usec_elapsed;
+	struct timeval start_time, end_time;
 	long pll_clock;
 
 	/* Read current counter value */
 	start_count = pdc_read_counter(probe_ent);
+	do_gettimeofday(&start_time);
 
 	/* Start the test mode */
 	scr = readl(probe_ent->mmio_base + PDC_SYS_CTL);
@@ -629,6 +631,7 @@
 
 	/* Read the counter values again */
 	end_count = pdc_read_counter(probe_ent);
+	do_gettimeofday(&end_time);
 
 	/* Stop the test mode */
 	scr = readl(probe_ent->mmio_base + PDC_SYS_CTL);
@@ -637,7 +640,9 @@
 	wmb();
 
 	/* calculate the input clock in Hz */
-	pll_clock = (long) ((start_count - end_count) * 10);
+	usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
+		(end_time.tv_usec - start_time.tv_usec);
+	pll_clock = (start_count - end_count) / 100 * (100000000 / usec_elapsed);
 
 	PDPRINTK("start[%lu] end[%lu] \n", start_count, end_count);
 	PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);