[PATCH] ata_piix: kill spurious assignment in piix_sata_probe()

[PATCH] ata_piix: kill spurious assignment in piix_sata_probe()

[Tejun Heo]

In piix_sata_probe(), mask gets assigned unnecessarily at the
beginning of the function.  Kill the assignment.

Signed-off-by: Tejun Heo <htejun@gmail.com>

---

This patch is against
the current upstream (bef4a456b8dc8b3638f4d49a25a89e1467da9483)
+ http://article.gmane.org/gmane.linux.ide/7967
+ http://article.gmane.org/gmane.linux.ide/7968 (2 patches)

 drivers/scsi/ata_piix.c |    3 ---
 1 file changed, 3 deletions(-)

Index: work1/drivers/scsi/ata_piix.c
===================================================================
--- work1.orig/drivers/scsi/ata_piix.c	2006-02-12 18:48:31.000000000 +0900
+++ work1/drivers/scsi/ata_piix.c	2006-02-12 18:48:31.000000000 +0900
@@ -425,9 +425,6 @@ static int piix_sata_probe (struct ata_p
 	int orig_mask, mask, i;
 	u8 pcs;
 
-	mask = (PIIX_PORT_PRESENT << ap->hard_port_no) |
-	       (PIIX_PORT_ENABLED << ap->hard_port_no);
-
 	pci_read_config_byte(pdev, ICH5_PCS, &pcs);
 	orig_mask = (int) pcs & 0xff;
 

Re: [PATCH] ata_piix: kill spurious assignment in piix_sata_probe()

[Jeff Garzik]

Tejun Heo wrote:
> In piix_sata_probe(), mask gets assigned unnecessarily at the
> beginning of the function.  Kill the assignment.
> 
> Signed-off-by: Tejun Heo <htejun@gmail.com>
> 
> ---
> 
> This patch is against
> the current upstream (bef4a456b8dc8b3638f4d49a25a89e1467da9483)
> + http://article.gmane.org/gmane.linux.ide/7967
> + http://article.gmane.org/gmane.linux.ide/7968 (2 patches)

applied, though this function needs a further look:

1) We should really:

* enable port X via PCS, if not already
* delay a bit, for SATA device detection
* check 'present' bit
* if nothing present, disable port X via PCS


2) In ICH6 and later, according to the docs:  PCS enable bits should 
always be set, and the port should be controlled via SATA phy registers. 
  As I noted in another email, ICH6+ should support SATA PHY registers 
even if AHCI is disabled.  See bit 9 of SIR (94h) register in ICH6 and 
ICH7, which enables access to SATA PHY regs.


I am hoping that we can make all ICH6/7 use SATA PHY registers, but I am 
worried that in some cases the AHCI BAR may not have been assigned a value.

	Jeff