Re: More information on ATI IXP failure in git9

[Tejun Heo <htejun@gmail.com>]

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Tejun Heo wrote:
> Hello, Andi.
> 
> Andi Kleen wrote:
>> Still doesn't work with it - see 
>> http://one.firstfloor.org/~andi/sata3.jpg
> 
> * SATA_IRQ bit is stuck (on all other sil controllers, this gets cleared 
> when SError is cleared)
> 
> * whenever interrupt occurs (from itself or from any other ones sharing 
> the IRQ), irq handler sees SATA_IRQ bit set and thus thinks it just 
> received phy status changed IRQ.
> 
> * phy status change aborts the active command, so no command gets 
> completed.
> 
> I'm attaching two patches.  The first one tries to clear SATA_IRQ by 
> writing 1 to it in thaw() assuming the bit is implemented as W1C (which 
> BTW is out of spec).  The second one kills SATA_IRQ handling completely. 
>  I wish the first one works but if not I'll update the second one such 
> that it applies only to ATI IXP.

And another one, just in case they were crazy enough to implement the 
bit as RW.

-- 
tejun

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diff --git a/drivers/scsi/sata_sil.c b/drivers/scsi/sata_sil.c
index bc9f918..0f19645 100644
--- a/drivers/scsi/sata_sil.c
+++ b/drivers/scsi/sata_sil.c
@@ -474,6 +474,10 @@ static void sil_thaw(struct ata_port *ap
 	ata_chk_status(ap);
 	ata_bmdma_irq_clear(ap);
 
+	/* SATA_IRQ has to be cleared manually on some controllers */
+	writel(SIL_DMA_SATA_IRQ, mmio_base + sil_port[ap->port_no].bmdma2);
+	writel(0, mmio_base + sil_port[ap->port_no].bmdma2);
+
 	/* turn on SATA IRQ */
 	writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);