Kernel fix for ICH7M controller

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* Kernel fix for ICH7M controller
@ 2006-09-03 14:26 Jonathan Dieter
  2006-09-04  2:47 ` Tejun Heo
  0 siblings, 1 reply; 9+ messages in thread
From: Jonathan Dieter @ 2006-09-03 14:26 UTC (permalink / raw)
  To: jeff, linux-ide; +Cc: fedora-devel-list

[-- Attachment #1: Type: text/plain, Size: 991 bytes --]

The ata_piix module doesn't detect that my laptop's disk controller 
(Intel Corporation 82801GBM/GHM - ICH7 Family) is configured to have 
PATA drives in the first two channels.  I looked at Intel's 
documentation and they say that my controller isn't supposed to support 
this configuration, but it's the default setup on this laptop, there's 
no way to change it in the BIOS, and it works in Windows, so I'm 
assuming this is a documentation error.

This patch changes one line in ata_piix.c so that it sees this 
configuration as valid (and therefore recognizes my drives).  I've 
tested it on my laptop and the module is now working perfectly (whereas 
the kernel was using the old IDE driver previously with no DMA enabled).

I'm cc'ing fedora-devel-list because I'm not even sure where this patch 
is supposed to go and I would like it to make it into FC6, as I really 
don't want to have to jump through hoop after hoop just to get FC6 
installed on my hard drive.

Thanks,
Jonathan

[-- Attachment #2: linux-2.6-fix-ich7m-with-pata-on-channel-one.patch --]
[-- Type: text/x-patch, Size: 577 bytes --]

--- linux-2.6.17/drivers/scsi/ata_piix.c	2006-09-03 16:37:16.000000000 +0300
+++ linux-2.6.17-new/drivers/scsi/ata_piix.c	2006-09-03 16:39:14.000000000 +0300
@@ -326,15 +326,15 @@
 static const struct piix_map_db ich6m_map_db = {
 	.mask = 0x3,
 	.port_enable = 0x5,
 	.present_shift = 4,
 	.map = {
 		/* PM   PS   SM   SS       MAP */
 		{  P0,  P2,  RV,  RV }, /* 00b */
-		{  RV,  RV,  RV,  RV },
+		{ IDE, IDE,  P1,  P3 }, /* 01b */
 		{  P0,  P2, IDE, IDE }, /* 10b */
 		{  RV,  RV,  RV,  RV },
 	},
 };

 static const struct piix_map_db ich8_map_db = {
 	.mask = 0x3,

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: Kernel fix for ICH7M controller
  2006-09-03 14:26 Kernel fix for ICH7M controller Jonathan Dieter
@ 2006-09-04  2:47 ` Tejun Heo
  2006-09-04  5:45   ` Jeff Garzik
  2006-09-04  6:53   ` Jonathan Dieter
  0 siblings, 2 replies; 9+ messages in thread
From: Tejun Heo @ 2006-09-04  2:47 UTC (permalink / raw)
  To: Jonathan Dieter; +Cc: jeff, linux-ide, fedora-devel-list

Jonathan Dieter wrote:
> The ata_piix module doesn't detect that my laptop's disk controller 
> (Intel Corporation 82801GBM/GHM - ICH7 Family) is configured to have 
> PATA drives in the first two channels.  I looked at Intel's 
> documentation and they say that my controller isn't supposed to support 
> this configuration, but it's the default setup on this laptop, there's 
> no way to change it in the BIOS, and it works in Windows, so I'm 
> assuming this is a documentation error.
> 
> This patch changes one line in ata_piix.c so that it sees this 
> configuration as valid (and therefore recognizes my drives).  I've 
> tested it on my laptop and the module is now working perfectly (whereas 
> the kernel was using the old IDE driver previously with no DMA enabled).

Hello,

Interesting.  Can you post the result of 'lspci -n -vvv -xxx'?  I don't 
see why this support shouldn't go into mainline but wanna see if 
narrowing down the effect a bit (if PCI ID allows us to) would be a good 
idea.

Thanks.

-- 
tejun

-- 
VGER BF report: H 3.87351e-06

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: Kernel fix for ICH7M controller
  2006-09-04  2:47 ` Tejun Heo
@ 2006-09-04  5:45   ` Jeff Garzik
  2006-09-04  7:34     ` Tejun Heo
  2006-09-04  6:53   ` Jonathan Dieter
  1 sibling, 1 reply; 9+ messages in thread
From: Jeff Garzik @ 2006-09-04  5:45 UTC (permalink / raw)
  To: Tejun Heo; +Cc: Jonathan Dieter, linux-ide, fedora-devel-list

Tejun Heo wrote:
> Jonathan Dieter wrote:
>> The ata_piix module doesn't detect that my laptop's disk controller 
>> (Intel Corporation 82801GBM/GHM - ICH7 Family) is configured to have 
>> PATA drives in the first two channels.  I looked at Intel's 
>> documentation and they say that my controller isn't supposed to 
>> support this configuration, but it's the default setup on this laptop, 
>> there's no way to change it in the BIOS, and it works in Windows, so 
>> I'm assuming this is a documentation error.
>>
>> This patch changes one line in ata_piix.c so that it sees this 
>> configuration as valid (and therefore recognizes my drives).  I've 
>> tested it on my laptop and the module is now working perfectly 
>> (whereas the kernel was using the old IDE driver previously with no 
>> DMA enabled).
> 
> Hello,
> 
> Interesting.  Can you post the result of 'lspci -n -vvv -xxx'?  I don't 
> see why this support shouldn't go into mainline but wanna see if 
> narrowing down the effect a bit (if PCI ID allows us to) would be a good 
> idea.

FWIW several PCI devices use the ich6m info entry.  We may want to split 
out ICH7M rather than assume other chips behave similarly.

	Jeff




-- 
VGER BF report: H 0

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: Kernel fix for ICH7M controller
  2006-09-04  5:45   ` Jeff Garzik
@ 2006-09-04  7:34     ` Tejun Heo
  0 siblings, 0 replies; 9+ messages in thread
From: Tejun Heo @ 2006-09-04  7:34 UTC (permalink / raw)
  To: Jeff Garzik; +Cc: Jonathan Dieter, linux-ide, fedora-devel-list

Jeff Garzik wrote:
> Tejun Heo wrote:
>> Jonathan Dieter wrote:
>>> The ata_piix module doesn't detect that my laptop's disk controller 
>>> (Intel Corporation 82801GBM/GHM - ICH7 Family) is configured to have 
>>> PATA drives in the first two channels.  I looked at Intel's 
>>> documentation and they say that my controller isn't supposed to 
>>> support this configuration, but it's the default setup on this 
>>> laptop, there's no way to change it in the BIOS, and it works in 
>>> Windows, so I'm assuming this is a documentation error.
>>>
>>> This patch changes one line in ata_piix.c so that it sees this 
>>> configuration as valid (and therefore recognizes my drives).  I've 
>>> tested it on my laptop and the module is now working perfectly 
>>> (whereas the kernel was using the old IDE driver previously with no 
>>> DMA enabled).
>>
>> Hello,
>>
>> Interesting.  Can you post the result of 'lspci -n -vvv -xxx'?  I 
>> don't see why this support shouldn't go into mainline but wanna see if 
>> narrowing down the effect a bit (if PCI ID allows us to) would be a 
>> good idea.
> 
> FWIW several PCI devices use the ich6m info entry.  We may want to split 
> out ICH7M rather than assume other chips behave similarly.

Hello, Jeff.

The controller is reporting subsystem id 1025(Acer):0107.  Either we can 
enable that entry for all ICH7Ms or only for the Acer.  I'm more 
inclined to the former.  What do you think?

Thanks.

-- 
tejun

-- 
VGER BF report: H 6.45778e-11

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: Kernel fix for ICH7M controller
  2006-09-04  2:47 ` Tejun Heo
  2006-09-04  5:45   ` Jeff Garzik
@ 2006-09-04  6:53   ` Jonathan Dieter
  2006-09-04  8:15     ` Tejun Heo
  1 sibling, 1 reply; 9+ messages in thread
From: Jonathan Dieter @ 2006-09-04  6:53 UTC (permalink / raw)
  To: Tejun Heo, Jeff Garzik; +Cc: linux-ide, fedora-devel-list

[-- Attachment #1: Type: text/plain, Size: 1222 bytes --]

Tejun Heo wrote:
> Jonathan Dieter wrote:
>> The ata_piix module doesn't detect that my laptop's disk controller 
>> (Intel Corporation 82801GBM/GHM - ICH7 Family) is configured to have 
>> PATA drives in the first two channels.  I looked at Intel's 
>> documentation and they say that my controller isn't supposed to 
>> support this configuration, but it's the default setup on this 
>> laptop, there's no way to change it in the BIOS, and it works in 
>> Windows, so I'm assuming this is a documentation error.
>>
>> This patch changes one line in ata_piix.c so that it sees this 
>> configuration as valid (and therefore recognizes my drives).  I've 
>> tested it on my laptop and the module is now working perfectly 
>> (whereas the kernel was using the old IDE driver previously with no 
>> DMA enabled).
>
> Hello,
>
> Interesting.  Can you post the result of 'lspci -n -vvv -xxx'?  I 
> don't see why this support shouldn't go into mainline but wanna see if 
> narrowing down the effect a bit (if PCI ID allows us to) would be a 
> good idea.
>
> Thanks.
>

Here's the lspci -n -xxx -vvv output.  I've attached the whole output, 
though my disk controller card is at 00:1f.2.

Thanks for looking at this,
Jonathan

[-- Attachment #2: lspci.out --]
[-- Type: text/plain, Size: 38723 bytes --]

00:00.0 0600: 8086:27a0 (rev 03)
	Subsystem: 1025:0107
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
	Latency: 0
	Capabilities: [e0] Vendor Specific Information
00: 86 80 a0 27 06 01 90 20 03 00 00 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
40: 01 90 d1 fe 01 40 d1 fe 01 00 00 e0 01 80 d1 fe
50: 00 00 02 00 03 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 10 11 11 00 10 13 11 01 ff 03 00 00 80 1a 39 00
a0: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 60 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 04 01 01 00
e0: 09 00 09 51 4a 00 4a b0 0e 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 03 00 10 00 00 00

00:01.0 0604: 8086:27a1 (rev 03)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0, Cache Line Size 10
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
	I/O behind bridge: 0000f000-00000fff
	Memory behind bridge: d0000000-d1ffffff
	Prefetchable memory behind bridge: 00000000b0000000-00000000bff00000
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B-
	Capabilities: [88] #0d [0000]
	Capabilities: [80] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [90] Message Signalled Interrupts: 64bit- Queue=0/0 Enable+
		Address: fee00000  Data: 40d9
	Capabilities: [a0] Express Root Port (Slot+) IRQ 0
		Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag-
		Device: Latency L0s <64ns, L1 <1us
		Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported-
		Device: RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
		Device: MaxPayload 128 bytes, MaxReadReq 128 bytes
		Link: Supported Speed 2.5Gb/s, Width x16, ASPM L0s L1, Port 2
		Link: Latency L0s <256ns, L1 <4us
		Link: ASPM L1 Enabled RCB 64 bytes CommClk+ ExtSynch-
		Link: Speed 2.5Gb/s, Width x16
		Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug- Surpise-
		Slot: Number 1, PowerLimit 75.000000
		Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq-
		Slot: AttnInd Off, PwrInd On, Power-
		Root: Correctable- Non-Fatal- Fatal- PME-
	Capabilities: [100] Virtual Channel
	Capabilities: [140] Unknown (5)
00: 86 80 a1 27 07 05 10 00 03 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 f0 00 00 20
20: 00 d0 f0 d1 01 b0 f1 bf 00 00 00 00 00 00 00 00
30: 00 00 00 00 88 00 00 00 00 00 00 00 0b 01 18 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02
80: 01 90 02 c8 00 00 00 00 0d 80 00 00 25 10 07 01
90: 05 a0 01 00 00 00 e0 fe d9 40 00 00 00 00 00 00
a0: 10 00 41 01 00 00 00 00 00 00 00 00 01 2d 01 02
b0: 42 00 01 11 80 25 08 00 c0 01 48 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 01 0f 00 00 00 00 86 0f 03 00 00 00 00 80

00:1b.0 0403: 8086:27d8 (rev 02)
	Subsystem: 1025:0107
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0, Cache Line Size 10
	Interrupt: pin A routed to IRQ 201
	Region 0: Memory at d2300000 (64-bit, non-prefetchable) [size=16K]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [60] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable-
		Address: 0000000000000000  Data: 0000
	Capabilities: [70] Express Unknown type IRQ 0
		Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag-
		Device: Latency L0s <64ns, L1 <1us
		Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported-
		Device: RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
		Device: MaxPayload 128 bytes, MaxReadReq 128 bytes
		Link: Supported Speed unknown, Width x0, ASPM unknown, Port 0
		Link: Latency L0s <64ns, L1 <1us
		Link: ASPM Disabled CommClk- ExtSynch-
		Link: Speed unknown, Width x0
	Capabilities: [100] Virtual Channel
	Capabilities: [130] Unknown (5)
00: 86 80 d8 27 06 01 10 00 02 00 03 04 10 00 00 00
10: 04 00 30 d2 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 00 00
40: 03 00 00 03 00 00 00 00 00 00 00 00 00 80 00 00
50: 01 60 42 c8 00 00 00 00 00 00 00 00 00 00 00 00
60: 05 70 80 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 10 00 91 00 00 00 00 00 00 08 10 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1c.0 0604: 8086:27d0 (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0, Cache Line Size 10
	Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
	I/O behind bridge: 00002000-00002fff
	Memory behind bridge: c8000000-c9ffffff
	Prefetchable memory behind bridge: 00000000c0000000-00000000c1f00000
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
	Capabilities: [40] Express Root Port (Slot+) IRQ 0
		Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag-
		Device: Latency L0s unlimited, L1 unlimited
		Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported-
		Device: RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
		Device: MaxPayload 128 bytes, MaxReadReq 128 bytes
		Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 1
		Link: Latency L0s <256ns, L1 <4us
		Link: ASPM L1 Enabled RCB 64 bytes CommClk+ ExtSynch-
		Link: Speed 2.5Gb/s, Width x1
		Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug+ Surpise+
		Slot: Number 2, PowerLimit 6.500000
		Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq-
		Slot: AttnInd Unknown, PwrInd Unknown, Power-
		Root: Correctable- Non-Fatal- Fatal- PME-
	Capabilities: [80] Message Signalled Interrupts: 64bit- Queue=0/0 Enable+
		Address: fee00000  Data: 40e1
	Capabilities: [90] #0d [0000]
	Capabilities: [a0] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [100] Virtual Channel
	Capabilities: [180] Unknown (5)
00: 86 80 d0 27 07 05 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 02 02 00 20 20 00 00
20: 00 c8 f0 c9 01 c0 f1 c1 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 04 00
40: 10 80 41 01 c0 0f 00 00 00 00 10 00 11 2c 11 01
50: 42 00 11 30 e0 a0 10 00 08 00 40 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 01 00 00 00 e0 fe e1 40 00 00 00 00 00 00
90: 0d a0 00 00 25 10 07 01 00 00 00 00 00 00 00 00
a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 80 00 11 c0 00 00 00 00
e0: 00 0f c7 00 06 07 08 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1c.1 0604: 8086:27d2 (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0, Cache Line Size 10
	Bus: primary=00, secondary=03, subordinate=04, sec-latency=0
	I/O behind bridge: 00003000-00003fff
	Memory behind bridge: ca000000-cbffffff
	Prefetchable memory behind bridge: 00000000c2000000-00000000c3f00000
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
	Capabilities: [40] Express Root Port (Slot+) IRQ 0
		Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag-
		Device: Latency L0s unlimited, L1 unlimited
		Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported-
		Device: RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
		Device: MaxPayload 128 bytes, MaxReadReq 128 bytes
		Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 2
		Link: Latency L0s <1us, L1 <4us
		Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch-
		Link: Speed 2.5Gb/s, Width x1
		Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug+ Surpise+
		Slot: Number 3, PowerLimit 6.500000
		Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq-
		Slot: AttnInd Unknown, PwrInd Unknown, Power-
		Root: Correctable- Non-Fatal- Fatal- PME-
	Capabilities: [80] Message Signalled Interrupts: 64bit- Queue=0/0 Enable+
		Address: fee00000  Data: 40e9
	Capabilities: [90] #0d [0000]
	Capabilities: [a0] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [100] Virtual Channel
	Capabilities: [180] Unknown (5)
00: 86 80 d2 27 07 05 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 03 04 00 30 30 00 00
20: 00 ca f0 cb 01 c2 f1 c3 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 02 04 00
40: 10 80 41 01 c0 0f 00 00 00 00 10 00 11 4c 11 02
50: 00 00 01 10 e0 a0 18 00 08 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 01 00 00 00 e0 fe e9 40 00 00 00 00 00 00
90: 0d a0 00 00 25 10 07 01 00 00 00 00 00 00 00 00
a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 80 00 11 c0 00 00 00 00
e0: 00 0f c7 00 06 07 08 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1c.2 0604: 8086:27d4 (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0, Cache Line Size 10
	Bus: primary=00, secondary=05, subordinate=06, sec-latency=0
	I/O behind bridge: 00004000-00004fff
	Memory behind bridge: cc000000-cdffffff
	Prefetchable memory behind bridge: 00000000c4000000-00000000c5f00000
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
	Capabilities: [40] Express Root Port (Slot+) IRQ 0
		Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag-
		Device: Latency L0s unlimited, L1 unlimited
		Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported-
		Device: RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
		Device: MaxPayload 128 bytes, MaxReadReq 128 bytes
		Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 3
		Link: Latency L0s <256ns, L1 <4us
		Link: ASPM L1 Enabled RCB 64 bytes CommClk+ ExtSynch-
		Link: Speed 2.5Gb/s, Width x1
		Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug+ Surpise+
		Slot: Number 4, PowerLimit 6.500000
		Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq-
		Slot: AttnInd Unknown, PwrInd Unknown, Power-
		Root: Correctable- Non-Fatal- Fatal- PME-
	Capabilities: [80] Message Signalled Interrupts: 64bit- Queue=0/0 Enable+
		Address: fee00000  Data: 4032
	Capabilities: [90] #0d [0000]
	Capabilities: [a0] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [100] Virtual Channel
	Capabilities: [180] Unknown (5)
00: 86 80 d4 27 07 05 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 05 06 00 40 40 00 00
20: 00 cc f0 cd 01 c4 f1 c5 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 03 04 00
40: 10 80 41 01 c0 0f 00 00 00 00 11 00 11 2c 11 03
50: 42 00 11 30 e0 a0 20 00 08 00 40 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 01 00 00 00 e0 fe 32 40 00 00 00 00 00 00
90: 0d a0 00 00 25 10 07 01 00 00 00 00 00 00 00 00
a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 80 00 11 c0 00 00 00 00
e0: 00 0f c7 80 06 07 08 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1c.3 0604: 8086:27d6 (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0, Cache Line Size 10
	Bus: primary=00, secondary=07, subordinate=08, sec-latency=0
	I/O behind bridge: 00005000-00005fff
	Memory behind bridge: ce000000-cfffffff
	Prefetchable memory behind bridge: 00000000c6000000-00000000c7f00000
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
	Capabilities: [40] Express Root Port (Slot+) IRQ 0
		Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag-
		Device: Latency L0s unlimited, L1 unlimited
		Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported-
		Device: RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
		Device: MaxPayload 128 bytes, MaxReadReq 128 bytes
		Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 4
		Link: Latency L0s <1us, L1 <4us
		Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch-
		Link: Speed 2.5Gb/s, Width x1
		Slot: AtnBtn- PwrCtrl- MRL- AtnInd- PwrInd- HotPlug+ Surpise+
		Slot: Number 5, PowerLimit 6.500000
		Slot: Enabled AtnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq-
		Slot: AttnInd Unknown, PwrInd Unknown, Power-
		Root: Correctable- Non-Fatal- Fatal- PME-
	Capabilities: [80] Message Signalled Interrupts: 64bit- Queue=0/0 Enable+
		Address: fee00000  Data: 403a
	Capabilities: [90] #0d [0000]
	Capabilities: [a0] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [100] Virtual Channel
	Capabilities: [180] Unknown (5)
00: 86 80 d6 27 07 05 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 07 08 00 50 50 00 00
20: 00 ce f0 cf 01 c6 f1 c7 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 04 04 00
40: 10 80 41 01 c0 0f 00 00 00 00 10 00 11 4c 11 04
50: 00 00 01 10 e0 a0 28 00 08 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 01 00 00 00 e0 fe 3a 40 00 00 00 00 00 00
90: 0d a0 00 00 25 10 07 01 00 00 00 00 00 00 00 00
a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 80 00 11 c0 00 00 00 00
e0: 00 0f c7 00 06 07 08 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1d.0 0c03: 8086:27c8 (rev 02)
	Subsystem: 1025:0107
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Interrupt: pin A routed to IRQ 66
	Region 4: I/O ports at 1800 [size=32]
00: 86 80 c8 27 05 00 80 02 02 00 03 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 18 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 27 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1d.1 0c03: 8086:27c9 (rev 02)
	Subsystem: 1025:0107
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Interrupt: pin B routed to IRQ 193
	Region 4: I/O ports at 1820 [size=32]
00: 86 80 c9 27 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 21 18 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 27 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1d.2 0c03: 8086:27ca (rev 02)
	Subsystem: 1025:0107
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Interrupt: pin C routed to IRQ 185
	Region 4: I/O ports at 1840 [size=32]
00: 86 80 ca 27 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 41 18 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 03 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 27 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1d.3 0c03: 8086:27cb (rev 02)
	Subsystem: 1025:0107
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Interrupt: pin D routed to IRQ 169
	Region 4: I/O ports at 1860 [size=32]
00: 86 80 cb 27 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 61 18 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 04 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 27 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1d.7 0c03: 8086:27cc (rev 02) (prog-if 20)
	Subsystem: 1025:0107
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Interrupt: pin A routed to IRQ 66
	Region 0: Memory at d2304000 (32-bit, non-prefetchable) [size=1K]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [58] Debug port
00: 86 80 cc 27 06 01 90 02 02 20 03 0c 00 00 00 00
10: 00 40 30 d2 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 58 c2 c9 00 00 00 00 0a 00 a0 20 00 00 00 00
60: 20 20 ff 01 00 00 00 00 01 00 00 01 00 00 08 80
70: 00 00 d7 3f 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 11 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 aa ff 00 ff 00 ff 00 20 00 00 88
e0: 00 00 00 00 db b6 6d 00 00 00 00 00 00 00 00 00
f0: 00 80 00 09 88 85 40 00 86 0f 02 00 06 17 02 20

00:1e.0 0604: 8086:2448 (rev e2) (prog-if 01)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Bus: primary=00, secondary=0a, subordinate=0e, sec-latency=56
	I/O behind bridge: 00006000-00006fff
	Memory behind bridge: d2000000-d20fffff
	Prefetchable memory behind bridge: 0000000088000000-0000000089f00000
	Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
	Capabilities: [50] #0d [0000]
00: 86 80 48 24 07 01 10 00 e2 01 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 0a 0e 38 60 60 80 22
20: 00 d2 00 d2 01 88 f1 89 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 04 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00
50: 0d 00 00 00 25 10 07 01 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1f.0 0601: 8086:27b9 (rev 02)
	Subsystem: 1025:0107
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Capabilities: [e0] Vendor Specific Information
00: 86 80 b9 27 07 01 10 02 02 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
40: 01 10 00 00 80 00 00 00 81 11 00 00 10 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 80 80 80 80 90 00 00 00 80 80 80 80 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 00 02 3f 00 00 00 00 01 12 04 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 24 06 00 00 01 00 00 00 13 1c 0a 00 00 03 00 00
b0: 00 00 f0 00 00 00 00 00 00 80 09 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 33 22 11 00 67 45 00 00 cf ff 00 00 00 00 00 00
e0: 09 00 0c 10 b4 02 24 17 00 00 00 00 00 00 00 00
f0: 01 c0 d1 fe 00 00 00 00 86 0f 02 00 00 00 00 00

00:1f.2 0101: 8086:27c4 (rev 02) (prog-if 80)
	Subsystem: 1025:0107
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Interrupt: pin B routed to IRQ 193
	Region 0: I/O ports at <unassigned>
	Region 1: I/O ports at <unassigned>
	Region 2: I/O ports at <unassigned>
	Region 3: I/O ports at <unassigned>
	Region 4: I/O ports at 18b0 [size=16]
	Capabilities: [70] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 86 80 c4 27 05 00 b0 02 02 80 01 01 00 00 00 00
10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00
20: b1 18 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 70 00 00 00 00 00 00 00 ff 02 00 00
40: 77 e3 00 80 0b 00 00 00 03 00 22 00 00 00 00 00
50: 00 00 00 00 33 00 04 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 01 00 02 40 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 01 00 05 00 80 01 00 4a 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

00:1f.3 0c05: 8086:27da (rev 02)
	Subsystem: 1025:0107
	Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Interrupt: pin B routed to IRQ 193
	Region 4: I/O ports at 18c0 [size=32]
00: 86 80 da 27 01 01 80 02 02 00 05 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: c1 18 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00
40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00

01:00.0 0300: 10de:01d7 (rev a1)
	Subsystem: 1025:0107
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Interrupt: pin A routed to IRQ 169
	Region 0: Memory at d1000000 (32-bit, non-prefetchable) [size=16M]
	Region 1: Memory at b0000000 (64-bit, prefetchable) [size=256M]
	Region 3: Memory at d0000000 (64-bit, non-prefetchable) [size=16M]
	Capabilities: [60] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [68] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable-
		Address: 0000000000000000  Data: 0000
	Capabilities: [78] Express Endpoint IRQ 0
		Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag-
		Device: Latency L0s <256ns, L1 <4us
		Device: AtnBtn- AtnInd- PwrInd-
		Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported-
		Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
		Device: MaxPayload 128 bytes, MaxReadReq 512 bytes
		Link: Supported Speed 2.5Gb/s, Width x16, ASPM L0s L1, Port 0
		Link: Latency L0s <256ns, L1 <4us
		Link: ASPM L1 Enabled RCB 128 bytes CommClk+ ExtSynch-
		Link: Speed 2.5Gb/s, Width x16
	Capabilities: [100] Virtual Channel
	Capabilities: [128] Power Budgeting
00: de 10 d7 01 07 01 10 00 a1 00 00 03 00 00 00 00
10: 00 00 00 d1 0c 00 00 b0 00 00 00 00 04 00 00 d0
20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 60 00 00 00 00 00 00 00 0b 01 00 00
40: 25 10 07 01 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 00 00 00 01 00 00 00 ce d6 23 00 00 00 00 00
60: 01 68 02 00 00 00 00 00 05 78 80 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 10 00 01 00 80 04 2c 01
80: 10 28 0a 00 01 2d 01 00 4a 00 01 11 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

02:00.0 0200: 10ec:8168 (rev 01)
	Subsystem: 1025:0107
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR+ <PERR-
	Latency: 0, Cache Line Size 10
	Interrupt: pin A routed to IRQ 11
	Region 0: I/O ports at 2000 [size=256]
	Region 2: Memory at c8000000 (64-bit, non-prefetchable) [size=4K]
	[virtual] Expansion ROM at c0000000 [disabled] [size=128K]
	Capabilities: [40] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [48] Vital Product Data
	Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable-
		Address: 0000000000000000  Data: 0000
	Capabilities: [60] Express Endpoint IRQ 0
		Device: Supported: MaxPayload 1024 bytes, PhantFunc 0, ExtTag+
		Device: Latency L0s <1us, L1 unlimited
		Device: AtnBtn+ AtnInd+ PwrInd+
		Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported-
		Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
		Device: MaxPayload 128 bytes, MaxReadReq 512 bytes
		Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s, Port 0
		Link: Latency L0s unlimited, L1 unlimited
		Link: ASPM Disabled RCB 64 bytes CommClk+ ExtSynch-
		Link: Speed 2.5Gb/s, Width x1
	Capabilities: [84] Vendor Specific Information
	Capabilities: [100] Advanced Error Reporting
	Capabilities: [12c] Virtual Channel
	Capabilities: [148] Device Serial Number 68-81-ec-10-00-00-00-1a
	Capabilities: [154] Power Budgeting
00: ec 10 68 81 07 01 10 40 01 00 00 02 10 00 00 00
10: 01 20 00 00 00 00 00 00 04 00 00 c8 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00
40: 01 48 c2 f7 00 00 00 00 03 50 00 00 00 00 00 00
50: 05 60 82 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 84 01 00 23 7f 00 00 10 28 1a 00 11 f4 03 00
70: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 09 00 4c 01 01 1c 02 00 fb ff ff 11
90: 08 30 00 00 d2 1a 05 00 ba 80 00 00 bf 00 00 00
a0: 02 28 ff 01 00 00 00 00 00 08 00 00 03 00 03 00
b0: 00 00 00 00 ff 3f ff 3f ff ff 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

05:00.0 0280: 8086:4222 (rev 02)
	Subsystem: 8086:1000
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0, Cache Line Size 10
	Interrupt: pin A routed to IRQ 185
	Region 0: Memory at cc000000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [c8] Power Management version 2
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [d0] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable-
		Address: 0000000000000000  Data: 0000
	Capabilities: [e0] Express Legacy Endpoint IRQ 0
		Device: Supported: MaxPayload 128 bytes, PhantFunc 0, ExtTag-
		Device: Latency L0s <512ns, L1 unlimited
		Device: AtnBtn- AtnInd- PwrInd-
		Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported-
		Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
		Device: MaxPayload 128 bytes, MaxReadReq 128 bytes
		Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 0
		Link: Latency L0s <128ns, L1 <64us
		Link: ASPM L1 Enabled RCB 64 bytes CommClk+ ExtSynch-
		Link: Speed 2.5Gb/s, Width x1
	Capabilities: [100] Advanced Error Reporting
	Capabilities: [140] Device Serial Number 69-2b-c6-ff-ff-02-13-00
00: 86 80 22 42 06 01 10 00 02 00 80 02 10 00 00 00
10: 00 00 00 cc 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 10
30: 00 00 00 00 c8 00 00 00 00 00 00 00 0a 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 01 d0 22 c8 00 00 00 0d
d0: 05 e0 80 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 10 00 11 00 c0 0e 00 00 10 08 1b 00 11 1c 07 00
f0: 42 01 11 10 00 00 00 00 00 00 00 00 00 00 00 00

0a:06.0 0607: 104c:8039
	Subsystem: 1025:0107
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 168, Cache Line Size 20
	Interrupt: pin A routed to IRQ 201
	Region 0: Memory at d2000000 (32-bit, non-prefetchable) [size=4K]
	Bus: primary=0a, secondary=0b, subordinate=0e, sec-latency=176
	Memory window 0: 88000000-89fff000 (prefetchable)
	Memory window 1: 8a000000-8bfff000
	I/O window 0: 00006000-000060ff
	I/O window 1: 00006400-000064ff
	BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset+ 16bInt+ PostWrite+
	16-bit legacy interface ports at 0001
00: 4c 10 39 80 07 00 10 02 00 00 07 06 20 a8 82 00
10: 00 00 00 d2 a0 00 00 02 0a 0b 0e b0 00 00 00 88
20: 00 f0 ff 89 00 00 00 8a 00 f0 ff 8b 00 60 00 00
30: fc 60 00 00 00 64 00 00 fc 64 00 00 ff 01 c0 05
40: 25 10 07 01 01 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 61 50 44 18 19 00 0b 02 00 00 0f 00 22 1b aa 01
90: c0 02 64 60 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 00 12 fe 00 00 c0 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 35 2f 51 db 65 15 00 6c 00 00 00 00 00 00 00 00

0a:06.2 0180: 104c:803b
	Subsystem: 1025:0107
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 57 (1750ns min, 1000ns max), Cache Line Size 10
	Interrupt: pin A routed to IRQ 10
	Region 0: Memory at d2004000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [44] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 4c 10 3b 80 06 01 10 02 00 00 80 01 10 39 80 00
10: 00 40 00 d2 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 07 04
40: 00 00 00 00 01 00 02 7e 00 00 00 00 60 00 00 00
50: 25 10 07 01 05 01 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0a:06.3 0805: 104c:803c
	Subsystem: 1025:0107
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 57 (1750ns min, 1000ns max), Cache Line Size 10
	Interrupt: pin A routed to IRQ 201
	Region 0: Memory at d2005800 (32-bit, non-prefetchable) [size=256]
	Capabilities: [80] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 4c 10 3c 80 06 01 10 02 00 00 05 08 10 39 80 00
10: 00 58 00 d2 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 07 01
30: 00 00 00 00 80 00 00 00 00 00 00 00 0a 01 07 04
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 02 7e 00 00 00 00 00 00 00 00 25 10 07 01
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: Kernel fix for ICH7M controller
  2006-09-04  6:53   ` Jonathan Dieter
@ 2006-09-04  8:15     ` Tejun Heo
  2006-09-04  9:04       ` Jonathan Dieter
  2006-09-10 19:54       ` Jonathan Dieter
  0 siblings, 2 replies; 9+ messages in thread
From: Tejun Heo @ 2006-09-04  8:15 UTC (permalink / raw)
  To: Jonathan Dieter; +Cc: Jeff Garzik, linux-ide, fedora-devel-list

[-- Attachment #1: Type: text/plain, Size: 53 bytes --]

Can you test the attached patch?

Thanks.

-- 
tejun

[-- Attachment #2: patch --]
[-- Type: text/plain, Size: 2201 bytes --]

diff --git a/drivers/scsi/ata_piix.c b/drivers/scsi/ata_piix.c
index 2d20caf..a9bb3cb 100644
--- a/drivers/scsi/ata_piix.c
+++ b/drivers/scsi/ata_piix.c
@@ -123,7 +123,8 @@ enum {
 	ich6_sata		= 4,
 	ich6_sata_ahci		= 5,
 	ich6m_sata_ahci		= 6,
-	ich8_sata_ahci		= 7,
+	ich7m_sata_ahci		= 7,
+	ich8_sata_ahci		= 8,
 
 	/* constants for mapping table */
 	P0			= 0,  /* port 0 */
@@ -188,7 +189,7 @@ #endif
 	/* 82801GB/GR/GH (ICH7, identical to ICH6) */
 	{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
 	/* 2801GBM/GHM (ICH7M, identical to ICH6M) */
-	{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
+	{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7m_sata_ahci },
 	/* Enterprise Southbridge 2 (where's the datasheet?) */
 	{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
 	/* SATA Controller 1 IDE (ICH8, no datasheet yet) */
@@ -336,6 +337,24 @@ static const struct piix_map_db ich6m_ma
 	},
 };
 
+static const struct piix_map_db ich7m_map_db = {
+	.mask = 0x3,
+	.port_enable = 0x5,
+	.present_shift = 4,
+
+	/* Map 01b isn't specified in the doc but some notebooks use
+	 * it anyway.  ATM, the only case spotted carries subsystem ID
+	 * 1025:0107.  This is the only difference from ich6m.
+	 */
+	.map = {
+		/* PM   PS   SM   SS       MAP */
+		{  P0,  P2,  RV,  RV }, /* 00b */
+		{ IDE, IDE,  P1,  P3 }, /* 01b */
+		{  P0,  P2, IDE, IDE }, /* 10b */
+		{  RV,  RV,  RV,  RV },
+	},
+};
+
 static const struct piix_map_db ich8_map_db = {
 	.mask = 0x3,
 	.port_enable = 0x3,
@@ -355,6 +374,7 @@ static const struct piix_map_db *piix_ma
 	[ich6_sata]		= &ich6_map_db,
 	[ich6_sata_ahci]	= &ich6_map_db,
 	[ich6m_sata_ahci]	= &ich6m_map_db,
+	[ich7m_sata_ahci]	= &ich7m_map_db,
 	[ich8_sata_ahci]	= &ich8_map_db,
 };
 
@@ -444,6 +464,18 @@ #endif
 		.port_ops	= &piix_sata_ops,
 	},
 
+	/* ich7m_sata_ahci */
+	{
+		.sht		= &piix_sht,
+		.host_flags	= ATA_FLAG_SATA |
+				  PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
+				  PIIX_FLAG_AHCI,
+		.pio_mask	= 0x1f,	/* pio0-4 */
+		.mwdma_mask	= 0x07, /* mwdma0-2 */
+		.udma_mask	= 0x7f,	/* udma0-6 */
+		.port_ops	= &piix_sata_ops,
+	},
+
 	/* ich8_sata_ahci */
 	{
 		.sht		= &piix_sht,

^ permalink raw reply related	[flat|nested] 9+ messages in thread

* Re: Kernel fix for ICH7M controller
  2006-09-04  8:15     ` Tejun Heo
@ 2006-09-04  9:04       ` Jonathan Dieter
  2006-09-10 19:54       ` Jonathan Dieter
  1 sibling, 0 replies; 9+ messages in thread
From: Jonathan Dieter @ 2006-09-04  9:04 UTC (permalink / raw)
  To: Tejun Heo; +Cc: Jeff Garzik, linux-ide

I've applied the patch and recompiled the module and everything seems to 
be working fine.

Thanks much,
Jonathan

Tejun Heo wrote:
> Can you test the attached patch?
>
> Thanks.
>


-- 
VGER BF report: H 3.0627e-06

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: Kernel fix for ICH7M controller
  2006-09-04  8:15     ` Tejun Heo
  2006-09-04  9:04       ` Jonathan Dieter
@ 2006-09-10 19:54       ` Jonathan Dieter
  2006-09-10 21:29         ` [PATCH] ata_piix: add map 01b for ICH7M Tejun Heo
  1 sibling, 1 reply; 9+ messages in thread
From: Jonathan Dieter @ 2006-09-10 19:54 UTC (permalink / raw)
  To: Tejun Heo; +Cc: Jeff Garzik, linux-ide

Is there anything else you need me to do or test before the patch goes 
into the mainline kernel?  I've been running it for six days now and 
it's working perfectly.

Thanks again,
Jonathan

Tejun Heo wrote:
> Can you test the attached patch?
>
> Thanks.
>
> ------------------------------------------------------------------------
>
> diff --git a/drivers/scsi/ata_piix.c b/drivers/scsi/ata_piix.c
> index 2d20caf..a9bb3cb 100644
> --- a/drivers/scsi/ata_piix.c
> +++ b/drivers/scsi/ata_piix.c
> @@ -123,7 +123,8 @@ enum {
>  	ich6_sata		= 4,
>  	ich6_sata_ahci		= 5,
>  	ich6m_sata_ahci		= 6,
> -	ich8_sata_ahci		= 7,
> +	ich7m_sata_ahci		= 7,
> +	ich8_sata_ahci		= 8,
>  
>  	/* constants for mapping table */
>  	P0			= 0,  /* port 0 */
> @@ -188,7 +189,7 @@ #endif
>  	/* 82801GB/GR/GH (ICH7, identical to ICH6) */
>  	{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
>  	/* 2801GBM/GHM (ICH7M, identical to ICH6M) */
> -	{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
> +	{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7m_sata_ahci },
>  	/* Enterprise Southbridge 2 (where's the datasheet?) */
>  	{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
>  	/* SATA Controller 1 IDE (ICH8, no datasheet yet) */
> @@ -336,6 +337,24 @@ static const struct piix_map_db ich6m_ma
>  	},
>  };
>  
> +static const struct piix_map_db ich7m_map_db = {
> +	.mask = 0x3,
> +	.port_enable = 0x5,
> +	.present_shift = 4,
> +
> +	/* Map 01b isn't specified in the doc but some notebooks use
> +	 * it anyway.  ATM, the only case spotted carries subsystem ID
> +	 * 1025:0107.  This is the only difference from ich6m.
> +	 */
> +	.map = {
> +		/* PM   PS   SM   SS       MAP */
> +		{  P0,  P2,  RV,  RV }, /* 00b */
> +		{ IDE, IDE,  P1,  P3 }, /* 01b */
> +		{  P0,  P2, IDE, IDE }, /* 10b */
> +		{  RV,  RV,  RV,  RV },
> +	},
> +};
> +
>  static const struct piix_map_db ich8_map_db = {
>  	.mask = 0x3,
>  	.port_enable = 0x3,
> @@ -355,6 +374,7 @@ static const struct piix_map_db *piix_ma
>  	[ich6_sata]		= &ich6_map_db,
>  	[ich6_sata_ahci]	= &ich6_map_db,
>  	[ich6m_sata_ahci]	= &ich6m_map_db,
> +	[ich7m_sata_ahci]	= &ich7m_map_db,
>  	[ich8_sata_ahci]	= &ich8_map_db,
>  };
>  
> @@ -444,6 +464,18 @@ #endif
>  		.port_ops	= &piix_sata_ops,
>  	},
>  
> +	/* ich7m_sata_ahci */
> +	{
> +		.sht		= &piix_sht,
> +		.host_flags	= ATA_FLAG_SATA |
> +				  PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
> +				  PIIX_FLAG_AHCI,
> +		.pio_mask	= 0x1f,	/* pio0-4 */
> +		.mwdma_mask	= 0x07, /* mwdma0-2 */
> +		.udma_mask	= 0x7f,	/* udma0-6 */
> +		.port_ops	= &piix_sata_ops,
> +	},
> +
>  	/* ich8_sata_ahci */
>  	{
>  		.sht		= &piix_sht,
>   


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH] ata_piix: add map 01b for ICH7M
  2006-09-10 19:54       ` Jonathan Dieter
@ 2006-09-10 21:29         ` Tejun Heo
  0 siblings, 0 replies; 9+ messages in thread
From: Tejun Heo @ 2006-09-10 21:29 UTC (permalink / raw)
  To: Jeff Garzik; +Cc: Jonathan Dieter, linux-ide

Although the document says otherwise, some ich7m uses map 01b.  This
patch adds separate map DB for ICH7M and adds map entry for 01b.

This was spotted on an ASUS laptop by Jonathan Dieter.

Signed-off-by: Tejun Heo <htejun@gmail.com>
Cc: Jonathan Dieter <jdieter@gmail.com>
---
Jonathan, thanks for reminding me.  I'm on the road and kind of forgot
about this.

Jeff, this patch is against #upstream-fixes.  If you want the patch
done against #upstream, please let me know.

Thanks.

diff --git a/drivers/scsi/ata_piix.c b/drivers/scsi/ata_piix.c
index 2d20caf..a9bb3cb 100644
--- a/drivers/scsi/ata_piix.c
+++ b/drivers/scsi/ata_piix.c
@@ -123,7 +123,8 @@ enum {
 	ich6_sata		= 4,
 	ich6_sata_ahci		= 5,
 	ich6m_sata_ahci		= 6,
-	ich8_sata_ahci		= 7,
+	ich7m_sata_ahci		= 7,
+	ich8_sata_ahci		= 8,
 
 	/* constants for mapping table */
 	P0			= 0,  /* port 0 */
@@ -188,7 +189,7 @@ #endif
 	/* 82801GB/GR/GH (ICH7, identical to ICH6) */
 	{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
 	/* 2801GBM/GHM (ICH7M, identical to ICH6M) */
-	{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
+	{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7m_sata_ahci },
 	/* Enterprise Southbridge 2 (where's the datasheet?) */
 	{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
 	/* SATA Controller 1 IDE (ICH8, no datasheet yet) */
@@ -336,6 +337,24 @@ static const struct piix_map_db ich6m_ma
 	},
 };
 
+static const struct piix_map_db ich7m_map_db = {
+	.mask = 0x3,
+	.port_enable = 0x5,
+	.present_shift = 4,
+
+	/* Map 01b isn't specified in the doc but some notebooks use
+	 * it anyway.  ATM, the only case spotted carries subsystem ID
+	 * 1025:0107.  This is the only difference from ich6m.
+	 */
+	.map = {
+		/* PM   PS   SM   SS       MAP */
+		{  P0,  P2,  RV,  RV }, /* 00b */
+		{ IDE, IDE,  P1,  P3 }, /* 01b */
+		{  P0,  P2, IDE, IDE }, /* 10b */
+		{  RV,  RV,  RV,  RV },
+	},
+};
+
 static const struct piix_map_db ich8_map_db = {
 	.mask = 0x3,
 	.port_enable = 0x3,
@@ -355,6 +374,7 @@ static const struct piix_map_db *piix_ma
 	[ich6_sata]		= &ich6_map_db,
 	[ich6_sata_ahci]	= &ich6_map_db,
 	[ich6m_sata_ahci]	= &ich6m_map_db,
+	[ich7m_sata_ahci]	= &ich7m_map_db,
 	[ich8_sata_ahci]	= &ich8_map_db,
 };
 
@@ -444,6 +464,18 @@ #endif
 		.port_ops	= &piix_sata_ops,
 	},
 
+	/* ich7m_sata_ahci */
+	{
+		.sht		= &piix_sht,
+		.host_flags	= ATA_FLAG_SATA |
+				  PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
+				  PIIX_FLAG_AHCI,
+		.pio_mask	= 0x1f,	/* pio0-4 */
+		.mwdma_mask	= 0x07, /* mwdma0-2 */
+		.udma_mask	= 0x7f,	/* udma0-6 */
+		.port_ops	= &piix_sata_ops,
+	},
+
 	/* ich8_sata_ahci */
 	{
 		.sht		= &piix_sht,

^ permalink raw reply related	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2006-09-10 21:29 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2006-09-03 14:26 Kernel fix for ICH7M controller Jonathan Dieter
2006-09-04  2:47 ` Tejun Heo
2006-09-04  5:45   ` Jeff Garzik
2006-09-04  7:34     ` Tejun Heo
2006-09-04  6:53   ` Jonathan Dieter
2006-09-04  8:15     ` Tejun Heo
2006-09-04  9:04       ` Jonathan Dieter
2006-09-10 19:54       ` Jonathan Dieter
2006-09-10 21:29         ` [PATCH] ata_piix: add map 01b for ICH7M Tejun Heo

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