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From: Jeff Garzik <jeff@garzik.org>
To: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: linux-ide@vger.kernel.org, alan@lxorguk.ukuu.org.uk
Subject: Re: [PATCH] pata_sl82c105: wrong assumptions about compatible PIO modes
Date: Tue, 06 Feb 2007 19:37:19 -0500	[thread overview]
Message-ID: <45C91F3F.1010300@garzik.org> (raw)
In-Reply-To: <200701302040.30895.sshtylyov@ru.mvista.com>

Sergei Shtylyov wrote:
> Fix the wrong "compatible" PIO mode choices: MWDMA0 has 480 ns cycle while PIO1
> only has 383 ns cycle, and MWDMA2 timings matchs those of PIO4 exactly.
> 
> ---
> Frankly speaking, I'm not sure this function is useful or correct at all --
> with the DMA timings being actually programmed in sl82c105_bmdma_start()...
> 
> And the issue of the same registers being used for both PIO and DMA timings is
> not specific for this driver at all but seems to be addressed only by it...
> 
> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
> 
>  drivers/ata/pata_sl82c105.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)

applied


      parent reply	other threads:[~2007-02-07  0:37 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-01-30 17:40 [PATCH] pata_sl82c105: wrong assumptions about compatible PIO modes Sergei Shtylyov
2007-01-30 19:07 ` Alan
2007-01-30 19:08   ` Sergei Shtylyov
2007-01-30 19:27     ` Alan
2007-02-07  0:37 ` Jeff Garzik [this message]

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