* [PATCH 2.6.20] sata_vsc: use default cache line size if non-zero
@ 2007-02-07 14:29 Dailey, Nate
2007-02-08 8:59 ` Jeremy Higdon
0 siblings, 1 reply; 3+ messages in thread
From: Dailey, Nate @ 2007-02-07 14:29 UTC (permalink / raw)
To: linux-ide; +Cc: Jeremy Higdon
[-- Attachment #1: Type: text/plain, Size: 324 bytes --]
The attached patch modifies drivers/ata/sata_vsc.c to only set the cache
line size to 0x80 if the default value is zero. Apparently zero isn't
allowed due to a bug in the chip, but I've found performance is much
better with the (non-zero) default instead of 0x80.
Signed-off-by: Nate Dailey <nate.dailey@stratus.com>
[-- Attachment #2: sata_vsc_CLS.patch --]
[-- Type: application/octet-stream, Size: 956 bytes --]
--- old/drivers/ata/sata_vsc.c 2007-02-04 13:44:54.000000000 -0500
+++ new/drivers/ata/sata_vsc.c 2007-02-07 09:13:17.000000000 -0500
@@ -345,6 +345,7 @@ static int __devinit vsc_sata_init_one (
int pci_dev_busy = 0;
void __iomem *mmio_base;
int rc;
+ u8 cls;
if (!printed_version++)
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
@@ -394,9 +395,13 @@ static int __devinit vsc_sata_init_one (
base = (unsigned long) mmio_base;
/*
- * Due to a bug in the chip, the default cache line size can't be used
+ * Due to a bug in the chip, the default cache line size can't be
+ * used (unless the default is non-zero).
*/
- pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
+ pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
+ if (cls == 0x00) {
+ pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
+ }
probe_ent->sht = &vsc_sata_sht;
probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH 2.6.20] sata_vsc: use default cache line size if non-zero
2007-02-07 14:29 [PATCH 2.6.20] sata_vsc: use default cache line size if non-zero Dailey, Nate
@ 2007-02-08 8:59 ` Jeremy Higdon
2007-02-15 23:14 ` Jeff Garzik
0 siblings, 1 reply; 3+ messages in thread
From: Jeremy Higdon @ 2007-02-08 8:59 UTC (permalink / raw)
To: Dailey, Nate; +Cc: linux-ide
On Wed, Feb 07, 2007 at 09:29:28AM -0500, Dailey, Nate wrote:
> The attached patch modifies drivers/ata/sata_vsc.c to only set the cache
> line size to 0x80 if the default value is zero. Apparently zero isn't
> allowed due to a bug in the chip, but I've found performance is much
> better with the (non-zero) default instead of 0x80.
>
> Signed-off-by: Nate Dailey <nate.dailey@stratus.com>
Signed-off-by: Jeremy Higdon <jeremy@sgi.com>
Here is the attachment from Nate, inline.
Content-Description: sata_vsc_CLS.patch
--- old/drivers/ata/sata_vsc.c 2007-02-04 13:44:54.000000000 -0500
+++ new/drivers/ata/sata_vsc.c 2007-02-07 09:13:17.000000000 -0500
@@ -345,6 +345,7 @@ static int __devinit vsc_sata_init_one (
int pci_dev_busy = 0;
void __iomem *mmio_base;
int rc;
+ u8 cls;
if (!printed_version++)
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
@@ -394,9 +395,13 @@ static int __devinit vsc_sata_init_one (
base = (unsigned long) mmio_base;
/*
- * Due to a bug in the chip, the default cache line size can't be used
+ * Due to a bug in the chip, the default cache line size can't be
+ * used (unless the default is non-zero).
*/
- pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
+ pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
+ if (cls == 0x00) {
+ pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
+ }
probe_ent->sht = &vsc_sata_sht;
probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH 2.6.20] sata_vsc: use default cache line size if non-zero
2007-02-08 8:59 ` Jeremy Higdon
@ 2007-02-15 23:14 ` Jeff Garzik
0 siblings, 0 replies; 3+ messages in thread
From: Jeff Garzik @ 2007-02-15 23:14 UTC (permalink / raw)
To: Jeremy Higdon; +Cc: Dailey, Nate, linux-ide
Jeremy Higdon wrote:
> On Wed, Feb 07, 2007 at 09:29:28AM -0500, Dailey, Nate wrote:
>> The attached patch modifies drivers/ata/sata_vsc.c to only set the cache
>> line size to 0x80 if the default value is zero. Apparently zero isn't
>> allowed due to a bug in the chip, but I've found performance is much
>> better with the (non-zero) default instead of 0x80.
>>
>> Signed-off-by: Nate Dailey <nate.dailey@stratus.com>
> Signed-off-by: Jeremy Higdon <jeremy@sgi.com>
>
> Here is the attachment from Nate, inline.
>
> Content-Description: sata_vsc_CLS.patch
> --- old/drivers/ata/sata_vsc.c 2007-02-04 13:44:54.000000000 -0500
> +++ new/drivers/ata/sata_vsc.c 2007-02-07 09:13:17.000000000 -0500
> @@ -345,6 +345,7 @@ static int __devinit vsc_sata_init_one (
> int pci_dev_busy = 0;
> void __iomem *mmio_base;
> int rc;
> + u8 cls;
>
> if (!printed_version++)
> dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
> @@ -394,9 +395,13 @@ static int __devinit vsc_sata_init_one (
> base = (unsigned long) mmio_base;
>
> /*
> - * Due to a bug in the chip, the default cache line size can't be used
> + * Due to a bug in the chip, the default cache line size can't be
> + * used (unless the default is non-zero).
> */
> - pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
> + pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
> + if (cls == 0x00) {
> + pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
> + }
applied, after removing the superfluous braces :)
^ permalink raw reply [flat|nested] 3+ messages in thread
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2007-02-07 14:29 [PATCH 2.6.20] sata_vsc: use default cache line size if non-zero Dailey, Nate
2007-02-08 8:59 ` Jeremy Higdon
2007-02-15 23:14 ` Jeff Garzik
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