Re: Question about PATA Sil680 Cache Line Size and Performance Degradation on ARM XScale

[Jeff Garzik <jeff@garzik.org>]

Fajun Chen wrote:
> On 2/22/07, Jeff Garzik <jeff@garzik.org> wrote:
>> Alan wrote:
>> >> Since Sil3124 has better PCI read/write performance, as a reference,
>> >> could someone explain or point me to the PCI configuration code for
>> >> Sil3124? I couldn't find it in sata_sil24.c.
>> >
>> > Are you sure the values used are not the power on ones in this case ?
>>
>> The values used, most likely, are BIOS-programmed.
>>
>> sata_sil24.c does not call pci_set_mwi(), which is the only code in the
>> kernel (besides driver-specific, hand-coded stuff) that adjusts the PCI
>> cacheline register value.
>>
> 
> I traced the latency timer and cache line size setup in  SATA Sil3124.
> Latency timer is set to 0x40 and cache line size is set to 0.  For
> PATA Sil680, latency timer is set to 0 and cache line size is set to
> 1.  If Sil3124 is a good reference for performance, we probably should
> set latency timer to 0x40 and cache line size to 0 or 8 for Sil680.
> Both Sil3124 and Sil680 specs recommend using Read Multiple as a PCI

If you are going to be using PCI transactions that operate on cacheline 
size-based quantities of data, you should definitely program the PCI 
config register to a non-zero value.


> master, ARM XScale cache line is 32 bytes, so it is probably better to
> set cache line size to 8 for ARM XScale.   I tested both
> configurations(cache line of 0 vs 8) though, no big difference in IO
> performance but both are much better than default configuration in
> Sil680.

Read pci_set_cacheline_size() in drivers/pci/pci.c for the proper method 
of programming.

	Jeff