From: Jeff Garzik <jeff@garzik.org>
To: Fajun Chen <fajunchen@gmail.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>,
"linux-ide@vger.kernel.org" <linux-ide@vger.kernel.org>,
Tejun Heo <htejun@gmail.com>
Subject: Re: PATA Sil680 Command Timeout on ARM XScale
Date: Wed, 14 Mar 2007 18:36:13 -0400 [thread overview]
Message-ID: <45F878DD.9000404@garzik.org> (raw)
In-Reply-To: <8202f4270703141527g459165dah647a8ad4116b96bb@mail.gmail.com>
Fajun Chen wrote:
> Since primary channel and secondary channel share the same IRQ, the
> ISR could be called to service one or both channels. So I would think
> it's normal to see "irq trap" traces when both channels are in IO
> operation, correct?
The irq trap code only occurs after a certain number of unhandled
interrupts.
> I have another question in regard to ata_host_intr() function in
> libata-core.c. For PIO read/write, the status of interrupt pin was not
> checked before moving the host state machine. Sil680 spec. recommend
> checking IDE channel interupt (bit 11 in the IDEx Task File Timing and
> Config + Status register) though. Could someone explain why interrupt
> status does not need to be checked for PIO?
Reading the Status register (as opposed to AltStatus) should clear the
interrupt condition, on standard hardware.
Jeff
next prev parent reply other threads:[~2007-03-14 22:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-03-13 18:34 PATA Sil680 Command Timeout on ARM XScale Fajun Chen
2007-03-13 19:39 ` Alan Cox
2007-03-13 21:17 ` Fajun Chen
2007-03-14 22:27 ` Fajun Chen
2007-03-14 22:36 ` Jeff Garzik [this message]
2007-03-14 23:46 ` Fajun Chen
2007-03-15 2:32 ` Albert Lee
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