Re: [PATCH 8/8] libata: ack more unsolicited INTRQ

[Tejun Heo <htejun@gmail.com>]

Hello, Albert.

Albert Lee wrote:
> Back to the problem that the patch was trying to solve,
> i.e. unsolicited interrupt when HSM doing data transfer in the wq,
> is there any experience about how often such situation occurs?
> 
> IMHO, it seems not something that happens often. If the cable/devices
> are well configured, the intrq would mostly occur when it should.
> 
> Even if the unsolicited irq happens, maybe the current code has
> good chance to handle it?
> e.g. ata_irq_task() already reads the status before data transfer,
> thus possibly clearing some of unsolicited irqs.
> e.g. maybe the data transfer in the workqueue is quick enough?
> If yes, hopefully the ATA_PFLAG_HSM_WQ is soon cleared, and
> then the interrupt handler can come in ack the irq. (Much the same
> way when the irq handler encounters "early irq" by bad devices.)

The problem is that if you have only one cpu and the unsolicited IRQ
happens, you never get to execute any non-IRQ handler code.  IRQ is
raised immediately again when the IRQ handler is complete, so nothing
can be quick enough.

I don't really know how to fix this.  It seems the only options are 1.
disable_irq() as IDE does which sucks if the IRQ is shared 2. doing PIO
transfers with local IRQ disabled and spinlock locked which makes the
system stutter like hell.  Oh crap, all this because we don't have
simple reliable IRQ pending bit.  :-(

Oh, BTW, we do have reliable IRQ pending bit on ata_piix's.  The IRQ bit
in BMDMA status acts as a IRQ pending even if the command isn't a DMA
one.  This is why we clear BMDMA IRQ even after nodata or PIO commands,
so we can probably solve the problem nicely for ata_piix by calling
ata_port_freeze() if IRQ is received while ATA_PFLAG_HSM_WQ is set.
sata_sil also has reliable IRQ pending bit.

Thanks.

-- 
tejun