From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
To: Linas Vepstas <linas@austin.ibm.com>
Cc: linux-ide@vger.kernel.org, bzolnier@gmail.com,
Alan Cox <alan@lxorguk.ukuu.org.uk>,
Andries.Brouwer@cwi.nl, michal.kepien@poczta.onet.pl
Subject: Re: [PATCH pata-2.6 fix queue] hpt366: don't check enablebits for HPT36x
Date: Fri, 25 May 2007 00:53:19 +0400 [thread overview]
Message-ID: <4655FB3F.2070605@ru.mvista.com> (raw)
In-Reply-To: <20070524203414.GO5921@austin.ibm.com>
Linas Vepstas wrote:
>>>HPT36x chip don't seem to have the channel enable bits, so prevent the IDE
>>>core from checking them...
>>>Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
>>> d->channels = 1;
>>>+ d->enablebits[0].reg = 0;
> The original patch worked for me.
>> Linas, Andries, Michal, cound you try this instead:
>>
>> d->enablebits[0].mask = d->enablebits[0].val = 0x10;
> Based on the printk's from my system, this should work fine.
> The config register had 0x33 in it, so 0x33 & mask == val for me.
> I'll reply tommorrow if this doesn't work.
It probably won't work the way it should anyway -- the secondary channel
(and controller in this case) uses another bit in this register and the
controllers get registered with IDE core "in pair". Highpoint knows how to
make broken hardware. :-)
> --linas
MBR, Sergei
next prev parent reply other threads:[~2007-05-24 20:51 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-05-04 19:18 [PATCH pata-2.6 fix queue] hpt366: don't check enablebits for HPT36x Sergei Shtylyov
2007-05-05 19:30 ` Bartlomiej Zolnierkiewicz
2007-05-05 20:18 ` Sergei Shtylyov
2007-05-05 21:20 ` Bartlomiej Zolnierkiewicz
2007-05-06 22:53 ` Andries Brouwer
2007-05-24 20:23 ` Sergei Shtylyov
2007-05-24 20:34 ` Linas Vepstas
2007-05-24 20:53 ` Sergei Shtylyov [this message]
2007-05-24 21:06 ` Linas Vepstas
2007-05-24 21:47 ` Sergei Shtylyov
2007-05-25 17:58 ` Linas Vepstas
2007-05-25 18:12 ` Sergei Shtylyov
2007-05-28 20:32 ` Andries Brouwer
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