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* Question about PATA Sil680 Bus Reset Code
@ 2007-07-09 16:46 Fajun Chen
  2007-07-09 16:58 ` Jeff Garzik
  2007-07-09 18:37 ` Sergei Shtylyov
  0 siblings, 2 replies; 8+ messages in thread
From: Fajun Chen @ 2007-07-09 16:46 UTC (permalink / raw)
  To: linux-ide@vger.kernel.org

Hi,

Could someone help me interpret the code snippet below:
static int sil680_bus_reset(struct ata_port *ap,unsigned int *classes)
{
        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
        unsigned long addr = sil680_selreg(ap, 0);
        u8 reset;

        pci_read_config_byte(pdev, addr, &reset);
        pci_write_config_byte(pdev, addr, reset | 0x03);   // ?
        udelay(25);
        pci_write_config_byte(pdev, addr, reset);
        return ata_std_softreset(ap, classes);
}

Based on Sil680 data sheet, channel reset bit is bit 2,  why the reset
code above is not "pci_write_config_byte(pdev, addr, reset | 0x04);"?

Thanks in advance!

Fajun

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2007-07-10 22:04 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2007-07-09 16:46 Question about PATA Sil680 Bus Reset Code Fajun Chen
2007-07-09 16:58 ` Jeff Garzik
2007-07-09 18:37 ` Sergei Shtylyov
2007-07-09 18:46   ` Jeff Garzik
2007-07-09 18:51     ` Sergei Shtylyov
2007-07-09 22:09   ` Alan Cox
2007-07-10 12:58     ` Sergei Shtylyov
2007-07-10 22:00       ` Bartlomiej Zolnierkiewicz

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