[PATCH] pata_hpt37x: Fix 2.6.22 clock PLL regression

[PATCH] pata_hpt37x: Fix 2.6.22 clock PLL regression

[Alan Cox]

	Just one version of Linux ago
	The PLL code broke - oh no!
	But set the right mode
	And fix up the code
	Makes the PLL timing sync go

Closes-bug: #8791
Signed-off-by: Alan Cox <alan@redhat.com>

diff -u --new-file --recursive --exclude-from /usr/src/exclude linux.vanilla-2.6.23rc1/drivers/ata/pata_hpt37x.c linux-2.6.23rc1/drivers/ata/pata_hpt37x.c
--- linux.vanilla-2.6.23rc1/drivers/ata/pata_hpt37x.c	2007-07-23 12:56:11.000000000 +0100
+++ linux-2.6.23rc1/drivers/ata/pata_hpt37x.c	2007-07-23 14:44:39.000000000 +0100
@@ -26,7 +26,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME	"pata_hpt37x"
-#define DRV_VERSION	"0.6.6"
+#define DRV_VERSION	"0.6.7"
 
 struct hpt_clock {
 	u8	xfer_speed;
@@ -1103,17 +1103,17 @@
 
 		/* Select the DPLL clock. */
 		pci_write_config_byte(dev, 0x5b, 0x21);
-		pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
+		pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
 
 		for(adjust = 0; adjust < 8; adjust++) {
 			if (hpt37x_calibrate_dpll(dev))
 				break;
 			/* See if it'll settle at a fractionally different clock */
-			if ((adjust & 3) == 3) {
-				f_low --;
-				f_high ++;
-			}
-			pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
+			if (adjust & 1)
+				f_low -= adjust >> 1;
+			else
+				f_high += adjust >> 1;
+			pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
 		}
 		if (adjust == 8) {
 			printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n");

Re: [PATCH] pata_hpt37x: Fix 2.6.22 clock PLL regression

[Sergei Shtylyov]

Hello.

Alan Cox wrote:

> 	Just one version of Linux ago
> 	The PLL code broke - oh no!
> 	But set the right mode
> 	And fix up the code
> 	Makes the PLL timing sync go

/me applauds :-)

> Closes-bug: #8791
> Signed-off-by: Alan Cox <alan@redhat.com>

Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>

    However, I found it strange that HPT374 against which was that bug report 
works with 66 MHz DPLL clock -- while I've recently forbidden that clock in 
the IDE driver because it was causing DMA timeouts.

> diff -u --new-file --recursive --exclude-from /usr/src/exclude linux.vanilla-2.6.23rc1/drivers/ata/pata_hpt37x.c linux-2.6.23rc1/drivers/ata/pata_hpt37x.c
> --- linux.vanilla-2.6.23rc1/drivers/ata/pata_hpt37x.c	2007-07-23 12:56:11.000000000 +0100
> +++ linux-2.6.23rc1/drivers/ata/pata_hpt37x.c	2007-07-23 14:44:39.000000000 +0100
> @@ -26,7 +26,7 @@
>  #include <linux/libata.h>
>  
>  #define DRV_NAME	"pata_hpt37x"
> -#define DRV_VERSION	"0.6.6"
> +#define DRV_VERSION	"0.6.7"
>  
>  struct hpt_clock {
>  	u8	xfer_speed;
> @@ -1103,17 +1103,17 @@
>  
>  		/* Select the DPLL clock. */
>  		pci_write_config_byte(dev, 0x5b, 0x21);
> -		pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
> +		pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);

    Heh, was quite a silly mistake. :-)

 >  		for(adjust = 0; adjust < 8; adjust++) {
 >  			if (hpt37x_calibrate_dpll(dev))
 >  				break;
 >  			/* See if it'll settle at a fractionally different clock */
 > -			if ((adjust & 3) == 3) {
 > -				f_low --;
 > -				f_high ++;
 > -			}
 > -			pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
 > +			if (adjust & 1)
 > +				f_low -= adjust >> 1;
 > +			else
 > +				f_high += adjust >> 1;
 > +			pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);

    OK, I'm seeing that the "oldie but goodie" calibration algrithm has 
finally found its way to the libata driver too. :-)

MBR, Sergei

Re: [PATCH] pata_hpt37x: Fix 2.6.22 clock PLL regression

[Jeff Garzik]

Alan Cox wrote:
> 	Just one version of Linux ago
> 	The PLL code broke - oh no!
> 	But set the right mode
> 	And fix up the code
> 	Makes the PLL timing sync go
> 
> Closes-bug: #8791
> Signed-off-by: Alan Cox <alan@redhat.com>

applied

Re: [PATCH] pata_hpt37x: Fix 2.6.22 clock PLL regression

[Linus Torvalds]

On Tue, 24 Jul 2007, Alan Cox wrote:
> 
> 	Just one version of Linux ago
> 	The PLL code broke - oh no!
> 	But set the right mode
> 	And fix up the code
> 	Makes the PLL timing sync go

Alan, I'm getting a bit worried about you.

		Linus