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* [PATCH 1/2] pata_hpt37x: actually clock HPT374 by 50 MHz DPLL
@ 2007-08-05 18:45 Sergei Shtylyov
  2007-08-05 19:23 ` Alan Cox
                   ` (2 more replies)
  0 siblings, 3 replies; 15+ messages in thread
From: Sergei Shtylyov @ 2007-08-05 18:45 UTC (permalink / raw)
  To: jgarzik, linux-ide; +Cc: alan, rah

The DPLL tuning code always set up it for 66 MHz due to wrong UltraDMA mask
including mode 5 used to check for the necessity of 66 MHz clocking -- This
caused 66 MHz clock to be used for HPT374 chip that does not tolerate it.
While fixing this, also remove PLL mode from the TODO list -- I don't think
it's still relevant item.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>

---
This is against the current Linus tree.
Bob, please test it and report what you'll find out...

 drivers/ata/pata_hpt37x.c |   12 ++++--------
 1 files changed, 4 insertions(+), 8 deletions(-)

Index: linux-2.6/drivers/ata/pata_hpt37x.c
===================================================================
--- linux-2.6.orig/drivers/ata/pata_hpt37x.c
+++ linux-2.6/drivers/ata/pata_hpt37x.c
@@ -8,12 +8,10 @@
  * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
  * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
  * Portions Copyright (C) 2003		Red Hat Inc
- * Portions Copyright (C) 2005-2006	MontaVista Software, Inc.
+ * Portions Copyright (C) 2005-2007	MontaVista Software, Inc.
  *
  * TODO
- *	PLL mode
- *	Look into engine reset on timeout errors. Should not be
- *		required.
+ *	Look into engine reset on timeout errors. Should not be	required.
  */
 
 #include <linux/kernel.h>
@@ -26,7 +24,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME	"pata_hpt37x"
-#define DRV_VERSION	"0.6.7"
+#define DRV_VERSION	"0.6.8"
 
 struct hpt_clock {
 	u8	xfer_speed;
@@ -1092,9 +1090,7 @@ static int hpt37x_init_one(struct pci_de
 		int dpll, adjust;
 
 		/* Compute DPLL */
-		dpll = 2;
-		if (port->udma_mask & 0xE0)
-			dpll = 3;
+		dpll = (port->udma_mask & 0xC0) ? 3 : 2;
 
 		f_low = (MHz[clock_slot] * 48) / MHz[dpll];
 		f_high = f_low + 2;


^ permalink raw reply	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2007-08-10 15:37 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2007-08-05 18:45 [PATCH 1/2] pata_hpt37x: actually clock HPT374 by 50 MHz DPLL Sergei Shtylyov
2007-08-05 19:23 ` Alan Cox
2007-08-08  0:49   ` Jeff Garzik
2007-08-08  1:17     ` Alan Cox
2007-08-08  1:22       ` Jeff Garzik
2007-08-08  1:41         ` Alan Cox
2007-08-06 16:53 ` Bob Ham
2007-08-06 17:16   ` Sergei Shtylyov
2007-08-09 20:48 ` Bartlomiej Zolnierkiewicz
2007-08-09 22:52   ` Alan Cox
2007-08-09 23:52     ` Bartlomiej Zolnierkiewicz
2007-08-10 13:24       ` Alan Cox
2007-08-10 15:39         ` Sergei Shtylyov
2007-08-10 15:36       ` Sergei Shtylyov
2007-08-10 15:34   ` Sergei Shtylyov

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