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From: Matt Sealey <matt@genesi-usa.com>
To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: linux-ide@vger.kernel.org
Subject: Re: Read Prefetch, Post Write on IDE chipsets
Date: Sun, 02 Sep 2007 15:04:22 +0100	[thread overview]
Message-ID: <46DAC2E6.6070102@genesi-usa.com> (raw)
In-Reply-To: <20070902150034.7a6713f5@the-village.bc.nu>

Alan Cox wrote:
> On Sun, 02 Sep 2007 13:51:43 +0100
> Matt Sealey <matt@genesi-usa.com> wrote:
> 
>> But, what is it? I've never seen any documentation but which register to use
>> to toggle it.. no vendor recommendations to turn it on, it seems like a rather
>> secret feature..?
> 
> Chipset specific. Some public documentation discusses it for certain
> chips (eg the Intel ATA tuning guidelines). For others you may need the
> BIOS vendor manual or similar.

All I see is.. that if you want to turn it on, you must make sure of a few things.

There is no discussion on what it DOES, I assume it simply buffers a little more
somewhere (somehow?) inside the chipset, for the purpose of allowing more
streamlined PIO access. But it has some awesome limitations..

Is it even relevant anymore? Does anyone even notice if these features are turned off?

-- 
Matt Sealey <matt@genesi-usa.com>
Genesi, Manager, Developer Relations

  reply	other threads:[~2007-09-02 14:02 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-09-02 12:51 Read Prefetch, Post Write on IDE chipsets Matt Sealey
2007-09-02 14:00 ` Alan Cox
2007-09-02 14:04   ` Matt Sealey [this message]
2007-09-02 14:07 ` Sergei Shtylyov
2007-09-02 14:12 ` Sergei Shtylyov
2007-09-02 14:23   ` Sergei Shtylyov

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