From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
To: Matt Sealey <matt@genesi-usa.com>
Cc: linux-ide@vger.kernel.org
Subject: Re: Read Prefetch, Post Write on IDE chipsets
Date: Sun, 02 Sep 2007 18:12:56 +0400 [thread overview]
Message-ID: <46DAC4E8.2070007@ru.mvista.com> (raw)
In-Reply-To: <46DAB1DF.5050109@genesi-usa.com>
Matt Sealey wrote:
> Does anyone have any decent information on the purpose, performance
> potential
> or perhaps quirks of the "read prefetch" and "post write" buffer
> features on
> some IDE chipsets?
Oh, I've forgotten to reply about posting. :-)
There's a (little) wrtie post buffer in the IDE contoroller where it puts the
data from the PCI and GNTs the PCI transfer. The data later get output to the
IDE bus when the IDE timings are met, so the slow IDE transfers (which usually
need to wait for active/recovery time) doesn't hog the PCI too.
MBR, Sergei
next prev parent reply other threads:[~2007-09-02 14:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-09-02 12:51 Read Prefetch, Post Write on IDE chipsets Matt Sealey
2007-09-02 14:00 ` Alan Cox
2007-09-02 14:04 ` Matt Sealey
2007-09-02 14:07 ` Sergei Shtylyov
2007-09-02 14:12 ` Sergei Shtylyov [this message]
2007-09-02 14:23 ` Sergei Shtylyov
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