Re: [PATCH] jmicron: update quirk for JMB361/3/5/6

[Jeff Garzik <jeff@garzik.org>]

Tejun Heo wrote:
> Set bits 0, 4, 5 and 7 of PCI configuration register 0x40 in the
> quirk.  This has the following effects and is recommended by the
> vendor.
> 
> * Force enable of IDE channels (used to be left alone as BIOS
>   configured)
> 
> * Change initial phase behavior of PIO cycle such that the host pulls
>   down the bus instead of tristating it.  Vendor recommends this
>   setting.
> 
> The above settings are better for the current generation of
> controllers and needed for the upcoming next generation.
> 
> Tested on JMB363.
> 
> Signed-off-by: Tejun Heo <htejun@gmail.com>
> Cc: Ethan Hsiao <ethanhsiao@jmicron.com>
> ---
>  drivers/pci/quirks.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> Index: work/drivers/pci/quirks.c
> ===================================================================
> --- work.orig/drivers/pci/quirks.c
> +++ work/drivers/pci/quirks.c
> @@ -1230,7 +1230,7 @@ static void quirk_jmicron_ata(struct pci
>  	case PCI_DEVICE_ID_JMICRON_JMB363:
>  		/* Enable dual function mode, AHCI on fn 0, IDE fn1 */
>  		/* Set the class codes correctly and then direct IDE 0 */
> -		conf1 |= 0x00C2A102; /* Set 1, 8, 13, 15, 17, 22, 23 */
> +		conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
>  		break;

applied