FIS structure and Command List structure for AHCI SATA controller

FIS structure and Command List structure for AHCI SATA controller

[mike zheng]

Hi All,

I am working on an AHCI SATA controller. For each port, there is one
FIS descriptor and one Command List, which points to a Received FIS
structure and Command List structure. So what is Received FIS
structure? The Command List structure points to Command Table, that
has Command FIS field and Physical Region Descriptor table. I assume
the Command table is used for the communication between processor and
the SATA controller. Then why do we need the Received FIS structure?

Thanks for your help,

Mike

Re: FIS structure and Command List structure for AHCI SATA controller

[Jeff Garzik]

On Thu, Nov 08, 2007 at 10:38:25PM -0500, mike zheng wrote:
> I am working on an AHCI SATA controller. For each port, there is one
> FIS descriptor and one Command List, which points to a Received FIS
> structure and Command List structure. So what is Received FIS
> structure? The Command List structure points to Command Table, that
> has Command FIS field and Physical Region Descriptor table. I assume
> the Command table is used for the communication between processor and
> the SATA controller. Then why do we need the Received FIS structure?

The driver actually doesn't need it at all, though a few ideas are
floating around for using it.

However, it's required by the hardware by definition -- you must
provide a buffer for incoming FIS's (P0FB), before enabling FIS
reception (P0CMD bit 4, FRE).

If I had to guess, the hardware dumps the RX FIS into host memory rather
than having additional internal buffers/FIFOs...

	Jeff

Re: FIS structure and Command List structure for AHCI SATA controller

[mike zheng]

Hi Jeff,

Actually I am using Marvell's 88SE6121 on kernel 2.4. I just wonder do
I have to enable the FIS? The SATA Command Table of the device have
following definitions:

00h Command FIS
40h ATAPI Command (CDB)
60h RSVD
80h Physical Region Descriptor Table

Does it mean I can only use FIS or ATAPI for this device?

Another confusion is the manual say that software should prepare the
command header, command FIS and the ATAPI command (CDB) for the ATAPI
command. Why it needs the FIS for ATAPI command?

Thanks for your help.

Mike

BTW, does anyone work on this device for kernel2.4?

On 11/8/07, Jeff Garzik <jeff@garzik.org> wrote:
> On Thu, Nov 08, 2007 at 10:38:25PM -0500, mike zheng wrote:
> > I am working on an AHCI SATA controller. For each port, there is one
> > FIS descriptor and one Command List, which points to a Received FIS
> > structure and Command List structure. So what is Received FIS
> > structure? The Command List structure points to Command Table, that
> > has Command FIS field and Physical Region Descriptor table. I assume
> > the Command table is used for the communication between processor and
> > the SATA controller. Then why do we need the Received FIS structure?
>
> The driver actually doesn't need it at all, though a few ideas are
> floating around for using it.
>
> However, it's required by the hardware by definition -- you must
> provide a buffer for incoming FIS's (P0FB), before enabling FIS
> reception (P0CMD bit 4, FRE).
>
> If I had to guess, the hardware dumps the RX FIS into host memory rather
> than having additional internal buffers/FIFOs...
>
>        Jeff
>
>
>
>

Re: FIS structure and Command List structure for AHCI SATA controller

[Jeff Garzik]

mike zheng wrote:
> Hi Jeff,
> 
> Actually I am using Marvell's 88SE6121 on kernel 2.4. I just wonder do
> I have to enable the FIS? The SATA Command Table of the device have
> following definitions:
> 
> 00h Command FIS
> 40h ATAPI Command (CDB)
> 60h RSVD
> 80h Physical Region Descriptor Table
> 
> Does it mean I can only use FIS or ATAPI for this device?
> 
> Another confusion is the manual say that software should prepare the
> command header, command FIS and the ATAPI command (CDB) for the ATAPI
> command. Why it needs the FIS for ATAPI command?
> 
> Thanks for your help.

FIS == basic data message used by all Serial ATA.

Both SATA ATA and SATA ATAPI use a FIS, it is fundamental to the nature 
of Serial ATA.

	Jeff

Re: FIS structure and Command List structure for AHCI SATA controller

[mike zheng]

Hi Jeff,

Does kernel2.4 support this chip (Marvell's 88SE6121)? I assume kernel
2.4 supports AHCI device. Is there any patch for this chip I may
apply? And which version of kernel2.4 shall I use?

Thanks for your help,

Mike

On 11/9/07, Jeff Garzik <jeff@garzik.org> wrote:
> mike zheng wrote:
> > Hi Jeff,
> >
> > Actually I am using Marvell's 88SE6121 on kernel 2.4. I just wonder do
> > I have to enable the FIS? The SATA Command Table of the device have
> > following definitions:
> >
> > 00h Command FIS
> > 40h ATAPI Command (CDB)
> > 60h RSVD
> > 80h Physical Region Descriptor Table
> >
> > Does it mean I can only use FIS or ATAPI for this device?
> >
> > Another confusion is the manual say that software should prepare the
> > command header, command FIS and the ATAPI command (CDB) for the ATAPI
> > command. Why it needs the FIS for ATAPI command?
> >
> > Thanks for your help.
>
> FIS == basic data message used by all Serial ATA.
>
> Both SATA ATA and SATA ATAPI use a FIS, it is fundamental to the nature
> of Serial ATA.
>
>        Jeff
>
>
>
>