From mboxrd@z Thu Jan 1 00:00:00 1970 From: Robert Hancock Subject: Re: sata_nv + ADMA + Samsung disk problem Date: Thu, 03 Jan 2008 19:43:39 -0600 Message-ID: <477D8F4B.6000601@shaw.ca> References: <20070808120804.GB5257@boogie.lpds.sztaki.hu> <20080101164416.GA29574@boogie.lpds.sztaki.hu> <477B0429.7040909@gmail.com> <477B0CFD.1030603@shaw.ca> <477BDEA5.8040701@garzik.org> <477C2A99.9010208@shaw.ca> <477C61D3.30009@rtr.ca> <477C6A85.9020607@shaw.ca> <477D02E0.5040301@rtr.ca> <477D039F.6000206@rtr.ca> <1199394786.7291.21.camel@pasglop> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: Received: from idcmail-mo1so.shaw.ca ([24.71.223.10]:45651 "EHLO pd3mo3so.prod.shaw.ca" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752813AbYADBnq (ORCPT ); Thu, 3 Jan 2008 20:43:46 -0500 In-reply-to: <1199394786.7291.21.camel@pasglop> Sender: linux-ide-owner@vger.kernel.org List-Id: linux-ide@vger.kernel.org To: benh@kernel.crashing.org Cc: Mark Lord , Allen Martin , Jeff Garzik , Tejun Heo , Gabor Gombas , linux-kernel@vger.kernel.org, linux-ide@vger.kernel.org, Kuan Luo , Peer Chen Benjamin Herrenschmidt wrote: >> Another thing about the PacDigi core: one has to be very careful >> to avoid sequential accesses to sequential PCI locations when >> programming the chip -- it cannot handle merged register writes. >> >> So for any group of sequentially laid out registers, the code has >> to ensure it never writes two adjacent registers in sequence.. > > Ugh ? Write combining isn't permitted on normal registers afaik... > > Ben. Byte merging can be done by the chipset on MMIO writes (merging multiple 8 or 16-bit writes into a single 32-bit cycle).