Re: [PATCH 1/2] ide: Add tx4939ide driver

[Sergei Shtylyov <sshtylyov@ru.mvista.com>]

Hello, I wrote:

> Thats wrong -- According t the spec. the bit should be set following 
> any assertion of INTRQ on IDE bus (possibly not at once though -- 
> after flushing FIFO). Well, no wonder with such description of the 
> bits as:
>
>
> INT_IDE (RWC) [Interrupt]
> Is “1” when data transfer completes. This bit is cleared by writing 
> “1” to it.
> When this bit is set to ‘1’, the following bits of the ATA Interrupt 
> Controller Register will be
> reset: bits [15:8] (Mask Address Error INT, Mask Reach Multiple INT, 
> Mask DEV
> Timing Error, Mask Ultra DMA DEV Terminate, Mask Timer INT, Mask Bus 
> Error, Mask
> Data Transfer End, Mask Host INT), and bits [1:0] (Data Transfer End, 
> Host INT).

   Forgot to mentiom that from this description it's not even clear if 
the int_ctl register bits are cleared when 1 is written to this bit or 
when the controller sets it. :-)

MBR, Sergei