From: Igor Plyatov <plyatov@gmail.com>
To: Stanislaw Gruszka <stf_xl@wp.pl>
Cc: linux-ide@vger.kernel.org
Subject: Re: [PATCH] ATA: pata_at91.c bugfixes
Date: Thu, 12 May 2011 16:03:40 +0400 [thread overview]
Message-ID: <4DCBCC9C.2040209@gmail.com> (raw)
In-Reply-To: <20110501211716.GA5217@localhost.localdomain>
Hello Stanislaw!
Thank you for patience and detailed explanations!
Sorry for long delays between answers, but I must work with another
projects.
>
>>>> * The NCS signal is not the same as CS1, CS2 ATA signals! It used only to
>>>> enable data bus transceiver U2.
>>> Well, they are different signals but connected together. All of these are
>>> controlled by NCS: CFCE1 (CS1), CFCE2 (CS2), CFRNW (DIR), CFCS0 (OE)
>>> if SMC is configured in True IDE mode.
>> I must repeat again - NCS ("CFCS1" from schematic) are completely
>> different signal for different purpose, then A0, A1, A2, CS0, CS1.
>> It used only to enable data bus transceiver U2.
> So, how in your opinion CS0 and CS1 are controlled? IMO there
> are delivered from CFCE1 and CFCE2, which itself are delivered
> from NCS. Here is corresponding quote from atmel documentation
> you cited above:
>
> "The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform"
This makes picture completely clean for me now.
I will publish new version patch for pata_at91.c.
Best regards!
--
Igor Plyatov
next prev parent reply other threads:[~2011-05-12 12:03 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-20 11:44 [PATCH] ATA: pata_at91.c bugfixes Igor Plyatov
2011-04-23 9:36 ` Stanislaw Gruszka
2011-04-26 6:38 ` Igor Plyatov
2011-04-27 18:38 ` Stanislaw Gruszka
2011-04-29 7:56 ` Stanisław Gruszka
[not found] ` <4DBA9E2F.3070100@gmail.com>
2011-05-01 21:17 ` Stanislaw Gruszka
2011-05-12 12:03 ` Igor Plyatov [this message]
2011-04-24 15:35 ` Jeff Garzik
2011-05-12 12:05 ` Igor Plyatov
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