* RE: New IDE driver for review [not found] <BFECAF9E178F144FAEF2BF4CE739C668030C7157@exmail1.se.axis.com> @ 2005-06-27 15:17 ` Mikael Starvik 2005-06-27 15:36 ` Bartlomiej Zolnierkiewicz 0 siblings, 1 reply; 9+ messages in thread From: Mikael Starvik @ 2005-06-27 15:17 UTC (permalink / raw) To: 'Bartlomiej Zolnierkiewicz', Mikael Starvik; +Cc: linux-ide [-- Attachment #1: Type: text/plain, Size: 7362 bytes --] Hi again! Great review comments, thanks! Fixed everything according to your remarks with the following comments: >previously there was a special case for IDE_STATUS_OFFSET here, >is it not needed any longer? That special case was for old crap disks but ok, I have readded the check just to be sure. >There is also number of changes w.r.t. v10 support: >* reset and initialization sequences are changed Yes, but that is ok >* "PIO comment" is gone Readded >* RESET_DMA()/WAIT_DMA() pairs are gone They were needed for the crap disks mentioned above, readded to be sure. >* 65536 sg size limit is gone Readded again with a new constant MAX_DESCR_SIZE. >* ->speedproc() method is added Yes, but that is a good thing. >It would make much sense to separate these changes from addition of v32 >support, this way testing for potential regressions would be much easier: I agree and will do that in the future. In this particular case it would require that I redo some of the work and tests so I would prefer a big patch in this case (that is, add the new file and remove the old). Updated file has been attached. /Mikael -----Original Message----- From: Bartlomiej Zolnierkiewicz [mailto:bzolnier@gmail.com] Sent: Monday, June 20, 2005 9:15 PM To: Mikael Starvik Cc: Mikael Starvik; linux-ide@vger.kernel.org Subject: Re: New IDE driver for review On 6/17/05, Mikael Starvik <mikael.starvik@axis.com> wrote: > Hi, Hi, > I have created a merged driver for CRIS v10 and v32. Do you think this > approach is better? In that case you'll also need a Makefile patch as > follows below. Looks much better. Thanks for doing this. Few comments: > void > cris_ide_outw(unsigned short data, unsigned long reg) { > int timeleft; > > LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg)); > > /* note the lack of handling any timeouts. we stop waiting, but we don't > * really notify anybody. > */ > > timeleft = IDE_REGISTER_TIMEOUT; > /* wait for busy flag */ > do { > timeleft--; > } while(timeleft && cris_ide_busy()); > > /* > * Fall through at a timeout, so the ongoing command will be > * aborted by the write below, which is expected to be a dummy > * command to the command register. This happens when a faulty > * drive times out on a command. See comment on timeout in > * INB. > */ > if(!timeleft) > printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data); > > cris_ide_write_command(reg|data); /* write data to the drive's register */ > > timeleft = IDE_REGISTER_TIMEOUT; > /* wait for transmitter ready */ > do { > timeleft--; > } while(timeleft && cris_ide_busy()); previously it was: while(timeleft && !(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy))) timeleft--; for v10, is it OK to use busy instead of tr_rdy? > } > unsigned short > cris_ide_inw(unsigned long reg) { > int timeleft; > unsigned short val; > > timeleft = IDE_REGISTER_TIMEOUT; > /* wait for busy flag */ > do { > timeleft--; > } while(timeleft && cris_ide_busy()); > > if(!timeleft) > return 0; previously there was a special case for IDE_STATUS_OFFSET here, is it not needed any longer? > cris_ide_write_command(reg | cris_pio_read); > > timeleft = IDE_REGISTER_TIMEOUT; > /* wait for available */ > do { > timeleft--; > } while(timeleft && !cris_ide_data_available(&val)); > > if(!timeleft) > return 0; > > LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg)); > > return val; > } > static void > cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) > { > D(printk("atapi_output_bytes, dreg 0x%x, buffer 0x%x, count %d\n", > 0, buffer, bytecount)); dreg? > if(bytecount & 1) { > printk("odd bytecount %d in atapi_out_bytes!\n", bytecount); > bytecount++; > } > > cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1); > cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount); > > /* wait for completion */ > > LED_DISK_WRITE(1); > LED_DISK_READ(1); > cris_ide_wait_dma(1); cris_ide_wait_dma(0) ? > LED_DISK_WRITE(0); > } > static int config_drive_for_dma (ide_drive_t *drive) > { > struct hd_driveid *id = drive->id; > > if (id && (id->capability & 1)) { > /* Enable DMA on any drive that supports mword2 DMA */ > if ((id->field_valid & 2) && > ((id->dma_mword & 0xff00) || (id->dma_ultra & 0xff00))) { no checking of (id->field_valid & 4) DMA will be used only if drive has it already enabled > drive->using_dma = 1; drive->using_dma shouldn't be touched at this layer > return 0; /* DMA enabled */ > } > } > drive->using_dma = 0; > return 0; /* DMA not enabled */ DMA whitelist/blacklist checking is missing > } should look more like: static int cris_config_drive_for_dma(ide_drive_t *drive) { u8 speed = ide_dma_speed(drive, 0); /* no UDMA for now */ if (!speed) return 0; speed_cris_ide(drive, speed); ide_config_drive_speed(drive, speed); return ide_dma_enable(drive); } > * For ATAPI devices, we just prepare for DMA and return. The caller should > * then issue the packet command to the drive and call us again with > * ide_dma_begin afterwards. this comment got re-introduced s/ide_dma_begin/->dma_start()/ > static int cris_dma_check(ide_drive_t *drive) > { > int speed = ide_dma_speed(drive, 0); /* No UDMA for now */ No UDMA? > speed_cris_ide(drive, speed); > ide_config_drive_speed(drive, speed); > return config_drive_for_dma (drive); > } should look more like: static int cris_dma_check(ide_drive_t *drive) { ide_hwif_t *hwif = drive->hwif; struct hd_driveid *id = drive->id; if (id && (id->capability & 1)) { if (ide_use_dma(drive) { if (cris_config_drive_for_dma(drive)) return hwif->ide_dma_on(drive); } } return hwif->ide_dma_off_quietly(drive); } > static int cris_prepare_dma(ide_drive_t *drive, int atapi, int reading) atapi and reading arguments are unused > { > struct request *rq = drive->hwif->hwgroup->rq; > if (cris_ide_build_dmatable (drive)) { > ide_map_sg(drive, rq); > return 1; > } > > return 0; > } > > static int cris_dma_setup(ide_drive_t *drive) > { > struct request *rq = drive->hwif->hwgroup->rq; > int ret; > if (rq_data_dir(rq)) > ret = cris_prepare_dma(drive, 0, 0); > else > ret = cris_prepare_dma(drive, 0, 1); > if (ret) > return ret; > drive->waiting_for_dma = 1; > return 0; > } should look more like: static int cris_dma_setup(ide_drive_t *drive) { struct request *rq = drive->hwif->hwgroup->rq; if (cris_ide_build_dmatable (drive)) { ide_map_sg(drive, rq); return 1; } drive->waiting_for_dma = 1; return 0; } cris_ide_reset() and cris_ide_init() should be marked with __init (for both archs) There is also number of changes w.r.t. v10 support: * reset and initialization sequences are changed * "PIO comment" is gone * RESET_DMA()/WAIT_DMA() pairs are gone * 65536 sg size limit is gone * ->speedproc() method is added * ... It would make much sense to separate these changes from addition of v32 support, this way testing for potential regressions would be much easier: 1. do v10 changes 2. add abstraction layer 3. add v32 support 4. rename driver One big patch is also fine with me as long as it is correct (IMHO it is easier to achieve correctness with a patch series). Cheers, Bartlomiej [-- Attachment #2: ide-cris.c --] [-- Type: application/octet-stream, Size: 30378 bytes --] /* $Id$ * * Etrax specific IDE functions, like init and PIO-mode setting etc. * Almost the entire ide.c is used for the rest of the Etrax ATA driver. * Copyright (c) 2000-2005 Axis Communications AB * * Authors: Bjorn Wesen (initial version) * Mikael Starvik (crisv32 port) */ /* Regarding DMA: * * There are two forms of DMA - "DMA handshaking" between the interface and the drive, * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's * something built-in in the Etrax. However only some drives support the DMA-mode handshaking * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the * device can't do DMA handshaking for some stupid reason. We don't need to do that. */ #undef REALLY_SLOW_IO /* most systems can safely undef this */ #include <linux/config.h> #include <linux/types.h> #include <linux/kernel.h> #include <linux/timer.h> #include <linux/mm.h> #include <linux/interrupt.h> #include <linux/delay.h> #include <linux/blkdev.h> #include <linux/hdreg.h> #include <linux/ide.h> #include <linux/init.h> #include <asm/io.h> #include <asm/dma.h> /* number of DMA descriptors */ #define MAX_DMA_DESCRS 64 /* number of times to retry busy-flags when reading/writing IDE-registers * this can't be too high because a hung harddisk might cause the watchdog * to trigger (sometimes INB and OUTB are called with irq's disabled) */ #define IDE_REGISTER_TIMEOUT 300 #define LOWDB(x) #define D(x) enum /* Transfer types */ { TYPE_PIO, TYPE_DMA, TYPE_UDMA }; /* CRISv32 specifics */ #ifdef CONFIG_ETRAX_ARCH_V32 #include <asm/arch/hwregs/ata_defs.h> #include <asm/arch/hwregs/dma_defs.h> #include <asm/arch/hwregs/dma.h> #include <asm/arch/pinmux.h> #define ATA_UDMA2_CYC 2 #define ATA_UDMA2_DVS 3 #define ATA_UDMA1_CYC 2 #define ATA_UDMA1_DVS 4 #define ATA_UDMA0_CYC 4 #define ATA_UDMA0_DVS 6 #define ATA_DMA2_STROBE 7 #define ATA_DMA2_HOLD 1 #define ATA_DMA1_STROBE 8 #define ATA_DMA1_HOLD 3 #define ATA_DMA0_STROBE 25 #define ATA_DMA0_HOLD 19 #define ATA_PIO4_SETUP 3 #define ATA_PIO4_STROBE 7 #define ATA_PIO4_HOLD 1 #define ATA_PIO3_SETUP 3 #define ATA_PIO3_STROBE 9 #define ATA_PIO3_HOLD 3 #define ATA_PIO2_SETUP 3 #define ATA_PIO2_STROBE 13 #define ATA_PIO2_HOLD 5 #define ATA_PIO1_SETUP 5 #define ATA_PIO1_STROBE 23 #define ATA_PIO1_HOLD 9 #define ATA_PIO0_SETUP 9 #define ATA_PIO0_STROBE 39 #define ATA_PIO0_HOLD 9 int cris_ide_ack_intr(ide_hwif_t* hwif) { reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, hwif->io_ports[0]); REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel); return 1; } static inline int cris_ide_busy(void) { reg_ata_rs_stat_data stat_data; stat_data = REG_RD(ata, regi_ata, rs_stat_data); return stat_data.busy; } static inline int cris_ide_ready(void) { return !cris_ide_busy(); } static inline int cris_ide_data_available(unsigned short* data) { reg_ata_rs_stat_data stat_data; stat_data = REG_RD(ata, regi_ata, rs_stat_data); *data = stat_data.data; return stat_data.dav; } static void cris_ide_write_command(unsigned long command) { REG_WR_INT(ata, regi_ata, rw_ctrl2, command); /* write data to the drive's register */ } static void cris_ide_set_speed(int type, int setup, int strobe, int hold) { reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1); if (type == TYPE_PIO) { ctrl0.pio_setup = setup; ctrl0.pio_strb = strobe; ctrl0.pio_hold = hold; } else if (type == TYPE_DMA) { ctrl0.dma_strb = strobe; ctrl0.dma_hold = hold; } else if (type == TYPE_UDMA) { ctrl1.udma_tcyc = setup; ctrl1.udma_tdvs = strobe; } REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); REG_WR(ata, regi_ata, rw_ctrl1, ctrl1); } static unsigned long cris_ide_base_address(int bus) { reg_ata_rw_ctrl2 ctrl2 = {0}; ctrl2.sel = bus; return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2); } static unsigned long cris_ide_reg_addr(unsigned long addr, int cs0, int cs1) { reg_ata_rw_ctrl2 ctrl2 = {0}; ctrl2.addr = addr; ctrl2.cs1 = cs1; ctrl2.cs0 = cs0; return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2); } static __init void cris_ide_reset(unsigned val) { reg_ata_rw_ctrl0 ctrl0 = {0}; ctrl0.rst = val ? regk_ata_active : regk_ata_inactive; REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); } static __init void cris_ide_init(void) { reg_ata_rw_ctrl0 ctrl0 = {0}; reg_ata_rw_intr_mask intr_mask = {0}; ctrl0.en = regk_ata_yes; REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); intr_mask.bus0 = regk_ata_yes; intr_mask.bus1 = regk_ata_yes; intr_mask.bus2 = regk_ata_yes; intr_mask.bus3 = regk_ata_yes; REG_WR(ata, regi_ata, rw_intr_mask, intr_mask); crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata); crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata); crisv32_pinmux_alloc_fixed(pinmux_ata); crisv32_pinmux_alloc_fixed(pinmux_ata0); crisv32_pinmux_alloc_fixed(pinmux_ata1); crisv32_pinmux_alloc_fixed(pinmux_ata2); crisv32_pinmux_alloc_fixed(pinmux_ata3); DMA_RESET(regi_dma2); DMA_ENABLE(regi_dma2); DMA_RESET(regi_dma3); DMA_ENABLE(regi_dma3); DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2); DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2); } static dma_descr_context mycontext __attribute__ ((__aligned__(32))); #define cris_dma_descr_type dma_descr_data #define cris_pio_read regk_ata_rd #define cris_ultra_mask 0x7 #define MAX_DESCR_SIZE 0xffffffffUL static unsigned long cris_ide_get_reg(unsigned long reg) { return (reg & 0x0e000000) >> 25; } static void cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last) { d->buf = (char*)virt_to_phys(buf); d->after = d->buf + len; d->eol = last; } static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,int len) { reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG); reg_ata_rw_trf_cnt trf_cnt = {0}; mycontext.saved_data = (dma_descr_data*)virt_to_phys(d); mycontext.saved_data_buf = d->buf; /* start the dma channel */ DMA_START_CONTEXT(dir ? regi_dma3 : regi_dma2, virt_to_phys(&mycontext)); /* initiate a multi word dma read using PIO handshaking */ trf_cnt.cnt = len >> 1; /* Due to a "feature" the transfer count has to be one extra word for UDMA. */ if (type == TYPE_UDMA) trf_cnt.cnt++; REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt); ctrl2.rw = dir ? regk_ata_rd : regk_ata_wr; ctrl2.trf_mode = regk_ata_dma; ctrl2.hsh = type == TYPE_PIO ? regk_ata_pio : type == TYPE_DMA ? regk_ata_dma : regk_ata_udma; ctrl2.multi = regk_ata_yes; ctrl2.dma_size = regk_ata_word; REG_WR(ata, regi_ata, rw_ctrl2, ctrl2); } static void cris_ide_wait_dma(int dir) { reg_dma_rw_stat status; do { status = REG_RD(dma, dir ? regi_dma3 : regi_dma2, rw_stat); } while(status.list_state != regk_dma_data_at_eol); } static int cris_dma_test_irq(ide_drive_t *drive) { int intr = REG_RD_INT(ata, regi_ata, r_intr); reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG); return intr & (1 << ctrl2.sel) ? 1 : 0; } static void cris_ide_initialize_dma(int dir) { } #else /* CRISv10 specifics */ #include <asm/arch/svinto.h> #include <asm/arch/io_interface_mux.h> /* PIO timing (in R_ATA_CONFIG) * * _____________________________ * ADDRESS : ________/ * * _______________ * DIOR : ____________/ \__________ * * _______________ * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX * * * DIOR is unbuffered while address and data is buffered. * This creates two problems: * 1. The DIOR pulse is to early (because it is unbuffered) * 2. The rise time of DIOR is long * * There are at least three different plausible solutions * 1. Use a pad capable of larger currents in Etrax * 2. Use an external buffer * 3. Make the strobe pulse longer * * Some of the strobe timings below are modified to compensate * for this. This implies a slight performance decrease. * * THIS SHOULD NEVER BE CHANGED! * * TODO: Is this true for the latest LX boards still ? */ #define ATA_UDMA2_CYC 0 /* No UDMA supported, just to make it compile. */ #define ATA_UDMA2_DVS 0 #define ATA_UDMA1_CYC 0 #define ATA_UDMA1_DVS 0 #define ATA_UDMA0_CYC 0 #define ATA_UDMA0_DVS 0 #define ATA_DMA2_STROBE 4 #define ATA_DMA2_HOLD 0 #define ATA_DMA1_STROBE 4 #define ATA_DMA1_HOLD 1 #define ATA_DMA0_STROBE 12 #define ATA_DMA0_HOLD 9 #define ATA_PIO4_SETUP 1 #define ATA_PIO4_STROBE 5 #define ATA_PIO4_HOLD 0 #define ATA_PIO3_SETUP 1 #define ATA_PIO3_STROBE 5 #define ATA_PIO3_HOLD 1 #define ATA_PIO2_SETUP 1 #define ATA_PIO2_STROBE 6 #define ATA_PIO2_HOLD 2 #define ATA_PIO1_SETUP 2 #define ATA_PIO1_STROBE 11 #define ATA_PIO1_HOLD 4 #define ATA_PIO0_SETUP 4 #define ATA_PIO0_STROBE 19 #define ATA_PIO0_HOLD 4 int cris_ide_ack_intr(ide_hwif_t* hwif) { return 1; } static inline int cris_ide_busy(void) { return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy) ; } static inline int cris_ide_ready(void) { return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy) ; } static inline int cris_ide_data_available(unsigned short* data) { unsigned long status = *R_ATA_STATUS_DATA; *data = (unsigned short)status; return status & IO_MASK(R_ATA_STATUS_DATA, dav); } static void cris_ide_write_command(unsigned long command) { *R_ATA_CTRL_DATA = command; } static void cris_ide_set_speed(int type, int setup, int strobe, int hold) { static int pio_setup = ATA_PIO4_SETUP; static int pio_strobe = ATA_PIO4_STROBE; static int pio_hold = ATA_PIO4_HOLD; static int dma_strobe = ATA_DMA2_STROBE; static int dma_hold = ATA_DMA2_HOLD; if (type == TYPE_PIO) { pio_setup = setup; pio_strobe = strobe; pio_hold = hold; } else if (type == TYPE_DMA) { dma_strobe = strobe; dma_hold = hold; } *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | IO_FIELD( R_ATA_CONFIG, dma_strobe, dma_strobe ) | IO_FIELD( R_ATA_CONFIG, dma_hold, dma_hold ) | IO_FIELD( R_ATA_CONFIG, pio_setup, pio_setup ) | IO_FIELD( R_ATA_CONFIG, pio_strobe, pio_strobe ) | IO_FIELD( R_ATA_CONFIG, pio_hold, pio_hold ) ); } static unsigned long cris_ide_base_address(int bus) { return IO_FIELD(R_ATA_CTRL_DATA, sel, bus); } static unsigned long cris_ide_reg_addr(unsigned long addr, int cs0, int cs1) { return IO_FIELD(R_ATA_CTRL_DATA, addr, addr) | IO_FIELD(R_ATA_CTRL_DATA, cs0, cs0) | IO_FIELD(R_ATA_CTRL_DATA, cs1, cs1); } static __init void cris_ide_reset(unsigned val) { #ifdef CONFIG_ETRAX_IDE_G27_RESET REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, val); #endif #ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, val); #endif #ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, val); #endif #ifdef CONFIG_ETRAX_IDE_PB7_RESET port_pb_dir_shadow = port_pb_dir_shadow | IO_STATE(R_PORT_PB_DIR, dir7, output); *R_PORT_PB_DIR = port_pb_dir_shadow; REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, val); #endif } static __init void cris_ide_init(void) { volatile unsigned int dummy; *R_ATA_CTRL_DATA = 0; *R_ATA_TRANSFER_CNT = 0; *R_ATA_CONFIG = 0; if (cris_request_io_interface(if_ata, "ETRAX100LX IDE")) { printk(KERN_CRIT "ide: Failed to get IO interface\n"); return; } else if (cris_request_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE TX", DMA_VERBOSE_ON_ERROR, dma_ata)) { cris_free_io_interface(if_ata); printk(KERN_CRIT "ide: Failed to get Tx DMA channel\n"); return; } else if (cris_request_dma(ATA_RX_DMA_NBR, "ETRAX100LX IDE RX", DMA_VERBOSE_ON_ERROR, dma_ata)) { cris_free_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE Tx"); cris_free_io_interface(if_ata); printk(KERN_CRIT "ide: Failed to get Rx DMA channel\n"); return; } /* make a dummy read to set the ata controller in a proper state */ dummy = *R_ATA_STATUS_DATA; *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 )); *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) | IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) ); while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/ *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) | IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) | IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) | IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) ); /* reset the dma channels we will use */ RESET_DMA(ATA_TX_DMA_NBR); RESET_DMA(ATA_RX_DMA_NBR); WAIT_DMA(ATA_TX_DMA_NBR); WAIT_DMA(ATA_RX_DMA_NBR); } #define cris_dma_descr_type etrax_dma_descr #define cris_pio_read IO_STATE(R_ATA_CTRL_DATA, rw, read) #define cris_ultra_mask 0x0 #define MAX_DESCR_SIZE 0x10000UL static unsigned long cris_ide_get_reg(unsigned long reg) { return (reg & 0x0e000000) >> 25; } static void cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last) { d->buf = virt_to_phys(buf); d->sw_len = len == MAX_DESCR_SIZE ? 0 : len; if (last) d->ctrl |= d_eol; } static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir, int type, int len) { unsigned long cmd; if (dir) { /* need to do this before RX DMA due to a chip bug * it is enough to just flush the part of the cache that * corresponds to the buffers we start, but since HD transfers * usually are more than 8 kB, it is easier to optimize for the * normal case and just flush the entire cache. its the only * way to be sure! (OB movie quote) */ flush_etrax_cache(); *R_DMA_CH3_FIRST = virt_to_phys(d); *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start); } else { *R_DMA_CH2_FIRST = virt_to_phys(d); *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start); } /* initiate a multi word dma read using DMA handshaking */ *R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, len >> 1); cmd = dir ? IO_STATE(R_ATA_CTRL_DATA, rw, read) : IO_STATE(R_ATA_CTRL_DATA, rw, write); cmd |= type == TYPE_PIO ? IO_STATE(R_ATA_CTRL_DATA, handsh, pio) : IO_STATE(R_ATA_CTRL_DATA, handsh, dma); *R_ATA_CTRL_DATA = cmd | IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) | IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) | IO_STATE(R_ATA_CTRL_DATA, multi, on) | IO_STATE(R_ATA_CTRL_DATA, dma_size, word); } static void cris_ide_wait_dma(int dir) { if (dir) WAIT_DMA(ATA_RX_DMA_NBR); else WAIT_DMA(ATA_TX_DMA_NBR); } static int cris_dma_test_irq(ide_drive_t *drive) { int intr = *R_IRQ_MASK0_RD; int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel, IDE_DATA_REG); return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0; } static void cris_ide_initialize_dma(int dir) { if (dir) { RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */ WAIT_DMA(ATA_RX_DMA_NBR); } else { RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */ WAIT_DMA(ATA_TX_DMA_NBR); } } #endif void cris_ide_outw(unsigned short data, unsigned long reg) { int timeleft; LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg)); /* note the lack of handling any timeouts. we stop waiting, but we don't * really notify anybody. */ timeleft = IDE_REGISTER_TIMEOUT; /* wait for busy flag */ do { timeleft--; } while(timeleft && cris_ide_busy()); /* * Fall through at a timeout, so the ongoing command will be * aborted by the write below, which is expected to be a dummy * command to the command register. This happens when a faulty * drive times out on a command. See comment on timeout in * INB. */ if(!timeleft) printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data); cris_ide_write_command(reg|data); /* write data to the drive's register */ timeleft = IDE_REGISTER_TIMEOUT; /* wait for transmitter ready */ do { timeleft--; } while(timeleft && !cris_ide_ready()); } void cris_ide_outb(unsigned char data, unsigned long reg) { cris_ide_outw(data, reg); } void cris_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port) { cris_ide_outw(addr, port); } unsigned short cris_ide_inw(unsigned long reg) { int timeleft; unsigned short val; timeleft = IDE_REGISTER_TIMEOUT; /* wait for busy flag */ do { timeleft--; } while(timeleft && cris_ide_busy()); if(!timeleft) { /* * If we're asked to read the status register, like for * example when a command does not complete for an * extended time, but the ATA interface is stuck in a * busy state at the *ETRAX* ATA interface level (as has * happened repeatedly with at least one bad disk), then * the best thing to do is to pretend that we read * "busy" in the status register, so the IDE driver will * time-out, abort the ongoing command and perform a * reset sequence. Note that the subsequent OUT_BYTE * call will also timeout on busy, but as long as the * write is still performed, everything will be fine. */ if (cris_ide_get_reg(reg) == IDE_STATUS_OFFSET) return BUSY_STAT; else /* For other rare cases we assume 0 is good enough. */ return 0; } cris_ide_write_command(reg | cris_pio_read); timeleft = IDE_REGISTER_TIMEOUT; /* wait for available */ do { timeleft--; } while(timeleft && !cris_ide_data_available(&val)); if(!timeleft) return 0; LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg)); return val; } unsigned char cris_ide_inb(unsigned long reg) { return (unsigned char)cris_ide_inw(reg); } static int cris_dma_check (ide_drive_t *drive); static int cris_dma_end (ide_drive_t *drive); static int cris_dma_setup (ide_drive_t *drive); static void cris_dma_exec_cmd (ide_drive_t *drive, u8 command); static int cris_dma_test_irq(ide_drive_t *drive); static void cris_dma_start(ide_drive_t *drive); static void cris_ide_input_data (ide_drive_t *drive, void *, unsigned int); static void cris_ide_output_data (ide_drive_t *drive, void *, unsigned int); static void cris_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int); static void cris_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int); static int cris_dma_off (ide_drive_t *drive); static int cris_dma_on (ide_drive_t *drive); static void tune_cris_ide(ide_drive_t *drive, u8 pio) { int setup, strobe, hold; switch(pio) { case 0: setup = ATA_PIO0_SETUP; strobe = ATA_PIO0_STROBE; hold = ATA_PIO0_HOLD; break; case 1: setup = ATA_PIO1_SETUP; strobe = ATA_PIO1_STROBE; hold = ATA_PIO1_HOLD; break; case 2: setup = ATA_PIO2_SETUP; strobe = ATA_PIO2_STROBE; hold = ATA_PIO2_HOLD; break; case 3: setup = ATA_PIO3_SETUP; strobe = ATA_PIO3_STROBE; hold = ATA_PIO3_HOLD; break; case 4: setup = ATA_PIO4_SETUP; strobe = ATA_PIO4_STROBE; hold = ATA_PIO4_HOLD; break; default: return; } cris_ide_set_speed(TYPE_PIO, setup, strobe, hold); } static int speed_cris_ide(ide_drive_t *drive, u8 speed) { int cyc = 0, dvs = 0, strobe = 0, hold = 0; if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) { tune_cris_ide(drive, speed - XFER_PIO_0); return 0; } switch(speed) { case XFER_UDMA_0: cyc = ATA_UDMA0_CYC; dvs = ATA_UDMA0_DVS; break; case XFER_UDMA_1: cyc = ATA_UDMA1_CYC; dvs = ATA_UDMA1_DVS; break; case XFER_UDMA_2: cyc = ATA_UDMA2_CYC; dvs = ATA_UDMA2_DVS; break; case XFER_MW_DMA_0: strobe = ATA_DMA0_STROBE; hold = ATA_DMA0_HOLD; break; case XFER_MW_DMA_1: strobe = ATA_DMA1_STROBE; hold = ATA_DMA1_HOLD; break; case XFER_MW_DMA_2: strobe = ATA_DMA2_STROBE; hold = ATA_DMA2_HOLD; break; default: return 0; } if (speed >= XFER_UDMA_0) cris_ide_set_speed(TYPE_UDMA, cyc, dvs, 0); else cris_ide_set_speed(TYPE_DMA, 0, strobe, hold); return 0; } void __init init_e100_ide (void) { hw_regs_t hw; int ide_offsets[IDE_NR_PORTS]; int h; int i; printk("ide: ETRAX FS built-in ATA DMA controller\n"); for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) ide_offsets[i] = cris_ide_reg_addr(i, 0, 1); /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */ ide_offsets[IDE_CONTROL_OFFSET] = cris_ide_reg_addr(6, 1, 0); /* first fill in some stuff in the ide_hwifs fields */ for(h = 0; h < MAX_HWIFS; h++) { ide_hwif_t *hwif = &ide_hwifs[h]; ide_setup_ports(&hw, cris_ide_base_address(h), ide_offsets, 0, 0, cris_ide_ack_intr, ide_default_irq(0)); ide_register_hw(&hw, &hwif); hwif->mmio = 2; hwif->chipset = ide_etrax100; hwif->tuneproc = &tune_cris_ide; hwif->speedproc = &speed_cris_ide; hwif->ata_input_data = &cris_ide_input_data; hwif->ata_output_data = &cris_ide_output_data; hwif->atapi_input_bytes = &cris_atapi_input_bytes; hwif->atapi_output_bytes = &cris_atapi_output_bytes; hwif->ide_dma_check = &cris_dma_check; hwif->ide_dma_end = &cris_dma_end; hwif->dma_setup = &cris_dma_setup; hwif->dma_exec_cmd = &cris_dma_exec_cmd; hwif->ide_dma_test_irq = &cris_dma_test_irq; hwif->dma_start = &cris_dma_start; hwif->OUTB = &cris_ide_outb; hwif->OUTW = &cris_ide_outw; hwif->OUTBSYNC = &cris_ide_outbsync; hwif->INB = &cris_ide_inb; hwif->INW = &cris_ide_inw; hwif->ide_dma_host_off = &cris_dma_off; hwif->ide_dma_host_on = &cris_dma_on; hwif->ide_dma_off_quietly = &cris_dma_off; hwif->udma_four = 0; hwif->ultra_mask = cris_ultra_mask; hwif->mwdma_mask = 0x07; /* Multiword DMA 0-2 */ hwif->swdma_mask = 0x07; /* Singleword DMA 0-2 */ } /* Reset pulse */ cris_ide_reset(0); udelay(25); cris_ide_reset(1); cris_ide_init(); cris_ide_set_speed(TYPE_PIO, ATA_PIO4_SETUP, ATA_PIO4_STROBE, ATA_PIO4_HOLD); cris_ide_set_speed(TYPE_DMA, 0, ATA_DMA2_STROBE, ATA_DMA2_HOLD); cris_ide_set_speed(TYPE_UDMA, ATA_UDMA2_CYC, ATA_UDMA2_DVS, 0); } static int cris_dma_off (ide_drive_t *drive) { return 0; } static int cris_dma_on (ide_drive_t *drive) { return 0; } static cris_dma_descr_type mydescr __attribute__ ((__aligned__(16))); /* * The following routines are mainly used by the ATAPI drivers. * * These routines will round up any request for an odd number of bytes, * so if an odd bytecount is specified, be sure that there's at least one * extra byte allocated for the buffer. */ static void cris_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) { D(printk("atapi_input_bytes, buffer 0x%x, count %d\n", buffer, bytecount)); if(bytecount & 1) { printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount); bytecount++; /* to round off */ } /* setup DMA and start transfer */ cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1); cris_ide_start_dma(drive, &mydescr, 1, TYPE_PIO, bytecount); /* wait for completion */ LED_DISK_READ(1); cris_ide_wait_dma(1); LED_DISK_READ(0); } static void cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) { D(printk("atapi_output_bytes, buffer 0x%x, count %d\n", buffer, bytecount)); if(bytecount & 1) { printk("odd bytecount %d in atapi_out_bytes!\n", bytecount); bytecount++; } cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1); cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount); /* wait for completion */ LED_DISK_WRITE(1); LED_DISK_READ(1); cris_ide_wait_dma(0); LED_DISK_WRITE(0); } /* * This is used for most PIO data transfers *from* the IDE interface */ static void cris_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount) { cris_atapi_input_bytes(drive, buffer, wcount << 2); } /* * This is used for most PIO data transfers *to* the IDE interface */ static void cris_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount) { cris_atapi_output_bytes(drive, buffer, wcount << 2); } /* we only have one DMA channel on the chip for ATA, so we can keep these statically */ static cris_dma_descr_type ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16))); static unsigned int ata_tot_size; /* * cris_ide_build_dmatable() prepares a dma request. * Returns 0 if all went okay, returns 1 otherwise. */ static int cris_ide_build_dmatable (ide_drive_t *drive) { ide_hwif_t *hwif = drive->hwif; struct scatterlist* sg; struct request *rq = drive->hwif->hwgroup->rq; unsigned long size, addr; unsigned int count = 0; int i = 0; sg = hwif->sg_table; ata_tot_size = 0; ide_map_sg(drive, rq); i = hwif->sg_nents; while(i) { /* * Determine addr and size of next buffer area. We assume that * individual virtual buffers are always composed linearly in * physical memory. For example, we assume that any 8kB buffer * is always composed of two adjacent physical 4kB pages rather * than two possibly non-adjacent physical 4kB pages. */ /* group sequential buffers into one large buffer */ addr = page_to_phys(sg->page) + sg->offset; size = sg_dma_len(sg); while (sg++, --i) { if ((addr + size) != page_to_phys(sg->page) + sg->offset) break; size += sg_dma_len(sg); } /* did we run out of descriptors? */ if(count >= MAX_DMA_DESCRS) { printk("%s: too few DMA descriptors\n", drive->name); return 1; } /* however, this case is more difficult - rw_trf_cnt cannot be more than 65536 words per transfer, so in that case we need to either 1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with the descriptors, or 2) simply do the request here, and get dma_intr to only ide_end_request on those blocks that were actually set-up for transfer. */ if(ata_tot_size + size > 131072) { printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size); return 1; } /* If size > MAX_DESCR_SIZE it has to be splitted into new descriptors. Since we don't handle size > 131072 only one split is necessary */ if(size > MAX_DESCR_SIZE) { cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, MAX_DESCR_SIZE, 0); count++; ata_tot_size += MAX_DESCR_SIZE; size -= MAX_DESCR_SIZE; addr += MAX_DESCR_SIZE; } cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, size,i ? 0 : 1); count++; ata_tot_size += size; } if (count) { /* return and say all is ok */ return 0; } printk("%s: empty DMA table?\n", drive->name); return 1; /* let the PIO routines handle this weirdness */ } static int cris_config_drive_for_dma (ide_drive_t *drive) { u8 speed = ide_dma_speed(drive, 1); if (!speed) return 0; speed_cris_ide(drive, speed); ide_config_drive_speed(drive, speed); return ide_dma_enable(drive); } /* * cris_dma_intr() is the handler for disk read/write DMA interrupts */ static ide_startstop_t cris_dma_intr (ide_drive_t *drive) { LED_DISK_READ(0); LED_DISK_WRITE(0); return ide_dma_intr(drive); } /* * Functions below initiates/aborts DMA read/write operations on a drive. * * The caller is assumed to have selected the drive and programmed the drive's * sector address using CHS or LBA. All that remains is to prepare for DMA * and then issue the actual read/write DMA/PIO command to the drive. * * For ATAPI devices, we just prepare for DMA and return. The caller should * then issue the packet command to the drive and call us again with * cris_dma_start afterwards. * * Returns 0 if all went well. * Returns 1 if DMA read/write could not be started, in which case * the caller should revert to PIO for the current request. */ static int cris_dma_check(ide_drive_t *drive) { ide_hwif_t *hwif = drive->hwif; struct hd_driveid* id = drive->id; if (id && (id->capability & 1)) { if (ide_use_dma(drive)) { if (cris_config_drive_for_dma(drive)) return hwif->ide_dma_on(drive); } } return hwif->ide_dma_off_quietly(drive); } static int cris_dma_end(ide_drive_t *drive) { drive->waiting_for_dma = 0; return 0; } static int cris_dma_setup(ide_drive_t *drive) { struct request *rq = drive->hwif->hwgroup->rq; cris_ide_initialize_dma(!rq_data_dir(rq)); if (cris_ide_build_dmatable (drive)) { ide_map_sg(drive, rq); return 1; } drive->waiting_for_dma = 1; return 0; } static void cris_dma_exec_cmd(ide_drive_t *drive, u8 command) { /* set the irq handler which will finish the request when DMA is done */ ide_set_handler(drive, &cris_dma_intr, WAIT_CMD, NULL); /* issue cmd to drive */ cris_ide_outb(command, IDE_COMMAND_REG); } static void cris_dma_start(ide_drive_t *drive) { struct request *rq = drive->hwif->hwgroup->rq; int writing = rq_data_dir(rq); int type = TYPE_DMA; if (drive->current_speed >= XFER_UDMA_0) type = TYPE_UDMA; cris_ide_start_dma(drive, &ata_descrs[0], writing ? 0 : 1, type, ata_tot_size); if (writing) { LED_DISK_WRITE(1); } else { LED_DISK_READ(1); } } ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: New IDE driver for review 2005-06-27 15:17 ` New IDE driver for review Mikael Starvik @ 2005-06-27 15:36 ` Bartlomiej Zolnierkiewicz 0 siblings, 0 replies; 9+ messages in thread From: Bartlomiej Zolnierkiewicz @ 2005-06-27 15:36 UTC (permalink / raw) To: Mikael Starvik; +Cc: Mikael Starvik, linux-ide Hi! Looks fine. Thanks for fixing it. I think that the best way to push this driver is through Andrew Morton with the rest of cris-v32 changes. Acked-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Cheers, Bartlomiej On 6/27/05, Mikael Starvik <mikael.starvik@axis.com> wrote: > Hi again! > > Great review comments, thanks! Fixed everything according to your remarks > with the following comments: > > >previously there was a special case for IDE_STATUS_OFFSET here, > >is it not needed any longer? > > That special case was for old crap disks but ok, I have readded the > check just to be sure. > > >There is also number of changes w.r.t. v10 support: > >* reset and initialization sequences are changed > > Yes, but that is ok > > >* "PIO comment" is gone > > Readded > > >* RESET_DMA()/WAIT_DMA() pairs are gone > > They were needed for the crap disks mentioned above, readded to be sure. > > >* 65536 sg size limit is gone > > Readded again with a new constant MAX_DESCR_SIZE. > > >* ->speedproc() method is added > > Yes, but that is a good thing. > > >It would make much sense to separate these changes from addition of v32 > >support, this way testing for potential regressions would be much easier: > > I agree and will do that in the future. In this particular case it would > require that I redo some of the work and tests so I would prefer a big > patch in this case (that is, add the new file and remove the old). > > Updated file has been attached. > > /Mikael > > -----Original Message----- > From: Bartlomiej Zolnierkiewicz [mailto:bzolnier@gmail.com] > Sent: Monday, June 20, 2005 9:15 PM > To: Mikael Starvik > Cc: Mikael Starvik; linux-ide@vger.kernel.org > Subject: Re: New IDE driver for review > > > On 6/17/05, Mikael Starvik <mikael.starvik@axis.com> wrote: > > Hi, > > Hi, > > > I have created a merged driver for CRIS v10 and v32. Do you think this > > approach is better? In that case you'll also need a Makefile patch as > > follows below. > > Looks much better. Thanks for doing this. > > Few comments: > > > void > > cris_ide_outw(unsigned short data, unsigned long reg) { > > int timeleft; > > > > LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg)); > > > > /* note the lack of handling any timeouts. we stop waiting, but we > don't > > * really notify anybody. > > */ > > > > timeleft = IDE_REGISTER_TIMEOUT; > > /* wait for busy flag */ > > do { > > timeleft--; > > } while(timeleft && cris_ide_busy()); > > > > /* > > * Fall through at a timeout, so the ongoing command will be > > * aborted by the write below, which is expected to be a dummy > > * command to the command register. This happens when a faulty > > * drive times out on a command. See comment on timeout in > > * INB. > > */ > > if(!timeleft) > > printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data); > > > > cris_ide_write_command(reg|data); /* write data to the drive's > register */ > > > > timeleft = IDE_REGISTER_TIMEOUT; > > /* wait for transmitter ready */ > > do { > > timeleft--; > > } while(timeleft && cris_ide_busy()); > > previously it was: > > while(timeleft && !(*R_ATA_STATUS_DATA & > IO_MASK(R_ATA_STATUS_DATA, tr_rdy))) > timeleft--; > > for v10, is it OK to use busy instead of tr_rdy? > > > } > > > unsigned short > > cris_ide_inw(unsigned long reg) { > > int timeleft; > > unsigned short val; > > > > timeleft = IDE_REGISTER_TIMEOUT; > > /* wait for busy flag */ > > do { > > timeleft--; > > } while(timeleft && cris_ide_busy()); > > > > if(!timeleft) > > return 0; > > previously there was a special case for IDE_STATUS_OFFSET here, > is it not needed any longer? > > > cris_ide_write_command(reg | cris_pio_read); > > > > timeleft = IDE_REGISTER_TIMEOUT; > > /* wait for available */ > > do { > > timeleft--; > > } while(timeleft && !cris_ide_data_available(&val)); > > > > if(!timeleft) > > return 0; > > > > LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg)); > > > > return val; > > } > > > static void > > cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int > bytecount) > > { > > D(printk("atapi_output_bytes, dreg 0x%x, buffer 0x%x, count %d\n", > > 0, buffer, bytecount)); > > dreg? > > > if(bytecount & 1) { > > printk("odd bytecount %d in atapi_out_bytes!\n", bytecount); > > bytecount++; > > } > > > > cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1); > > cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount); > > > > /* wait for completion */ > > > > LED_DISK_WRITE(1); > > LED_DISK_READ(1); > > cris_ide_wait_dma(1); > > cris_ide_wait_dma(0) ? > > > LED_DISK_WRITE(0); > > } > > > static int config_drive_for_dma (ide_drive_t *drive) > > { > > struct hd_driveid *id = drive->id; > > > > if (id && (id->capability & 1)) { > > /* Enable DMA on any drive that supports mword2 DMA */ > > if ((id->field_valid & 2) && > > ((id->dma_mword & 0xff00) || (id->dma_ultra & 0xff00))) > { > > no checking of (id->field_valid & 4) > > DMA will be used only if drive has it already enabled > > > drive->using_dma = 1; > > drive->using_dma shouldn't be touched at this layer > > > return 0; /* DMA enabled */ > > } > > } > > drive->using_dma = 0; > > return 0; /* DMA not enabled */ > > DMA whitelist/blacklist checking is missing > > > } > > should look more like: > > static int cris_config_drive_for_dma(ide_drive_t *drive) > { > u8 speed = ide_dma_speed(drive, 0); /* no UDMA for now */ > > if (!speed) > return 0; > > speed_cris_ide(drive, speed); > ide_config_drive_speed(drive, speed); > > return ide_dma_enable(drive); > } > > > * For ATAPI devices, we just prepare for DMA and return. The caller > should > > * then issue the packet command to the drive and call us again with > > * ide_dma_begin afterwards. > > this comment got re-introduced > s/ide_dma_begin/->dma_start()/ > > > static int cris_dma_check(ide_drive_t *drive) > > { > > int speed = ide_dma_speed(drive, 0); /* No UDMA for now */ > > No UDMA? > > > speed_cris_ide(drive, speed); > > ide_config_drive_speed(drive, speed); > > return config_drive_for_dma (drive); > > } > > should look more like: > > static int cris_dma_check(ide_drive_t *drive) > { > ide_hwif_t *hwif = drive->hwif; > struct hd_driveid *id = drive->id; > > if (id && (id->capability & 1)) { > if (ide_use_dma(drive) { > if (cris_config_drive_for_dma(drive)) > return hwif->ide_dma_on(drive); > } > } > > return hwif->ide_dma_off_quietly(drive); > } > > > static int cris_prepare_dma(ide_drive_t *drive, int atapi, int reading) > > atapi and reading arguments are unused > > > { > > struct request *rq = drive->hwif->hwgroup->rq; > > if (cris_ide_build_dmatable (drive)) { > > ide_map_sg(drive, rq); > > return 1; > > } > > > > return 0; > > } > > > > static int cris_dma_setup(ide_drive_t *drive) > > { > > struct request *rq = drive->hwif->hwgroup->rq; > > int ret; > > if (rq_data_dir(rq)) > > ret = cris_prepare_dma(drive, 0, 0); > > else > > ret = cris_prepare_dma(drive, 0, 1); > > if (ret) > > return ret; > > drive->waiting_for_dma = 1; > > return 0; > > } > > should look more like: > > static int cris_dma_setup(ide_drive_t *drive) > { > struct request *rq = drive->hwif->hwgroup->rq; > > if (cris_ide_build_dmatable (drive)) { > ide_map_sg(drive, rq); > return 1; > } > > drive->waiting_for_dma = 1; > > return 0; > } > > > cris_ide_reset() and cris_ide_init() should be marked with __init > (for both archs) > > > There is also number of changes w.r.t. v10 support: > * reset and initialization sequences are changed > * "PIO comment" is gone > * RESET_DMA()/WAIT_DMA() pairs are gone > * 65536 sg size limit is gone > * ->speedproc() method is added > * ... > > It would make much sense to separate these changes from addition of v32 > support, this way testing for potential regressions would be much easier: > > 1. do v10 changes > 2. add abstraction layer > 3. add v32 support > 4. rename driver > > One big patch is also fine with me as long as it is correct > (IMHO it is easier to achieve correctness with a patch series). > > Cheers, > Bartlomiej > ^ permalink raw reply [flat|nested] 9+ messages in thread
[parent not found: <BFECAF9E178F144FAEF2BF4CE739C668030176E7@exmail1.se.axis.com>]
* RE: New IDE driver for review [not found] <BFECAF9E178F144FAEF2BF4CE739C668030176E7@exmail1.se.axis.com> @ 2005-06-17 14:16 ` Mikael Starvik 2005-06-20 19:15 ` Bartlomiej Zolnierkiewicz 0 siblings, 1 reply; 9+ messages in thread From: Mikael Starvik @ 2005-06-17 14:16 UTC (permalink / raw) To: 'Bartlomiej Zolnierkiewicz', Mikael Starvik; +Cc: linux-ide [-- Attachment #1: Type: text/plain, Size: 2194 bytes --] Hi, I have created a merged driver for CRIS v10 and v32. Do you think this approach is better? In that case you'll also need a Makefile patch as follows below. /Mikael Index: Makefile =================================================================== RCS file: /usr/local/cvs/linux/os/linux-2.6/drivers/ide/cris/Makefile,v retrieving revision 1.1 diff -u -r1.1 Makefile --- Makefile 27 Dec 2004 08:21:33 -0000 1.1 +++ Makefile 17 Jun 2005 14:14:52 -0000 @@ -1,3 +1,3 @@ EXTRA_CFLAGS += -Idrivers/ide -obj-$(CONFIG_ETRAX_ARCH_V10) += ide-v10.o +obj-y += ide-cris.o -----Original Message----- From: Bartlomiej Zolnierkiewicz [mailto:bzolnier@gmail.com] Sent: Thursday, June 09, 2005 5:10 PM To: Mikael Starvik Cc: linux-ide@vger.kernel.org Subject: Re: New IDE driver for review On 6/9/05, Mikael Starvik <mikael.starvik@axis.com> wrote: > Ok, updated driver and requested include files attached. Thanks. > The drivers are similar but it would still require many ugly ifdef:s or > similar to combine them. I could of course extract the stuff that is the > same to a common file to make the arch-specific files smaller. These drivers > are rarley touched so I see no major maintanence benefit by combining them. I still would like to see one driver: * less maintenance for IDE people * better readability of ide-v10.c (IDE specific stuff separated from arch specific stuff) * good opportunity to cleanup ide-v10.c a bit this won't require many ugly ifdef's, ie. #ifdef v10 static void etrax_ide_set_pio(u8 setup, u8 strobe, u8 hold) { *R_ATA_CONFIG = IO_FIELD(R_ATA_CONFIG, enable, 1 ) | IO_FIELD(R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE) | IO_FIELD(R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD) | IO_FIELD(R_ATA_CONFIG, pio_setup, setup) | IO_FIELD(R_ATA_CONFIG, pio_strobe, strobe) | IO_FIELD(R_ATA_CONFIG, pio_hold, hold); } ... #else static void etrax_ide_set_pio(u8 setup, u8 strobe, u8 hold) { reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); ctrl0.pio_setup = setup; ctrl0.pio_strb = strobe; ctrl0.pio_hold = hold; REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); } ... #endif and later just use etrax_ide_set_pio() Bartlomiej [-- Attachment #2: ide-cris.c --] [-- Type: application/octet-stream, Size: 27687 bytes --] /* $Id$ * * Etrax specific IDE functions, like init and PIO-mode setting etc. * Almost the entire ide.c is used for the rest of the Etrax ATA driver. * Copyright (c) 2000-2005 Axis Communications AB * * Authors: Bjorn Wesen (initial version) * Mikael Starvik (crisv32 port) */ /* Regarding DMA: * * There are two forms of DMA - "DMA handshaking" between the interface and the drive, * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's * something built-in in the Etrax. However only some drives support the DMA-mode handshaking * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the * device can't do DMA handshaking for some stupid reason. We don't need to do that. */ #undef REALLY_SLOW_IO /* most systems can safely undef this */ #include <linux/config.h> #include <linux/types.h> #include <linux/kernel.h> #include <linux/timer.h> #include <linux/mm.h> #include <linux/interrupt.h> #include <linux/delay.h> #include <linux/blkdev.h> #include <linux/hdreg.h> #include <linux/ide.h> #include <linux/init.h> #include <asm/io.h> #include <asm/dma.h> /* number of DMA descriptors */ #define MAX_DMA_DESCRS 64 /* number of times to retry busy-flags when reading/writing IDE-registers * this can't be too high because a hung harddisk might cause the watchdog * to trigger (sometimes INB and OUTB are called with irq's disabled) */ #define IDE_REGISTER_TIMEOUT 300 #define LOWDB(x) #define D(x) enum /* Transfer types */ { TYPE_PIO, TYPE_DMA, TYPE_UDMA }; /* CRISv32 specifics */ #ifdef CONFIG_ETRAX_ARCH_V32 #include <asm/arch/hwregs/ata_defs.h> #include <asm/arch/hwregs/dma_defs.h> #include <asm/arch/hwregs/dma.h> #include <asm/arch/pinmux.h> #define ATA_UDMA2_CYC 2 #define ATA_UDMA2_DVS 3 #define ATA_UDMA1_CYC 2 #define ATA_UDMA1_DVS 4 #define ATA_UDMA0_CYC 4 #define ATA_UDMA0_DVS 6 #define ATA_DMA2_STROBE 7 #define ATA_DMA2_HOLD 1 #define ATA_DMA1_STROBE 8 #define ATA_DMA1_HOLD 3 #define ATA_DMA0_STROBE 25 #define ATA_DMA0_HOLD 19 #define ATA_PIO4_SETUP 3 #define ATA_PIO4_STROBE 7 #define ATA_PIO4_HOLD 1 #define ATA_PIO3_SETUP 3 #define ATA_PIO3_STROBE 9 #define ATA_PIO3_HOLD 3 #define ATA_PIO2_SETUP 3 #define ATA_PIO2_STROBE 13 #define ATA_PIO2_HOLD 5 #define ATA_PIO1_SETUP 5 #define ATA_PIO1_STROBE 23 #define ATA_PIO1_HOLD 9 #define ATA_PIO0_SETUP 9 #define ATA_PIO0_STROBE 39 #define ATA_PIO0_HOLD 9 int cris_ide_ack_intr(ide_hwif_t* hwif) { reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, hwif->io_ports[0]); REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel); return 1; } static inline int cris_ide_busy(void) { reg_ata_rs_stat_data stat_data; stat_data = REG_RD(ata, regi_ata, rs_stat_data); return stat_data.busy; } static inline int cris_ide_data_available(unsigned short* data) { reg_ata_rs_stat_data stat_data; stat_data = REG_RD(ata, regi_ata, rs_stat_data); *data = stat_data.data; return stat_data.dav; } static void cris_ide_write_command(unsigned long command) { REG_WR_INT(ata, regi_ata, rw_ctrl2, command); /* write data to the drive's register */ } static void cris_ide_set_speed(int type, int setup, int strobe, int hold) { reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1); if (type == TYPE_PIO) { ctrl0.pio_setup = setup; ctrl0.pio_strb = strobe; ctrl0.pio_hold = hold; } else if (type == TYPE_DMA) { ctrl0.dma_strb = strobe; ctrl0.dma_hold = hold; } else if (type == TYPE_UDMA) { ctrl1.udma_tcyc = setup; ctrl1.udma_tdvs = strobe; } REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); REG_WR(ata, regi_ata, rw_ctrl1, ctrl1); } static unsigned long cris_ide_base_address(int bus) { reg_ata_rw_ctrl2 ctrl2 = {0}; ctrl2.sel = bus; return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2); } static unsigned long cris_ide_reg_addr(unsigned long addr, int cs0, int cs1) { reg_ata_rw_ctrl2 ctrl2 = {0}; ctrl2.addr = addr; ctrl2.cs1 = cs1; ctrl2.cs0 = cs0; return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2); } static void cris_ide_reset(unsigned val) { reg_ata_rw_ctrl0 ctrl0 = {0}; ctrl0.rst = val ? regk_ata_active : regk_ata_inactive; REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); } static void cris_ide_init(void) { reg_ata_rw_ctrl0 ctrl0 = {0}; reg_ata_rw_intr_mask intr_mask = {0}; ctrl0.en = regk_ata_yes; REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); intr_mask.bus0 = regk_ata_yes; intr_mask.bus1 = regk_ata_yes; intr_mask.bus2 = regk_ata_yes; intr_mask.bus3 = regk_ata_yes; REG_WR(ata, regi_ata, rw_intr_mask, intr_mask); crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata); crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata); crisv32_pinmux_alloc_fixed(pinmux_ata); crisv32_pinmux_alloc_fixed(pinmux_ata0); crisv32_pinmux_alloc_fixed(pinmux_ata1); crisv32_pinmux_alloc_fixed(pinmux_ata2); crisv32_pinmux_alloc_fixed(pinmux_ata3); DMA_RESET(regi_dma2); DMA_ENABLE(regi_dma2); DMA_RESET(regi_dma3); DMA_ENABLE(regi_dma3); DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2); DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2); } static dma_descr_context mycontext __attribute__ ((__aligned__(32))); #define cris_dma_descr_type dma_descr_data #define cris_pio_read regk_ata_rd #define cris_ultra_mask 0x7 static void cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last) { d->buf = (char*)virt_to_phys(buf); d->after = d->buf + len; d->eol = last; } static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,int len) { reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG); reg_ata_rw_trf_cnt trf_cnt = {0}; mycontext.saved_data = (dma_descr_data*)virt_to_phys(d); mycontext.saved_data_buf = d->buf; /* start the dma channel */ DMA_START_CONTEXT(dir ? regi_dma3 : regi_dma2, virt_to_phys(&mycontext)); /* initiate a multi word dma read using PIO handshaking */ trf_cnt.cnt = len >> 1; /* Due to a "feature" the transfer count has to be one extra word for UDMA. */ if (type == TYPE_UDMA) trf_cnt.cnt++; REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt); ctrl2.rw = dir ? regk_ata_rd : regk_ata_wr; ctrl2.trf_mode = regk_ata_dma; ctrl2.hsh = type == TYPE_PIO ? regk_ata_pio : type == TYPE_DMA ? regk_ata_dma : regk_ata_udma; ctrl2.multi = regk_ata_yes; ctrl2.dma_size = regk_ata_word; REG_WR(ata, regi_ata, rw_ctrl2, ctrl2); } static void cris_ide_wait_dma(int dir) { reg_dma_rw_stat status; do { status = REG_RD(dma, dir ? regi_dma3 : regi_dma2, rw_stat); } while(status.list_state != regk_dma_data_at_eol); } static int cris_dma_test_irq(ide_drive_t *drive) { int intr = REG_RD_INT(ata, regi_ata, r_intr); reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG); return intr & (1 << ctrl2.sel) ? 1 : 0; } #else /* CRISv10 specifics */ #include <asm/arch/svinto.h> #include <asm/arch/io_interface_mux.h> #define ATA_UDMA2_CYC 0 /* No UDMA supported, just to make it compile. */ #define ATA_UDMA2_DVS 0 #define ATA_UDMA1_CYC 0 #define ATA_UDMA1_DVS 0 #define ATA_UDMA0_CYC 0 #define ATA_UDMA0_DVS 0 #define ATA_DMA2_STROBE 4 #define ATA_DMA2_HOLD 0 #define ATA_DMA1_STROBE 4 #define ATA_DMA1_HOLD 1 #define ATA_DMA0_STROBE 12 #define ATA_DMA0_HOLD 9 #define ATA_PIO4_SETUP 1 #define ATA_PIO4_STROBE 5 #define ATA_PIO4_HOLD 0 #define ATA_PIO3_SETUP 1 #define ATA_PIO3_STROBE 5 #define ATA_PIO3_HOLD 1 #define ATA_PIO2_SETUP 1 #define ATA_PIO2_STROBE 6 #define ATA_PIO2_HOLD 2 #define ATA_PIO1_SETUP 2 #define ATA_PIO1_STROBE 11 #define ATA_PIO1_HOLD 4 #define ATA_PIO0_SETUP 4 #define ATA_PIO0_STROBE 19 #define ATA_PIO0_HOLD 4 int cris_ide_ack_intr(ide_hwif_t* hwif) { return 1; } static inline int cris_ide_busy(void) { return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy) ; } static inline int cris_ide_data_available(unsigned short* data) { unsigned long status = *R_ATA_STATUS_DATA; *data = (unsigned short)status; return status & IO_MASK(R_ATA_STATUS_DATA, dav); } static void cris_ide_write_command(unsigned long command) { *R_ATA_CTRL_DATA = command; } static void cris_ide_set_speed(int type, int setup, int strobe, int hold) { static int pio_setup = ATA_PIO4_SETUP; static int pio_strobe = ATA_PIO4_STROBE; static int pio_hold = ATA_PIO4_HOLD; static int dma_strobe = ATA_DMA2_STROBE; static int dma_hold = ATA_DMA2_HOLD; if (type == TYPE_PIO) { pio_setup = setup; pio_strobe = strobe; pio_hold = hold; } else if (type == TYPE_DMA) { dma_strobe = strobe; dma_hold = hold; } *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) | IO_FIELD( R_ATA_CONFIG, dma_strobe, dma_strobe ) | IO_FIELD( R_ATA_CONFIG, dma_hold, dma_hold ) | IO_FIELD( R_ATA_CONFIG, pio_setup, pio_setup ) | IO_FIELD( R_ATA_CONFIG, pio_strobe, pio_strobe ) | IO_FIELD( R_ATA_CONFIG, pio_hold, pio_hold ) ); } static unsigned long cris_ide_base_address(int bus) { return IO_FIELD(R_ATA_CTRL_DATA, sel, bus); } static unsigned long cris_ide_reg_addr(unsigned long addr, int cs0, int cs1) { return IO_FIELD(R_ATA_CTRL_DATA, addr, addr) | IO_FIELD(R_ATA_CTRL_DATA, cs0, cs0) | IO_FIELD(R_ATA_CTRL_DATA, cs1, cs1); } static void cris_ide_reset(unsigned val) { #ifdef CONFIG_ETRAX_IDE_G27_RESET REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, val); #endif #ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, val); #endif #ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, val); #endif #ifdef CONFIG_ETRAX_IDE_PB7_RESET port_pb_dir_shadow = port_pb_dir_shadow | IO_STATE(R_PORT_PB_DIR, dir7, output); *R_PORT_PB_DIR = port_pb_dir_shadow; REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, val); #endif } static void cris_ide_init(void) { volatile unsigned int dummy; *R_ATA_CTRL_DATA = 0; *R_ATA_TRANSFER_CNT = 0; *R_ATA_CONFIG = 0; if (cris_request_io_interface(if_ata, "ETRAX100LX IDE")) { printk(KERN_CRIT "ide: Failed to get IO interface\n"); return; } else if (cris_request_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE TX", DMA_VERBOSE_ON_ERROR, dma_ata)) { cris_free_io_interface(if_ata); printk(KERN_CRIT "ide: Failed to get Tx DMA channel\n"); return; } else if (cris_request_dma(ATA_RX_DMA_NBR, "ETRAX100LX IDE RX", DMA_VERBOSE_ON_ERROR, dma_ata)) { cris_free_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE Tx"); cris_free_io_interface(if_ata); printk(KERN_CRIT "ide: Failed to get Rx DMA channel\n"); return; } /* make a dummy read to set the ata controller in a proper state */ dummy = *R_ATA_STATUS_DATA; *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 )); *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) | IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) ); while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/ *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) | IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) | IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) | IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) ); /* reset the dma channels we will use */ RESET_DMA(ATA_TX_DMA_NBR); RESET_DMA(ATA_RX_DMA_NBR); WAIT_DMA(ATA_TX_DMA_NBR); WAIT_DMA(ATA_RX_DMA_NBR); } #define cris_dma_descr_type etrax_dma_descr #define cris_pio_read IO_STATE(R_ATA_CTRL_DATA, rw, read) #define cris_ultra_mask 0x0 static void cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last) { d->buf = virt_to_phys(buf); d->sw_len = len; if (last) d->ctrl |= d_eol; } static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir, int type, int len) { unsigned long cmd; if (dir) { /* need to do this before RX DMA due to a chip bug * it is enough to just flush the part of the cache that * corresponds to the buffers we start, but since HD transfers * usually are more than 8 kB, it is easier to optimize for the * normal case and just flush the entire cache. its the only * way to be sure! (OB movie quote) */ flush_etrax_cache(); *R_DMA_CH3_FIRST = virt_to_phys(d); *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start); } else { *R_DMA_CH2_FIRST = virt_to_phys(d); *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start); } /* initiate a multi word dma read using DMA handshaking */ *R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, len >> 1); cmd = dir ? IO_STATE(R_ATA_CTRL_DATA, rw, read) : IO_STATE(R_ATA_CTRL_DATA, rw, write); cmd |= type == TYPE_PIO ? IO_STATE(R_ATA_CTRL_DATA, handsh, pio) : IO_STATE(R_ATA_CTRL_DATA, handsh, dma); *R_ATA_CTRL_DATA = cmd | IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) | IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) | IO_STATE(R_ATA_CTRL_DATA, multi, on) | IO_STATE(R_ATA_CTRL_DATA, dma_size, word); } static void cris_ide_wait_dma(int dir) { if (dir) WAIT_DMA(ATA_RX_DMA_NBR); else WAIT_DMA(ATA_TX_DMA_NBR); } static int cris_dma_test_irq(ide_drive_t *drive) { int intr = *R_IRQ_MASK0_RD; int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel, IDE_DATA_REG); return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0; } #endif void cris_ide_outw(unsigned short data, unsigned long reg) { int timeleft; LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg)); /* note the lack of handling any timeouts. we stop waiting, but we don't * really notify anybody. */ timeleft = IDE_REGISTER_TIMEOUT; /* wait for busy flag */ do { timeleft--; } while(timeleft && cris_ide_busy()); /* * Fall through at a timeout, so the ongoing command will be * aborted by the write below, which is expected to be a dummy * command to the command register. This happens when a faulty * drive times out on a command. See comment on timeout in * INB. */ if(!timeleft) printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data); cris_ide_write_command(reg|data); /* write data to the drive's register */ timeleft = IDE_REGISTER_TIMEOUT; /* wait for transmitter ready */ do { timeleft--; } while(timeleft && cris_ide_busy()); } void cris_ide_outb(unsigned char data, unsigned long reg) { cris_ide_outw(data, reg); } void cris_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port) { cris_ide_outw(addr, port); } unsigned short cris_ide_inw(unsigned long reg) { int timeleft; unsigned short val; timeleft = IDE_REGISTER_TIMEOUT; /* wait for busy flag */ do { timeleft--; } while(timeleft && cris_ide_busy()); if(!timeleft) return 0; cris_ide_write_command(reg | cris_pio_read); timeleft = IDE_REGISTER_TIMEOUT; /* wait for available */ do { timeleft--; } while(timeleft && !cris_ide_data_available(&val)); if(!timeleft) return 0; LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg)); return val; } unsigned char cris_ide_inb(unsigned long reg) { return (unsigned char)cris_ide_inw(reg); } static int cris_dma_check (ide_drive_t *drive); static int cris_dma_end (ide_drive_t *drive); static int cris_dma_setup (ide_drive_t *drive); static void cris_dma_exec_cmd (ide_drive_t *drive, u8 command); static int cris_dma_test_irq(ide_drive_t *drive); static void cris_dma_start(ide_drive_t *drive); static void cris_ide_input_data (ide_drive_t *drive, void *, unsigned int); static void cris_ide_output_data (ide_drive_t *drive, void *, unsigned int); static void cris_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int); static void cris_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int); static int cris_dma_off (ide_drive_t *drive); static int cris_dma_on (ide_drive_t *drive); static void tune_cris_ide(ide_drive_t *drive, u8 pio) { int setup, strobe, hold; switch(pio) { case 0: setup = ATA_PIO0_SETUP; strobe = ATA_PIO0_STROBE; hold = ATA_PIO0_HOLD; break; case 1: setup = ATA_PIO1_SETUP; strobe = ATA_PIO1_STROBE; hold = ATA_PIO1_HOLD; break; case 2: setup = ATA_PIO2_SETUP; strobe = ATA_PIO2_STROBE; hold = ATA_PIO2_HOLD; break; case 3: setup = ATA_PIO3_SETUP; strobe = ATA_PIO3_STROBE; hold = ATA_PIO3_HOLD; break; case 4: setup = ATA_PIO4_SETUP; strobe = ATA_PIO4_STROBE; hold = ATA_PIO4_HOLD; break; default: return; } cris_ide_set_speed(TYPE_PIO, setup, strobe, hold); } static int speed_cris_ide(ide_drive_t *drive, u8 speed) { int cyc = 0, dvs = 0, strobe = 0, hold = 0; if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) { tune_cris_ide(drive, speed - XFER_PIO_0); return 0; } switch(speed) { case XFER_UDMA_0: cyc = ATA_UDMA0_CYC; dvs = ATA_UDMA0_DVS; break; case XFER_UDMA_1: cyc = ATA_UDMA1_CYC; dvs = ATA_UDMA1_DVS; break; case XFER_UDMA_2: cyc = ATA_UDMA2_CYC; dvs = ATA_UDMA2_DVS; break; case XFER_MW_DMA_0: strobe = ATA_DMA0_STROBE; hold = ATA_DMA0_HOLD; break; case XFER_MW_DMA_1: strobe = ATA_DMA1_STROBE; hold = ATA_DMA1_HOLD; break; case XFER_MW_DMA_2: strobe = ATA_DMA2_STROBE; hold = ATA_DMA2_HOLD; break; default: return 0; } if (speed >= XFER_UDMA_0) cris_ide_set_speed(TYPE_UDMA, cyc, dvs, 0); else cris_ide_set_speed(TYPE_DMA, 0, strobe, hold); return 0; } void __init init_e100_ide (void) { hw_regs_t hw; int ide_offsets[IDE_NR_PORTS]; int h; int i; printk("ide: ETRAX FS built-in ATA DMA controller\n"); for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) ide_offsets[i] = cris_ide_reg_addr(i, 0, 1); /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */ ide_offsets[IDE_CONTROL_OFFSET] = cris_ide_reg_addr(6, 1, 0); /* first fill in some stuff in the ide_hwifs fields */ for(h = 0; h < MAX_HWIFS; h++) { ide_hwif_t *hwif = &ide_hwifs[h]; ide_setup_ports(&hw, cris_ide_base_address(h), ide_offsets, 0, 0, cris_ide_ack_intr, ide_default_irq(0)); ide_register_hw(&hw, &hwif); hwif->mmio = 2; hwif->chipset = ide_etrax100; hwif->tuneproc = &tune_cris_ide; hwif->speedproc = &speed_cris_ide; hwif->ata_input_data = &cris_ide_input_data; hwif->ata_output_data = &cris_ide_output_data; hwif->atapi_input_bytes = &cris_atapi_input_bytes; hwif->atapi_output_bytes = &cris_atapi_output_bytes; hwif->ide_dma_check = &cris_dma_check; hwif->ide_dma_end = &cris_dma_end; hwif->dma_setup = &cris_dma_setup; hwif->dma_exec_cmd = &cris_dma_exec_cmd; hwif->ide_dma_test_irq = &cris_dma_test_irq; hwif->dma_start = &cris_dma_start; hwif->OUTB = &cris_ide_outb; hwif->OUTW = &cris_ide_outw; hwif->OUTBSYNC = &cris_ide_outbsync; hwif->INB = &cris_ide_inb; hwif->INW = &cris_ide_inw; hwif->ide_dma_host_off = &cris_dma_off; hwif->ide_dma_host_on = &cris_dma_on; hwif->ide_dma_off_quietly = &cris_dma_off; hwif->udma_four = 0; hwif->ultra_mask = cris_ultra_mask; hwif->mwdma_mask = 0x07; /* Multiword DMA 0-2 */ hwif->swdma_mask = 0x07; /* Singleword DMA 0-2 */ } /* Reset pulse */ cris_ide_reset(0); udelay(25); cris_ide_reset(1); cris_ide_init(); cris_ide_set_speed(TYPE_PIO, ATA_PIO4_SETUP, ATA_PIO4_STROBE, ATA_PIO4_HOLD); cris_ide_set_speed(TYPE_DMA, 0, ATA_DMA2_STROBE, ATA_DMA2_HOLD); cris_ide_set_speed(TYPE_UDMA, ATA_UDMA2_CYC, ATA_UDMA2_DVS, 0); } static int cris_dma_off (ide_drive_t *drive) { return 0; } static int cris_dma_on (ide_drive_t *drive) { return 0; } static cris_dma_descr_type mydescr __attribute__ ((__aligned__(16))); /* * The following routines are mainly used by the ATAPI drivers. * * These routines will round up any request for an odd number of bytes, * so if an odd bytecount is specified, be sure that there's at least one * extra byte allocated for the buffer. */ static void cris_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) { D(printk("atapi_input_bytes, buffer 0x%x, count %d\n", buffer, bytecount)); if(bytecount & 1) { printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount); bytecount++; /* to round off */ } /* setup DMA and start transfer */ cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1); cris_ide_start_dma(drive, &mydescr, 1, TYPE_PIO, bytecount); /* wait for completion */ LED_DISK_READ(1); cris_ide_wait_dma(1); LED_DISK_READ(0); } static void cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) { D(printk("atapi_output_bytes, dreg 0x%x, buffer 0x%x, count %d\n", 0, buffer, bytecount)); if(bytecount & 1) { printk("odd bytecount %d in atapi_out_bytes!\n", bytecount); bytecount++; } cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1); cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount); /* wait for completion */ LED_DISK_WRITE(1); LED_DISK_READ(1); cris_ide_wait_dma(1); LED_DISK_WRITE(0); } /* * This is used for most PIO data transfers *from* the IDE interface */ static void cris_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount) { cris_atapi_input_bytes(drive, buffer, wcount << 2); } /* * This is used for most PIO data transfers *to* the IDE interface */ static void cris_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount) { cris_atapi_output_bytes(drive, buffer, wcount << 2); } /* we only have one DMA channel on the chip for ATA, so we can keep these statically */ static cris_dma_descr_type ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16))); static unsigned int ata_tot_size; /* * cris_ide_build_dmatable() prepares a dma request. * Returns 0 if all went okay, returns 1 otherwise. */ static int cris_ide_build_dmatable (ide_drive_t *drive) { ide_hwif_t *hwif = drive->hwif; struct scatterlist* sg; struct request *rq = drive->hwif->hwgroup->rq; unsigned long size, addr; unsigned int count = 0; int i = 0; sg = hwif->sg_table; ata_tot_size = 0; ide_map_sg(drive, rq); i = hwif->sg_nents; while(i) { /* * Determine addr and size of next buffer area. We assume that * individual virtual buffers are always composed linearly in * physical memory. For example, we assume that any 8kB buffer * is always composed of two adjacent physical 4kB pages rather * than two possibly non-adjacent physical 4kB pages. */ /* group sequential buffers into one large buffer */ addr = page_to_phys(sg->page) + sg->offset; size = sg_dma_len(sg); while (sg++, --i) { if ((addr + size) != page_to_phys(sg->page) + sg->offset) break; size += sg_dma_len(sg); } /* did we run out of descriptors? */ if(count >= MAX_DMA_DESCRS) { printk("%s: too few DMA descriptors\n", drive->name); return 1; } /* however, this case is more difficult - rw_trf_cnt cannot be more than 65536 words per transfer, so in that case we need to either 1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with the descriptors, or 2) simply do the request here, and get dma_intr to only ide_end_request on those blocks that were actually set-up for transfer. */ if(ata_tot_size + size > 131072) { printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size); return 1; } cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, size,i ? 0 : 1); count++; ata_tot_size += size; } if (count) { /* return and say all is ok */ return 0; } printk("%s: empty DMA table?\n", drive->name); return 1; /* let the PIO routines handle this weirdness */ } static int config_drive_for_dma (ide_drive_t *drive) { struct hd_driveid *id = drive->id; if (id && (id->capability & 1)) { /* Enable DMA on any drive that supports mword2 DMA */ if ((id->field_valid & 2) && ((id->dma_mword & 0xff00) || (id->dma_ultra & 0xff00))) { drive->using_dma = 1; return 0; /* DMA enabled */ } } drive->using_dma = 0; return 0; /* DMA not enabled */ } /* * cris_dma_intr() is the handler for disk read/write DMA interrupts */ static ide_startstop_t cris_dma_intr (ide_drive_t *drive) { LED_DISK_READ(0); LED_DISK_WRITE(0); return ide_dma_intr(drive); } /* * Functions below initiates/aborts DMA read/write operations on a drive. * * The caller is assumed to have selected the drive and programmed the drive's * sector address using CHS or LBA. All that remains is to prepare for DMA * and then issue the actual read/write DMA/PIO command to the drive. * * For ATAPI devices, we just prepare for DMA and return. The caller should * then issue the packet command to the drive and call us again with * ide_dma_begin afterwards. * * Returns 0 if all went well. * Returns 1 if DMA read/write could not be started, in which case * the caller should revert to PIO for the current request. */ static int cris_dma_check(ide_drive_t *drive) { int speed = ide_dma_speed(drive, 0); /* No UDMA for now */ speed_cris_ide(drive, speed); ide_config_drive_speed(drive, speed); return config_drive_for_dma (drive); } static int cris_dma_end(ide_drive_t *drive) { drive->waiting_for_dma = 0; return 0; } static int cris_prepare_dma(ide_drive_t *drive, int atapi, int reading) { struct request *rq = drive->hwif->hwgroup->rq; if (cris_ide_build_dmatable (drive)) { ide_map_sg(drive, rq); return 1; } return 0; } static int cris_dma_setup(ide_drive_t *drive) { struct request *rq = drive->hwif->hwgroup->rq; int ret; if (rq_data_dir(rq)) ret = cris_prepare_dma(drive, 0, 0); else ret = cris_prepare_dma(drive, 0, 1); if (ret) return ret; drive->waiting_for_dma = 1; return 0; } static void cris_dma_exec_cmd(ide_drive_t *drive, u8 command) { /* set the irq handler which will finish the request when DMA is done */ ide_set_handler(drive, &cris_dma_intr, WAIT_CMD, NULL); /* issue cmd to drive */ cris_ide_outb(command, IDE_COMMAND_REG); } static void cris_dma_start(ide_drive_t *drive) { struct request *rq = drive->hwif->hwgroup->rq; int writing = rq_data_dir(rq); int type = TYPE_DMA; if (drive->current_speed >= XFER_UDMA_0) type = TYPE_UDMA; cris_ide_start_dma(drive, &ata_descrs[0], writing ? 0 : 1, type, ata_tot_size); if (writing) { LED_DISK_WRITE(1); } else { LED_DISK_READ(1); } } ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: New IDE driver for review 2005-06-17 14:16 ` Mikael Starvik @ 2005-06-20 19:15 ` Bartlomiej Zolnierkiewicz 0 siblings, 0 replies; 9+ messages in thread From: Bartlomiej Zolnierkiewicz @ 2005-06-20 19:15 UTC (permalink / raw) To: Mikael Starvik; +Cc: Mikael Starvik, linux-ide On 6/17/05, Mikael Starvik <mikael.starvik@axis.com> wrote: > Hi, Hi, > I have created a merged driver for CRIS v10 and v32. Do you think this > approach is better? In that case you'll also need a Makefile patch as > follows below. Looks much better. Thanks for doing this. Few comments: > void > cris_ide_outw(unsigned short data, unsigned long reg) { > int timeleft; > > LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg)); > > /* note the lack of handling any timeouts. we stop waiting, but we don't > * really notify anybody. > */ > > timeleft = IDE_REGISTER_TIMEOUT; > /* wait for busy flag */ > do { > timeleft--; > } while(timeleft && cris_ide_busy()); > > /* > * Fall through at a timeout, so the ongoing command will be > * aborted by the write below, which is expected to be a dummy > * command to the command register. This happens when a faulty > * drive times out on a command. See comment on timeout in > * INB. > */ > if(!timeleft) > printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data); > > cris_ide_write_command(reg|data); /* write data to the drive's register */ > > timeleft = IDE_REGISTER_TIMEOUT; > /* wait for transmitter ready */ > do { > timeleft--; > } while(timeleft && cris_ide_busy()); previously it was: while(timeleft && !(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy))) timeleft--; for v10, is it OK to use busy instead of tr_rdy? > } > unsigned short > cris_ide_inw(unsigned long reg) { > int timeleft; > unsigned short val; > > timeleft = IDE_REGISTER_TIMEOUT; > /* wait for busy flag */ > do { > timeleft--; > } while(timeleft && cris_ide_busy()); > > if(!timeleft) > return 0; previously there was a special case for IDE_STATUS_OFFSET here, is it not needed any longer? > cris_ide_write_command(reg | cris_pio_read); > > timeleft = IDE_REGISTER_TIMEOUT; > /* wait for available */ > do { > timeleft--; > } while(timeleft && !cris_ide_data_available(&val)); > > if(!timeleft) > return 0; > > LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg)); > > return val; > } > static void > cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) > { > D(printk("atapi_output_bytes, dreg 0x%x, buffer 0x%x, count %d\n", > 0, buffer, bytecount)); dreg? > if(bytecount & 1) { > printk("odd bytecount %d in atapi_out_bytes!\n", bytecount); > bytecount++; > } > > cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1); > cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount); > > /* wait for completion */ > > LED_DISK_WRITE(1); > LED_DISK_READ(1); > cris_ide_wait_dma(1); cris_ide_wait_dma(0) ? > LED_DISK_WRITE(0); > } > static int config_drive_for_dma (ide_drive_t *drive) > { > struct hd_driveid *id = drive->id; > > if (id && (id->capability & 1)) { > /* Enable DMA on any drive that supports mword2 DMA */ > if ((id->field_valid & 2) && > ((id->dma_mword & 0xff00) || (id->dma_ultra & 0xff00))) { no checking of (id->field_valid & 4) DMA will be used only if drive has it already enabled > drive->using_dma = 1; drive->using_dma shouldn't be touched at this layer > return 0; /* DMA enabled */ > } > } > drive->using_dma = 0; > return 0; /* DMA not enabled */ DMA whitelist/blacklist checking is missing > } should look more like: static int cris_config_drive_for_dma(ide_drive_t *drive) { u8 speed = ide_dma_speed(drive, 0); /* no UDMA for now */ if (!speed) return 0; speed_cris_ide(drive, speed); ide_config_drive_speed(drive, speed); return ide_dma_enable(drive); } > * For ATAPI devices, we just prepare for DMA and return. The caller should > * then issue the packet command to the drive and call us again with > * ide_dma_begin afterwards. this comment got re-introduced s/ide_dma_begin/->dma_start()/ > static int cris_dma_check(ide_drive_t *drive) > { > int speed = ide_dma_speed(drive, 0); /* No UDMA for now */ No UDMA? > speed_cris_ide(drive, speed); > ide_config_drive_speed(drive, speed); > return config_drive_for_dma (drive); > } should look more like: static int cris_dma_check(ide_drive_t *drive) { ide_hwif_t *hwif = drive->hwif; struct hd_driveid *id = drive->id; if (id && (id->capability & 1)) { if (ide_use_dma(drive) { if (cris_config_drive_for_dma(drive)) return hwif->ide_dma_on(drive); } } return hwif->ide_dma_off_quietly(drive); } > static int cris_prepare_dma(ide_drive_t *drive, int atapi, int reading) atapi and reading arguments are unused > { > struct request *rq = drive->hwif->hwgroup->rq; > if (cris_ide_build_dmatable (drive)) { > ide_map_sg(drive, rq); > return 1; > } > > return 0; > } > > static int cris_dma_setup(ide_drive_t *drive) > { > struct request *rq = drive->hwif->hwgroup->rq; > int ret; > if (rq_data_dir(rq)) > ret = cris_prepare_dma(drive, 0, 0); > else > ret = cris_prepare_dma(drive, 0, 1); > if (ret) > return ret; > drive->waiting_for_dma = 1; > return 0; > } should look more like: static int cris_dma_setup(ide_drive_t *drive) { struct request *rq = drive->hwif->hwgroup->rq; if (cris_ide_build_dmatable (drive)) { ide_map_sg(drive, rq); return 1; } drive->waiting_for_dma = 1; return 0; } cris_ide_reset() and cris_ide_init() should be marked with __init (for both archs) There is also number of changes w.r.t. v10 support: * reset and initialization sequences are changed * "PIO comment" is gone * RESET_DMA()/WAIT_DMA() pairs are gone * 65536 sg size limit is gone * ->speedproc() method is added * ... It would make much sense to separate these changes from addition of v32 support, this way testing for potential regressions would be much easier: 1. do v10 changes 2. add abstraction layer 3. add v32 support 4. rename driver One big patch is also fine with me as long as it is correct (IMHO it is easier to achieve correctness with a patch series). Cheers, Bartlomiej ^ permalink raw reply [flat|nested] 9+ messages in thread
[parent not found: <BFECAF9E178F144FAEF2BF4CE739C668030174FD@exmail1.se.axis.com>]
* RE: New IDE driver for review [not found] <BFECAF9E178F144FAEF2BF4CE739C668030174FD@exmail1.se.axis.com> @ 2005-06-09 10:29 ` Mikael Starvik 2005-06-09 12:54 ` Mikael Starvik 1 sibling, 0 replies; 9+ messages in thread From: Mikael Starvik @ 2005-06-09 10:29 UTC (permalink / raw) To: 'Bartlomiej Zolnierkiewicz'; +Cc: linux-ide Great, thanks for your time! I'll correct the things you point out and send the files again (including .h-files) for a new round. /Mikael -----Original Message----- From: Bartlomiej Zolnierkiewicz [mailto:bzolnier@gmail.com] Sent: Thursday, June 09, 2005 12:14 PM To: Mikael Starvik Cc: linux-ide@vger.kernel.org Subject: Re: New IDE driver for review Hi, On 6/9/05, Mikael Starvik <mikael.starvik@axis.com> wrote: > I am about to release a new subarchitecture to the cris architcecture. > A part of this release is a new IDE driver. Basically just a port of > the IDE driver for the old architecture with the addition of UDMA 0-2. > > The driver is attached if anyone wants to review it before submission. > I understand if no one is interrested in taking a look at it (CRIS > is really a minor arch). it depends on the IDE subsystem so... > If no one objects I'll send this to Andrew after the 2.6.12 release. >From the quick review: following files are needed to really understand what the driver is doing... > #include <asm/arch/hwregs/ata_defs.h> > #include <asm/arch/hwregs/dma_defs.h> > #include <asm/arch/hwregs/dma.h> ... > static void tune_crisv32_ide(ide_drive_t *drive, byte pio) > { please use 'u8' instead of 'byte' (everywhere) > reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); > reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1); ctrl1 variable is not modified anywhere in tune_crisv32_ide(), if hardware doesn't require related registers (can't tell more - you haven't attached include files) to be refreshed it can be removed > if (pio <= 4) > pio = ide_get_best_pio_mode(drive, pio, 4, NULL); ide_get_best_pio_mode() call with such parameters returns 'pio', you can remove these two lines > switch(pio) > { > case 0: > ctrl0.pio_setup = ATA_PIO0_SETUP; > ctrl0.pio_strb = ATA_PIO0_STROBE; > ctrl0.pio_hold = ATA_PIO0_HOLD; > break; > case 1: > ctrl0.pio_setup = ATA_PIO1_SETUP; > ctrl0.pio_strb = ATA_PIO1_STROBE; > ctrl0.pio_hold = ATA_PIO1_HOLD; > break; > case 2: > ctrl0.pio_setup = ATA_PIO2_SETUP; > ctrl0.pio_strb = ATA_PIO2_STROBE; > ctrl0.pio_hold = ATA_PIO2_HOLD; > break; > case 3: > ctrl0.pio_setup = ATA_PIO3_SETUP; > ctrl0.pio_strb = ATA_PIO3_STROBE; > ctrl0.pio_hold = ATA_PIO3_HOLD; > break; > case 4: > ctrl0.pio_setup = ATA_PIO4_SETUP; > ctrl0.pio_strb = ATA_PIO4_STROBE; > ctrl0.pio_hold = ATA_PIO4_HOLD; > break; > } > > REG_WR(ata, regi_ata, rw_ctrl1, ctrl1); > REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); > } > > static int speed_crisv32_ide(ide_drive_t *drive, byte speed) > { > reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); > reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1); > > switch(speed) > { > case XFER_UDMA_0: > ctrl1.udma_tcyc = ATA_UDMA0_CYC; > ctrl1.udma_tdvs = ATA_UDMA0_DVS; > break; > case XFER_UDMA_1: > ctrl1.udma_tcyc = ATA_UDMA1_CYC; > ctrl1.udma_tdvs = ATA_UDMA1_DVS; > break; > case XFER_UDMA_2: > ctrl1.udma_tcyc = ATA_UDMA2_CYC; > ctrl1.udma_tdvs = ATA_UDMA2_DVS; > break; > case XFER_MW_DMA_2: > ctrl0.dma_strb = ATA_DMA0_STROBE; > ctrl0.dma_hold = ATA_DMA0_HOLD; > break; is this correct: XFER_MW_DMA_2 -> ATA_DMA0_* ? > case XFER_MW_DMA_0: > ctrl0.dma_strb = ATA_DMA2_STROBE; > ctrl0.dma_hold = ATA_DMA2_HOLD; > break; ditto > case XFER_PIO_0: > ctrl0.pio_setup = ATA_PIO0_SETUP; > ctrl0.pio_strb = ATA_PIO0_STROBE; > ctrl0.pio_hold = ATA_PIO0_HOLD; > break; > case XFER_PIO_1: > ctrl0.pio_setup = ATA_PIO1_SETUP; > ctrl0.pio_strb = ATA_PIO1_STROBE; > ctrl0.pio_hold = ATA_PIO1_HOLD; > break; > case XFER_PIO_2: > ctrl0.pio_setup = ATA_PIO2_SETUP; > ctrl0.pio_strb = ATA_PIO2_STROBE; > ctrl0.pio_hold = ATA_PIO2_HOLD; > break; > case XFER_PIO_3: > ctrl0.pio_setup = ATA_PIO3_SETUP; > ctrl0.pio_strb = ATA_PIO3_STROBE; > ctrl0.pio_hold = ATA_PIO3_HOLD; > break; > case XFER_PIO_4: > ctrl0.pio_setup = ATA_PIO4_SETUP; > ctrl0.pio_strb = ATA_PIO4_STROBE; > ctrl0.pio_hold = ATA_PIO4_HOLD; > break; > } PIO setup code is _identical_ to that in tune_crisv32_ide(), speed_crisv32_ide() can be rewritten to use tune_crisv32_ide(): static int speed_crisv32_ide(ide_drive_t *drive, u8 speed) { reg_ata_rw_ctrl0 ctrl0; reg_ata_rw_ctrl1 ctrl1; if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) return tune_crisv32_ide(drive, speed); ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1); ... } > REG_WR(ata, regi_ata, rw_ctrl1, ctrl1); > REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); > > return 0; > } > void __init > init_e100_ide (void) > { > hwif->udma_four = 1; why is host side 80-wires cable flag always set? this controller doesn't even support UDMA > 2 > hwif->sg_table = > kmalloc(sizeof(struct scatterlist) * PRD_ENTRIES, GFP_KERNEL); this will memleak memory as hwif->sg_table is allocated during probe > static int crisv32_ide_build_dmatable (ide_drive_t *drive) > { > ide_hwif_t *hwif = HWIF(drive); please use 'drive->hwif' instead of HWIF() (everywhere) > struct scatterlist* sg; > struct request *rq = HWGROUP(drive)->rq; please use 'drive->hwif->hwgroup' instead of HWGROUP() (everywhere) > if (HWGROUP(drive)->rq->flags & REQ_DRIVE_TASKFILE) { > u8 *virt_addr = rq->buffer; > int sector_count = rq->nr_sectors; > memset(&sg[0], 0, sizeof(*sg)); > sg[0].page = virt_to_page(virt_addr); > sg[0].offset = offset_in_page(virt_addr); > sg[0].length = sector_count * SECTOR_SIZE; > hwif->sg_nents = i = 1; > } > else > { > hwif->sg_nents = i = blk_rq_map_sg(drive->queue, rq, hwif->sg_table); > } above code should be replaced by: ide_map_sg(drive, rq); i = hwif->sg_nents; > static ide_startstop_t crisv32_dma_intr (ide_drive_t *drive) > { > int i, dma_stat; > byte stat; > > LED_DISK_READ(0); > LED_DISK_WRITE(0); > > dma_stat = HWIF(drive)->ide_dma_end(drive); > stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */ > if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { > if (!dma_stat) { > struct request *rq; > rq = HWGROUP(drive)->rq; > for (i = rq->nr_sectors; i > 0;) { > i -= rq->current_nr_sectors; > DRIVER(drive)->end_request(drive, 1, rq->nr_sectors); > } > return ide_stopped; > } > printk("%s: bad DMA status\n", drive->name); > } > return ide_error(drive, "dma_intr", stat); > } this won't even compile with 2.6.12-rc6 (DRIVER() was removed), besides crisv32_dma_intr() can be much simpler: static ide_startstop_t crisv32_dma_intr(ide_drive_t *drive) { LED_DISK_READ(0); LED_DISK_WRITE(0); return ide_dma_intr(drive); } It may be reasonable to merge ide-v10.c and ide-v32.c drivers (using macros to abstract differences etc.) but without seeing register layout for v32 I can't tell for sure (hint: missing include files). Thanks, Bartlomiej ^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: New IDE driver for review [not found] <BFECAF9E178F144FAEF2BF4CE739C668030174FD@exmail1.se.axis.com> 2005-06-09 10:29 ` Mikael Starvik @ 2005-06-09 12:54 ` Mikael Starvik 2005-06-09 15:10 ` Bartlomiej Zolnierkiewicz 1 sibling, 1 reply; 9+ messages in thread From: Mikael Starvik @ 2005-06-09 12:54 UTC (permalink / raw) To: 'Bartlomiej Zolnierkiewicz', Mikael Starvik; +Cc: linux-ide [-- Attachment #1: Type: text/plain, Size: 7869 bytes --] Ok, updated driver and requested include files attached. The drivers are similar but it would still require many ugly ifdef:s or similar to combine them. I could of course extract the stuff that is the same to a common file to make the arch-specific files smaller. These drivers are rarley touched so I see no major maintanence benefit by combining them. /Mikael A patch for the Makefile in drives/ide/cris is also necessary: Index: Makefile =================================================================== RCS file: /usr/local/cvs/linux/os/linux-2.6/drivers/ide/cris/Makefile,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -r1.1.1.1 -r1.2 3a4 > obj-$(CONFIG_ETRAX_ARCH_V32) += ide-v32.o -----Original Message----- From: Bartlomiej Zolnierkiewicz [mailto:bzolnier@gmail.com] Sent: Thursday, June 09, 2005 12:14 PM To: Mikael Starvik Cc: linux-ide@vger.kernel.org Subject: Re: New IDE driver for review Hi, On 6/9/05, Mikael Starvik <mikael.starvik@axis.com> wrote: > I am about to release a new subarchitecture to the cris architcecture. > A part of this release is a new IDE driver. Basically just a port of > the IDE driver for the old architecture with the addition of UDMA 0-2. > > The driver is attached if anyone wants to review it before submission. > I understand if no one is interrested in taking a look at it (CRIS > is really a minor arch). it depends on the IDE subsystem so... > If no one objects I'll send this to Andrew after the 2.6.12 release. >From the quick review: following files are needed to really understand what the driver is doing... > #include <asm/arch/hwregs/ata_defs.h> > #include <asm/arch/hwregs/dma_defs.h> > #include <asm/arch/hwregs/dma.h> ... > static void tune_crisv32_ide(ide_drive_t *drive, byte pio) > { please use 'u8' instead of 'byte' (everywhere) > reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); > reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1); ctrl1 variable is not modified anywhere in tune_crisv32_ide(), if hardware doesn't require related registers (can't tell more - you haven't attached include files) to be refreshed it can be removed > if (pio <= 4) > pio = ide_get_best_pio_mode(drive, pio, 4, NULL); ide_get_best_pio_mode() call with such parameters returns 'pio', you can remove these two lines > switch(pio) > { > case 0: > ctrl0.pio_setup = ATA_PIO0_SETUP; > ctrl0.pio_strb = ATA_PIO0_STROBE; > ctrl0.pio_hold = ATA_PIO0_HOLD; > break; > case 1: > ctrl0.pio_setup = ATA_PIO1_SETUP; > ctrl0.pio_strb = ATA_PIO1_STROBE; > ctrl0.pio_hold = ATA_PIO1_HOLD; > break; > case 2: > ctrl0.pio_setup = ATA_PIO2_SETUP; > ctrl0.pio_strb = ATA_PIO2_STROBE; > ctrl0.pio_hold = ATA_PIO2_HOLD; > break; > case 3: > ctrl0.pio_setup = ATA_PIO3_SETUP; > ctrl0.pio_strb = ATA_PIO3_STROBE; > ctrl0.pio_hold = ATA_PIO3_HOLD; > break; > case 4: > ctrl0.pio_setup = ATA_PIO4_SETUP; > ctrl0.pio_strb = ATA_PIO4_STROBE; > ctrl0.pio_hold = ATA_PIO4_HOLD; > break; > } > > REG_WR(ata, regi_ata, rw_ctrl1, ctrl1); > REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); > } > > static int speed_crisv32_ide(ide_drive_t *drive, byte speed) > { > reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); > reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1); > > switch(speed) > { > case XFER_UDMA_0: > ctrl1.udma_tcyc = ATA_UDMA0_CYC; > ctrl1.udma_tdvs = ATA_UDMA0_DVS; > break; > case XFER_UDMA_1: > ctrl1.udma_tcyc = ATA_UDMA1_CYC; > ctrl1.udma_tdvs = ATA_UDMA1_DVS; > break; > case XFER_UDMA_2: > ctrl1.udma_tcyc = ATA_UDMA2_CYC; > ctrl1.udma_tdvs = ATA_UDMA2_DVS; > break; > case XFER_MW_DMA_2: > ctrl0.dma_strb = ATA_DMA0_STROBE; > ctrl0.dma_hold = ATA_DMA0_HOLD; > break; is this correct: XFER_MW_DMA_2 -> ATA_DMA0_* ? > case XFER_MW_DMA_0: > ctrl0.dma_strb = ATA_DMA2_STROBE; > ctrl0.dma_hold = ATA_DMA2_HOLD; > break; ditto > case XFER_PIO_0: > ctrl0.pio_setup = ATA_PIO0_SETUP; > ctrl0.pio_strb = ATA_PIO0_STROBE; > ctrl0.pio_hold = ATA_PIO0_HOLD; > break; > case XFER_PIO_1: > ctrl0.pio_setup = ATA_PIO1_SETUP; > ctrl0.pio_strb = ATA_PIO1_STROBE; > ctrl0.pio_hold = ATA_PIO1_HOLD; > break; > case XFER_PIO_2: > ctrl0.pio_setup = ATA_PIO2_SETUP; > ctrl0.pio_strb = ATA_PIO2_STROBE; > ctrl0.pio_hold = ATA_PIO2_HOLD; > break; > case XFER_PIO_3: > ctrl0.pio_setup = ATA_PIO3_SETUP; > ctrl0.pio_strb = ATA_PIO3_STROBE; > ctrl0.pio_hold = ATA_PIO3_HOLD; > break; > case XFER_PIO_4: > ctrl0.pio_setup = ATA_PIO4_SETUP; > ctrl0.pio_strb = ATA_PIO4_STROBE; > ctrl0.pio_hold = ATA_PIO4_HOLD; > break; > } PIO setup code is _identical_ to that in tune_crisv32_ide(), speed_crisv32_ide() can be rewritten to use tune_crisv32_ide(): static int speed_crisv32_ide(ide_drive_t *drive, u8 speed) { reg_ata_rw_ctrl0 ctrl0; reg_ata_rw_ctrl1 ctrl1; if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) return tune_crisv32_ide(drive, speed); ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1); ... } > REG_WR(ata, regi_ata, rw_ctrl1, ctrl1); > REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); > > return 0; > } > void __init > init_e100_ide (void) > { > hwif->udma_four = 1; why is host side 80-wires cable flag always set? this controller doesn't even support UDMA > 2 > hwif->sg_table = > kmalloc(sizeof(struct scatterlist) * PRD_ENTRIES, GFP_KERNEL); this will memleak memory as hwif->sg_table is allocated during probe > static int crisv32_ide_build_dmatable (ide_drive_t *drive) > { > ide_hwif_t *hwif = HWIF(drive); please use 'drive->hwif' instead of HWIF() (everywhere) > struct scatterlist* sg; > struct request *rq = HWGROUP(drive)->rq; please use 'drive->hwif->hwgroup' instead of HWGROUP() (everywhere) > if (HWGROUP(drive)->rq->flags & REQ_DRIVE_TASKFILE) { > u8 *virt_addr = rq->buffer; > int sector_count = rq->nr_sectors; > memset(&sg[0], 0, sizeof(*sg)); > sg[0].page = virt_to_page(virt_addr); > sg[0].offset = offset_in_page(virt_addr); > sg[0].length = sector_count * SECTOR_SIZE; > hwif->sg_nents = i = 1; > } > else > { > hwif->sg_nents = i = blk_rq_map_sg(drive->queue, rq, hwif->sg_table); > } above code should be replaced by: ide_map_sg(drive, rq); i = hwif->sg_nents; > static ide_startstop_t crisv32_dma_intr (ide_drive_t *drive) > { > int i, dma_stat; > byte stat; > > LED_DISK_READ(0); > LED_DISK_WRITE(0); > > dma_stat = HWIF(drive)->ide_dma_end(drive); > stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */ > if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { > if (!dma_stat) { > struct request *rq; > rq = HWGROUP(drive)->rq; > for (i = rq->nr_sectors; i > 0;) { > i -= rq->current_nr_sectors; > DRIVER(drive)->end_request(drive, 1, rq->nr_sectors); > } > return ide_stopped; > } > printk("%s: bad DMA status\n", drive->name); > } > return ide_error(drive, "dma_intr", stat); > } this won't even compile with 2.6.12-rc6 (DRIVER() was removed), besides crisv32_dma_intr() can be much simpler: static ide_startstop_t crisv32_dma_intr(ide_drive_t *drive) { LED_DISK_READ(0); LED_DISK_WRITE(0); return ide_dma_intr(drive); } It may be reasonable to merge ide-v10.c and ide-v32.c drivers (using macros to abstract differences etc.) but without seeing register layout for v32 I can't tell for sure (hint: missing include files). Thanks, Bartlomiej [-- Attachment #2: ide-v32.c --] [-- Type: application/octet-stream, Size: 22348 bytes --] /* $Id: ide-v32.c,v 1.6 2005/06/09 12:40:48 starvik Exp $ * * Etrax specific IDE functions, like init and PIO-mode setting etc. * Almost the entire ide.c is used for the rest of the Etrax ATA driver. * Copyright (c) 2000-2004 Axis Communications AB * * Authors: Bjorn Wesen (initial version) * Mikael Starvik (crisv32 port) */ /* Regarding DMA: * * There are two forms of DMA - "DMA handshaking" between the interface and the drive, * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's * something built-in in the Etrax. However only some drives support the DMA-mode handshaking * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the * device can't do DMA handshaking for some stupid reason. We don't need to do that. */ #undef REALLY_SLOW_IO /* most systems can safely undef this */ #include <linux/config.h> #include <linux/types.h> #include <linux/kernel.h> #include <linux/timer.h> #include <linux/mm.h> #include <linux/interrupt.h> #include <linux/delay.h> #include <linux/blkdev.h> #include <linux/hdreg.h> #include <linux/ide.h> #include <linux/init.h> #include <asm/io.h> #include <asm/arch/hwregs/ata_defs.h> #include <asm/arch/hwregs/dma_defs.h> #include <asm/arch/hwregs/dma.h> #include <asm/dma.h> #include <asm/arch/pinmux.h> /* number of DMA descriptors */ #define MAX_DMA_DESCRS 64 /* number of times to retry busy-flags when reading/writing IDE-registers * this can't be too high because a hung harddisk might cause the watchdog * to trigger (sometimes INB and OUTB are called with irq's disabled) */ #define IDE_REGISTER_TIMEOUT 300 #define LOWDB(x) #define D(x) int crisv32_ide_ack_intr(ide_hwif_t* hwif) { reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, hwif->io_ports[0]); REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel); return 1; } void crisv32_ide_outw(unsigned short data, unsigned long reg) { int timeleft; reg_ata_rs_stat_data stat_data; LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg)); /* note the lack of handling any timeouts. we stop waiting, but we don't * really notify anybody. */ timeleft = IDE_REGISTER_TIMEOUT; /* wait for busy flag */ do { timeleft--; stat_data = REG_RD(ata, regi_ata, rs_stat_data); } while(timeleft && stat_data.busy); /* * Fall through at a timeout, so the ongoing command will be * aborted by the write below, which is expected to be a dummy * command to the command register. This happens when a faulty * drive times out on a command. See comment on timeout in * INB. */ if(!timeleft) printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data); REG_WR_INT(ata, regi_ata, rw_ctrl2, reg | data); /* write data to the drive's register */ timeleft = IDE_REGISTER_TIMEOUT; /* wait for transmitter ready */ do { timeleft--; stat_data = REG_RD(ata, regi_ata, rs_stat_data); } while(timeleft && stat_data.busy); } void crisv32_ide_outb(unsigned char data, unsigned long reg) { crisv32_ide_outw(data, reg); } void crisv32_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port) { crisv32_ide_outw(addr, port); } unsigned short crisv32_ide_inw(unsigned long reg) { int timeleft; reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, unsigned long, reg); reg_ata_rs_stat_data stat_data; timeleft = IDE_REGISTER_TIMEOUT; /* wait for busy flag */ do { timeleft--; stat_data = REG_RD(ata, regi_ata, rs_stat_data); } while(timeleft && stat_data.busy); if(!timeleft) { /* * If we're asked to read the status register, like for * example when a command does not complete for an * extended time, but the ATA interface is stuck in a * busy state at the *ETRAX* ATA interface level (as has * happened repeatedly with at least one bad disk), then * the best thing to do is to pretend that we read * "busy" in the status register, so the IDE driver will * time-out, abort the ongoing command and perform a * reset sequence. Note that the subsequent OUT_BYTE * call will also timeout on busy, but as long as the * write is still performed, everything will be fine. */ if (ctrl2.addr == IDE_STATUS_OFFSET) return BUSY_STAT; else /* For other rare cases we assume 0 is good enough. */ return 0; } ctrl2.rw = regk_ata_rd; REG_WR(ata, regi_ata, rw_ctrl2, ctrl2); timeleft = IDE_REGISTER_TIMEOUT; /* wait for available */ do { timeleft--; stat_data = REG_RD(ata, regi_ata, rs_stat_data); } while(timeleft && !stat_data.dav); if(!timeleft) return 0; LOWDB(printk("inb: 0x%x from reg 0x%x\n", stat_data.data & 0xff, reg)); return (unsigned short)stat_data.data; } unsigned char crisv32_ide_inb(unsigned long reg) { return (unsigned char)crisv32_ide_inw(reg); } #define ATA_UDMA2_CYC 2 #define ATA_UDMA2_DVS 3 #define ATA_UDMA1_CYC 2 #define ATA_UDMA1_DVS 4 #define ATA_UDMA0_CYC 4 #define ATA_UDMA0_DVS 6 #define ATA_DMA2_STROBE 7 #define ATA_DMA2_HOLD 1 #define ATA_DMA1_STROBE 8 #define ATA_DMA1_HOLD 3 #define ATA_DMA0_STROBE 25 #define ATA_DMA0_HOLD 19 #define ATA_PIO4_SETUP 3 #define ATA_PIO4_STROBE 7 #define ATA_PIO4_HOLD 1 #define ATA_PIO3_SETUP 3 #define ATA_PIO3_STROBE 9 #define ATA_PIO3_HOLD 3 #define ATA_PIO2_SETUP 3 #define ATA_PIO2_STROBE 13 #define ATA_PIO2_HOLD 5 #define ATA_PIO1_SETUP 5 #define ATA_PIO1_STROBE 23 #define ATA_PIO1_HOLD 9 #define ATA_PIO0_SETUP 9 #define ATA_PIO0_STROBE 39 #define ATA_PIO0_HOLD 9 static int crisv32_dma_check (ide_drive_t *drive); static int crisv32_dma_end (ide_drive_t *drive); static int crisv32_dma_setup (ide_drive_t *drive); static void crisv32_dma_exec_cmd (ide_drive_t *drive, u8 command); static int crisv32_dma_test_irq(ide_drive_t *drive); static void crisv32_dma_start(ide_drive_t *drive); static void crisv32_ide_input_data (ide_drive_t *drive, void *, unsigned int); static void crisv32_ide_output_data (ide_drive_t *drive, void *, unsigned int); static void crisv32_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int); static void crisv32_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int); static int crisv32_dma_off (ide_drive_t *drive); static int crisv32_dma_on (ide_drive_t *drive); static void tune_crisv32_ide(ide_drive_t *drive, u8 pio) { reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); switch(pio) { case 0: ctrl0.pio_setup = ATA_PIO0_SETUP; ctrl0.pio_strb = ATA_PIO0_STROBE; ctrl0.pio_hold = ATA_PIO0_HOLD; break; case 1: ctrl0.pio_setup = ATA_PIO1_SETUP; ctrl0.pio_strb = ATA_PIO1_STROBE; ctrl0.pio_hold = ATA_PIO1_HOLD; break; case 2: ctrl0.pio_setup = ATA_PIO2_SETUP; ctrl0.pio_strb = ATA_PIO2_STROBE; ctrl0.pio_hold = ATA_PIO2_HOLD; break; case 3: ctrl0.pio_setup = ATA_PIO3_SETUP; ctrl0.pio_strb = ATA_PIO3_STROBE; ctrl0.pio_hold = ATA_PIO3_HOLD; break; case 4: ctrl0.pio_setup = ATA_PIO4_SETUP; ctrl0.pio_strb = ATA_PIO4_STROBE; ctrl0.pio_hold = ATA_PIO4_HOLD; break; } REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); } static int speed_crisv32_ide(ide_drive_t *drive, u8 speed) { reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1); if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) { tune_crisv32_ide(drive, speed - XFER_PIO_0); return 0; } switch(speed) { case XFER_UDMA_0: ctrl1.udma_tcyc = ATA_UDMA0_CYC; ctrl1.udma_tdvs = ATA_UDMA0_DVS; break; case XFER_UDMA_1: ctrl1.udma_tcyc = ATA_UDMA1_CYC; ctrl1.udma_tdvs = ATA_UDMA1_DVS; break; case XFER_UDMA_2: ctrl1.udma_tcyc = ATA_UDMA2_CYC; ctrl1.udma_tdvs = ATA_UDMA2_DVS; break; case XFER_MW_DMA_0: ctrl0.dma_strb = ATA_DMA0_STROBE; ctrl0.dma_hold = ATA_DMA0_HOLD; break; case XFER_MW_DMA_1: ctrl0.dma_strb = ATA_DMA1_STROBE; ctrl0.dma_hold = ATA_DMA1_HOLD; break; case XFER_MW_DMA_2: ctrl0.dma_strb = ATA_DMA2_STROBE; ctrl0.dma_hold = ATA_DMA2_HOLD; break; } REG_WR(ata, regi_ata, rw_ctrl1, ctrl1); REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); return 0; } void __init init_e100_ide (void) { reg_ata_rw_ctrl0 ctrl0 = {0}; reg_ata_rw_ctrl1 ctrl1 = {0}; reg_ata_rw_intr_mask intr_mask = {0}; hw_regs_t hw; int ide_offsets[IDE_NR_PORTS]; int h; int i; reg_ata_rw_ctrl2 ctrl2 = {0}; printk("ide: ETRAX FS built-in ATA DMA controller\n"); for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { ctrl2.addr = i; ctrl2.cs0 = regk_ata_active; ide_offsets[i] = REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2); } /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */ ctrl2.addr = 6; ctrl2.cs1 = regk_ata_active; ctrl2.cs0 = regk_ata_inactive; ide_offsets[IDE_CONTROL_OFFSET] = REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2); memset(&ctrl2, 0, sizeof(ctrl2)); /* first fill in some stuff in the ide_hwifs fields */ for(h = 0; h < MAX_HWIFS; h++) { reg_ata_rw_ctrl2 ctrl2 = {.sel = h}; ide_hwif_t *hwif = &ide_hwifs[h]; ide_setup_ports(&hw, REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2), ide_offsets, 0, 0, crisv32_ide_ack_intr, ATA_INTR_VECT); ide_register_hw(&hw, &hwif); hwif->mmio = 2; hwif->chipset = ide_etrax100; hwif->tuneproc = &tune_crisv32_ide; hwif->speedproc = &speed_crisv32_ide; hwif->ata_input_data = &crisv32_ide_input_data; hwif->ata_output_data = &crisv32_ide_output_data; hwif->atapi_input_bytes = &crisv32_atapi_input_bytes; hwif->atapi_output_bytes = &crisv32_atapi_output_bytes; hwif->ide_dma_check = &crisv32_dma_check; hwif->ide_dma_end = &crisv32_dma_end; hwif->dma_setup = &crisv32_dma_setup; hwif->dma_exec_cmd = &crisv32_dma_exec_cmd; hwif->ide_dma_test_irq = &crisv32_dma_test_irq; hwif->dma_start = &crisv32_dma_start; hwif->OUTB = &crisv32_ide_outb; hwif->OUTW = &crisv32_ide_outw; hwif->OUTBSYNC = &crisv32_ide_outbsync; hwif->INB = &crisv32_ide_inb; hwif->INW = &crisv32_ide_inw; hwif->ide_dma_host_off = &crisv32_dma_off; hwif->ide_dma_host_on = &crisv32_dma_on; hwif->ide_dma_off_quietly = &crisv32_dma_off; hwif->udma_four = 0; hwif->ultra_mask = 0x07; /* UDMA 0-2 */ hwif->mwdma_mask = 0x07; /* Multiword DMA 0-2 */ hwif->swdma_mask = 0x07; /* Singleword DMA 0-2 */ } /* actually reset and configure the crisv32 ide/ata interface */ REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); /* pull the chosen /reset-line low */ ctrl0.rst = regk_ata_active; REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); /* wait some */ udelay(25); /* de-assert bus-reset */ ctrl0.rst = regk_ata_inactive; REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); ctrl0.en = regk_ata_yes; ctrl0.dma_strb = ATA_DMA2_STROBE; ctrl0.dma_hold = ATA_DMA2_HOLD; ctrl0.pio_setup = ATA_PIO4_SETUP; ctrl0.pio_strb = ATA_PIO4_STROBE; ctrl0.pio_hold = ATA_PIO4_HOLD; REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); ctrl1.udma_tcyc = ATA_UDMA2_CYC; ctrl1.udma_tdvs = ATA_UDMA2_DVS; REG_WR(ata, regi_ata, rw_ctrl1, ctrl1); intr_mask.bus0 = regk_ata_yes; intr_mask.bus1 = regk_ata_yes; intr_mask.bus2 = regk_ata_yes; intr_mask.bus3 = regk_ata_yes; REG_WR(ata, regi_ata, rw_intr_mask, intr_mask); crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata); crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata); crisv32_pinmux_alloc_fixed(pinmux_ata); crisv32_pinmux_alloc_fixed(pinmux_ata0); crisv32_pinmux_alloc_fixed(pinmux_ata1); crisv32_pinmux_alloc_fixed(pinmux_ata2); crisv32_pinmux_alloc_fixed(pinmux_ata3); DMA_RESET(regi_dma2); DMA_ENABLE(regi_dma2); DMA_RESET(regi_dma3); DMA_ENABLE(regi_dma3); DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2); DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2); } static int crisv32_dma_off (ide_drive_t *drive) { return 0; } static int crisv32_dma_on (ide_drive_t *drive) { return 0; } static dma_descr_context mycontext __attribute__ ((__aligned__(32))); static dma_descr_data mydescr __attribute__ ((__aligned__(16))); /* * The following routines are mainly used by the ATAPI drivers. * * These routines will round up any request for an odd number of bytes, * so if an odd bytecount is specified, be sure that there's at least one * extra byte allocated for the buffer. */ static void crisv32_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) { reg_ata_rw_trf_cnt trf_cnt = {0}; reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG); reg_dma_rw_stat status; unsigned char* d; D(printk("atapi_input_bytes, buffer 0x%x, count %d\n", buffer, bytecount)); if(bytecount & 1) { printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount); bytecount++; /* to round off */ } /* setup DMA descriptor */ mydescr.eol = 1; mydescr.buf = (char*)virt_to_phys(buffer); mydescr.after = mydescr.buf + bytecount; mycontext.saved_data = (dma_descr_data*)virt_to_phys(&mydescr); mycontext.saved_data_buf = mydescr.buf; /* start the dma channel */ DMA_START_CONTEXT(regi_dma3, virt_to_phys(&mycontext)); /* initiate a multi word dma read using PIO handshaking */ trf_cnt.cnt = bytecount >> 1; REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt); d = buffer; ctrl2.rw = regk_ata_rd; ctrl2.trf_mode = regk_ata_dma; ctrl2.hsh = regk_ata_pio; ctrl2.multi = regk_ata_yes; ctrl2.dma_size = regk_ata_word; REG_WR(ata, regi_ata, rw_ctrl2, ctrl2); /* wait for completion */ LED_DISK_READ(1); do { status = REG_RD(dma, regi_dma3, rw_stat); } while(status.list_state != regk_dma_data_at_eol); LED_DISK_READ(0); } static void crisv32_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount) { reg_ata_rw_trf_cnt trf_cnt = {0}; reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG); reg_dma_rw_stat status; D(printk("atapi_output_bytes, dreg 0x%x, buffer 0x%x, count %d\n", 0, buffer, bytecount)); if(bytecount & 1) { printk("odd bytecount %d in atapi_out_bytes!\n", bytecount); bytecount++; } /* setup DMA descriptor */ mydescr.eol = 1; mydescr.buf = (char*)virt_to_phys(buffer); mydescr.after = mydescr.buf + bytecount; mycontext.saved_data = (dma_descr_data*)virt_to_phys(&mydescr); mycontext.saved_data_buf = mydescr.buf; /* start the dma channel */ DMA_START_CONTEXT(regi_dma2, virt_to_phys(&mycontext)); /* initiate a multi word dma write using PIO handshaking */ trf_cnt.cnt = bytecount >> 1; REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt); ctrl2.rw = regk_ata_wr; ctrl2.trf_mode = regk_ata_dma; ctrl2.hsh = regk_ata_pio; ctrl2.multi = regk_ata_yes; ctrl2.dma_size = regk_ata_word; REG_WR(ata, regi_ata, rw_ctrl2, ctrl2); /* wait for completion */ LED_DISK_WRITE(1); LED_DISK_READ(1); do { status = REG_RD(dma, regi_dma2, rw_stat); } while(status.list_state != regk_dma_data_at_eol); LED_DISK_WRITE(0); } /* * This is used for most PIO data transfers *from* the IDE interface */ static void crisv32_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount) { crisv32_atapi_input_bytes(drive, buffer, wcount << 2); } /* * This is used for most PIO data transfers *to* the IDE interface */ static void crisv32_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount) { crisv32_atapi_output_bytes(drive, buffer, wcount << 2); } /* we only have one DMA channel on the chip for ATA, so we can keep these statically */ static dma_descr_data ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16))); static unsigned int ata_tot_size; /* * crisv32_ide_build_dmatable() prepares a dma request. * Returns 0 if all went okay, returns 1 otherwise. */ static int crisv32_ide_build_dmatable (ide_drive_t *drive) { ide_hwif_t *hwif = drive->hwif; struct scatterlist* sg; struct request *rq = drive->hwif->hwgroup->rq; unsigned long size, addr; unsigned int count = 0; int i = 0; sg = hwif->sg_table; ata_tot_size = 0; ide_map_sg(drive, rq); i = hwif->sg_nents; while(i) { /* * Determine addr and size of next buffer area. We assume that * individual virtual buffers are always composed linearly in * physical memory. For example, we assume that any 8kB buffer * is always composed of two adjacent physical 4kB pages rather * than two possibly non-adjacent physical 4kB pages. */ /* group sequential buffers into one large buffer */ addr = page_to_phys(sg->page) + sg->offset; size = sg_dma_len(sg); while (sg++, --i) { if ((addr + size) != page_to_phys(sg->page) + sg->offset) break; size += sg_dma_len(sg); } /* did we run out of descriptors? */ if(count >= MAX_DMA_DESCRS) { printk("%s: too few DMA descriptors\n", drive->name); return 1; } /* however, this case is more difficult - rw_trf_cnt cannot be more than 65536 words per transfer, so in that case we need to either 1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with the descriptors, or 2) simply do the request here, and get dma_intr to only ide_end_request on those blocks that were actually set-up for transfer. */ if(ata_tot_size + size > 131072) { printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size); return 1; } ata_descrs[count].eol = 0; ata_descrs[count].buf = (char*)addr; ata_descrs[count].after = ata_descrs[count].buf + size; ata_descrs[count].next = (dma_descr_data*)virt_to_phys(&ata_descrs[count + 1]); count++; ata_tot_size += size; } if (count) { /* set the end-of-list flag on the last descriptor */ ata_descrs[count - 1].eol = 1; /* return and say all is ok */ return 0; } printk("%s: empty DMA table?\n", drive->name); return 1; /* let the PIO routines handle this weirdness */ } static int config_drive_for_dma (ide_drive_t *drive) { struct hd_driveid *id = drive->id; if (id && (id->capability & 1)) { /* Enable DMA on any drive that supports mword2 DMA */ if ((id->field_valid & 2) && ((id->dma_mword & 0xff00) || (id->dma_ultra & 0xff00))) { drive->using_dma = 1; return 0; /* DMA enabled */ } } drive->using_dma = 0; return 0; /* DMA not enabled */ } /* * crisv32_dma_intr() is the handler for disk read/write DMA interrupts */ static ide_startstop_t crisv32_dma_intr (ide_drive_t *drive) { LED_DISK_READ(0); LED_DISK_WRITE(0); return ide_dma_intr(drive); } /* * Functions below initiates/aborts DMA read/write operations on a drive. * * The caller is assumed to have selected the drive and programmed the drive's * sector address using CHS or LBA. All that remains is to prepare for DMA * and then issue the actual read/write DMA/PIO command to the drive. * * For ATAPI devices, we just prepare for DMA and return. The caller should * then issue the packet command to the drive and call us again with * ide_dma_begin afterwards. * * Returns 0 if all went well. * Returns 1 if DMA read/write could not be started, in which case * the caller should revert to PIO for the current request. */ static int crisv32_dma_check(ide_drive_t *drive) { int speed = ide_dma_speed(drive, 0); /* No UDMA for now */ speed_crisv32_ide(drive, speed); ide_config_drive_speed(drive, speed); return config_drive_for_dma (drive); } static int crisv32_dma_end(ide_drive_t *drive) { drive->waiting_for_dma = 0; return 0; } static int crisv32_prepare_dma(ide_drive_t *drive, int atapi, int reading) { struct request *rq = drive->hwif->hwgroup->rq; if (crisv32_ide_build_dmatable (drive)) { ide_map_sg(drive, rq); return 1; } return 0; } static int crisv32_dma_setup(ide_drive_t *drive) { struct request *rq = drive->hwif->hwgroup->rq; int ret; if (rq_data_dir(rq)) ret = crisv32_prepare_dma(drive, 0, 0); else ret = crisv32_prepare_dma(drive, 0, 1); if (ret) return ret; drive->waiting_for_dma = 1; return 0; } static void crisv32_dma_exec_cmd(ide_drive_t *drive, u8 command) { /* set the irq handler which will finish the request when DMA is done */ ide_set_handler(drive, &crisv32_dma_intr, WAIT_CMD, NULL); /* issue cmd to drive */ crisv32_ide_outb(command, IDE_COMMAND_REG); } static int crisv32_dma_test_irq(ide_drive_t *drive) { int intr = REG_RD_INT(ata, regi_ata, r_intr); reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG); return intr & (1 << ctrl2.sel) ? 1 : 0; } static void crisv32_dma_start(ide_drive_t *drive) { struct request *rq = drive->hwif->hwgroup->rq; reg_ata_rw_trf_cnt trf_cnt = {0}; int writing = rq_data_dir(rq); reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG); /* initiate a multi word dma read using DMA handshaking */ mycontext.saved_data = (dma_descr_data*)virt_to_phys(&ata_descrs[0]); mycontext.saved_data_buf = ata_descrs[0].buf; if (writing) DMA_START_CONTEXT(regi_dma2, virt_to_phys(&mycontext)); else DMA_START_CONTEXT(regi_dma3, virt_to_phys(&mycontext)); trf_cnt.cnt = ata_tot_size >> 1; ctrl2.rw = writing ? regk_ata_wr : regk_ata_rd; ctrl2.trf_mode = regk_ata_dma; if (drive->current_speed >= XFER_UDMA_0) { /* Due to a "feature" the transfer count has to be one extra word for UDMA. */ trf_cnt.cnt++; ctrl2.hsh = regk_ata_udma; } else ctrl2.hsh = regk_ata_dma; ctrl2.multi = regk_ata_yes; ctrl2.dma_size = regk_ata_word; REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt); REG_WR(ata, regi_ata, rw_ctrl2, ctrl2); if (writing) { LED_DISK_WRITE(1); } else { LED_DISK_READ(1); } } [-- Attachment #3: dma_defs.h --] [-- Type: application/octet-stream, Size: 14548 bytes --] #ifndef __dma_defs_h #define __dma_defs_h /* * This file is autogenerated from * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp * last modfied: Mon Apr 11 16:06:51 2005 * * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r * id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ * Any changes here will be lost. * * -*- buffer-read-only: t -*- */ /* Main access macros */ #ifndef REG_RD #define REG_RD( scope, inst, reg ) \ REG_READ( reg_##scope##_##reg, \ (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_WR #define REG_WR( scope, inst, reg, val ) \ REG_WRITE( reg_##scope##_##reg, \ (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) #endif #ifndef REG_RD_VECT #define REG_RD_VECT( scope, inst, reg, index ) \ REG_READ( reg_##scope##_##reg, \ (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif #ifndef REG_WR_VECT #define REG_WR_VECT( scope, inst, reg, index, val ) \ REG_WRITE( reg_##scope##_##reg, \ (inst) + REG_WR_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg, (val) ) #endif #ifndef REG_RD_INT #define REG_RD_INT( scope, inst, reg ) \ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_WR_INT #define REG_WR_INT( scope, inst, reg, val ) \ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) #endif #ifndef REG_RD_INT_VECT #define REG_RD_INT_VECT( scope, inst, reg, index ) \ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif #ifndef REG_WR_INT_VECT #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg, (val) ) #endif #ifndef REG_TYPE_CONV #define REG_TYPE_CONV( type, orgtype, val ) \ ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) #endif #ifndef reg_page_size #define reg_page_size 8192 #endif #ifndef REG_ADDR #define REG_ADDR( scope, inst, reg ) \ ( (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_ADDR_VECT #define REG_ADDR_VECT( scope, inst, reg, index ) \ ( (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif /* C-code for register scope dma */ /* Register rw_data, scope dma, type rw */ typedef unsigned int reg_dma_rw_data; #define REG_RD_ADDR_dma_rw_data 0 #define REG_WR_ADDR_dma_rw_data 0 /* Register rw_data_next, scope dma, type rw */ typedef unsigned int reg_dma_rw_data_next; #define REG_RD_ADDR_dma_rw_data_next 4 #define REG_WR_ADDR_dma_rw_data_next 4 /* Register rw_data_buf, scope dma, type rw */ typedef unsigned int reg_dma_rw_data_buf; #define REG_RD_ADDR_dma_rw_data_buf 8 #define REG_WR_ADDR_dma_rw_data_buf 8 /* Register rw_data_ctrl, scope dma, type rw */ typedef struct { unsigned int eol : 1; unsigned int dummy1 : 2; unsigned int out_eop : 1; unsigned int intr : 1; unsigned int wait : 1; unsigned int dummy2 : 26; } reg_dma_rw_data_ctrl; #define REG_RD_ADDR_dma_rw_data_ctrl 12 #define REG_WR_ADDR_dma_rw_data_ctrl 12 /* Register rw_data_stat, scope dma, type rw */ typedef struct { unsigned int dummy1 : 3; unsigned int in_eop : 1; unsigned int dummy2 : 28; } reg_dma_rw_data_stat; #define REG_RD_ADDR_dma_rw_data_stat 16 #define REG_WR_ADDR_dma_rw_data_stat 16 /* Register rw_data_md, scope dma, type rw */ typedef struct { unsigned int md : 16; unsigned int dummy1 : 16; } reg_dma_rw_data_md; #define REG_RD_ADDR_dma_rw_data_md 20 #define REG_WR_ADDR_dma_rw_data_md 20 /* Register rw_data_md_s, scope dma, type rw */ typedef struct { unsigned int md_s : 16; unsigned int dummy1 : 16; } reg_dma_rw_data_md_s; #define REG_RD_ADDR_dma_rw_data_md_s 24 #define REG_WR_ADDR_dma_rw_data_md_s 24 /* Register rw_data_after, scope dma, type rw */ typedef unsigned int reg_dma_rw_data_after; #define REG_RD_ADDR_dma_rw_data_after 28 #define REG_WR_ADDR_dma_rw_data_after 28 /* Register rw_ctxt, scope dma, type rw */ typedef unsigned int reg_dma_rw_ctxt; #define REG_RD_ADDR_dma_rw_ctxt 32 #define REG_WR_ADDR_dma_rw_ctxt 32 /* Register rw_ctxt_next, scope dma, type rw */ typedef unsigned int reg_dma_rw_ctxt_next; #define REG_RD_ADDR_dma_rw_ctxt_next 36 #define REG_WR_ADDR_dma_rw_ctxt_next 36 /* Register rw_ctxt_ctrl, scope dma, type rw */ typedef struct { unsigned int eol : 1; unsigned int dummy1 : 3; unsigned int intr : 1; unsigned int dummy2 : 1; unsigned int store_mode : 1; unsigned int en : 1; unsigned int dummy3 : 24; } reg_dma_rw_ctxt_ctrl; #define REG_RD_ADDR_dma_rw_ctxt_ctrl 40 #define REG_WR_ADDR_dma_rw_ctxt_ctrl 40 /* Register rw_ctxt_stat, scope dma, type rw */ typedef struct { unsigned int dummy1 : 7; unsigned int dis : 1; unsigned int dummy2 : 24; } reg_dma_rw_ctxt_stat; #define REG_RD_ADDR_dma_rw_ctxt_stat 44 #define REG_WR_ADDR_dma_rw_ctxt_stat 44 /* Register rw_ctxt_md0, scope dma, type rw */ typedef struct { unsigned int md0 : 16; unsigned int dummy1 : 16; } reg_dma_rw_ctxt_md0; #define REG_RD_ADDR_dma_rw_ctxt_md0 48 #define REG_WR_ADDR_dma_rw_ctxt_md0 48 /* Register rw_ctxt_md0_s, scope dma, type rw */ typedef struct { unsigned int md0_s : 16; unsigned int dummy1 : 16; } reg_dma_rw_ctxt_md0_s; #define REG_RD_ADDR_dma_rw_ctxt_md0_s 52 #define REG_WR_ADDR_dma_rw_ctxt_md0_s 52 /* Register rw_ctxt_md1, scope dma, type rw */ typedef unsigned int reg_dma_rw_ctxt_md1; #define REG_RD_ADDR_dma_rw_ctxt_md1 56 #define REG_WR_ADDR_dma_rw_ctxt_md1 56 /* Register rw_ctxt_md1_s, scope dma, type rw */ typedef unsigned int reg_dma_rw_ctxt_md1_s; #define REG_RD_ADDR_dma_rw_ctxt_md1_s 60 #define REG_WR_ADDR_dma_rw_ctxt_md1_s 60 /* Register rw_ctxt_md2, scope dma, type rw */ typedef unsigned int reg_dma_rw_ctxt_md2; #define REG_RD_ADDR_dma_rw_ctxt_md2 64 #define REG_WR_ADDR_dma_rw_ctxt_md2 64 /* Register rw_ctxt_md2_s, scope dma, type rw */ typedef unsigned int reg_dma_rw_ctxt_md2_s; #define REG_RD_ADDR_dma_rw_ctxt_md2_s 68 #define REG_WR_ADDR_dma_rw_ctxt_md2_s 68 /* Register rw_ctxt_md3, scope dma, type rw */ typedef unsigned int reg_dma_rw_ctxt_md3; #define REG_RD_ADDR_dma_rw_ctxt_md3 72 #define REG_WR_ADDR_dma_rw_ctxt_md3 72 /* Register rw_ctxt_md3_s, scope dma, type rw */ typedef unsigned int reg_dma_rw_ctxt_md3_s; #define REG_RD_ADDR_dma_rw_ctxt_md3_s 76 #define REG_WR_ADDR_dma_rw_ctxt_md3_s 76 /* Register rw_ctxt_md4, scope dma, type rw */ typedef unsigned int reg_dma_rw_ctxt_md4; #define REG_RD_ADDR_dma_rw_ctxt_md4 80 #define REG_WR_ADDR_dma_rw_ctxt_md4 80 /* Register rw_ctxt_md4_s, scope dma, type rw */ typedef unsigned int reg_dma_rw_ctxt_md4_s; #define REG_RD_ADDR_dma_rw_ctxt_md4_s 84 #define REG_WR_ADDR_dma_rw_ctxt_md4_s 84 /* Register rw_saved_data, scope dma, type rw */ typedef unsigned int reg_dma_rw_saved_data; #define REG_RD_ADDR_dma_rw_saved_data 88 #define REG_WR_ADDR_dma_rw_saved_data 88 /* Register rw_saved_data_buf, scope dma, type rw */ typedef unsigned int reg_dma_rw_saved_data_buf; #define REG_RD_ADDR_dma_rw_saved_data_buf 92 #define REG_WR_ADDR_dma_rw_saved_data_buf 92 /* Register rw_group, scope dma, type rw */ typedef unsigned int reg_dma_rw_group; #define REG_RD_ADDR_dma_rw_group 96 #define REG_WR_ADDR_dma_rw_group 96 /* Register rw_group_next, scope dma, type rw */ typedef unsigned int reg_dma_rw_group_next; #define REG_RD_ADDR_dma_rw_group_next 100 #define REG_WR_ADDR_dma_rw_group_next 100 /* Register rw_group_ctrl, scope dma, type rw */ typedef struct { unsigned int eol : 1; unsigned int tol : 1; unsigned int bol : 1; unsigned int dummy1 : 1; unsigned int intr : 1; unsigned int dummy2 : 2; unsigned int en : 1; unsigned int dummy3 : 24; } reg_dma_rw_group_ctrl; #define REG_RD_ADDR_dma_rw_group_ctrl 104 #define REG_WR_ADDR_dma_rw_group_ctrl 104 /* Register rw_group_stat, scope dma, type rw */ typedef struct { unsigned int dummy1 : 7; unsigned int dis : 1; unsigned int dummy2 : 24; } reg_dma_rw_group_stat; #define REG_RD_ADDR_dma_rw_group_stat 108 #define REG_WR_ADDR_dma_rw_group_stat 108 /* Register rw_group_md, scope dma, type rw */ typedef struct { unsigned int md : 16; unsigned int dummy1 : 16; } reg_dma_rw_group_md; #define REG_RD_ADDR_dma_rw_group_md 112 #define REG_WR_ADDR_dma_rw_group_md 112 /* Register rw_group_md_s, scope dma, type rw */ typedef struct { unsigned int md_s : 16; unsigned int dummy1 : 16; } reg_dma_rw_group_md_s; #define REG_RD_ADDR_dma_rw_group_md_s 116 #define REG_WR_ADDR_dma_rw_group_md_s 116 /* Register rw_group_up, scope dma, type rw */ typedef unsigned int reg_dma_rw_group_up; #define REG_RD_ADDR_dma_rw_group_up 120 #define REG_WR_ADDR_dma_rw_group_up 120 /* Register rw_group_down, scope dma, type rw */ typedef unsigned int reg_dma_rw_group_down; #define REG_RD_ADDR_dma_rw_group_down 124 #define REG_WR_ADDR_dma_rw_group_down 124 /* Register rw_cmd, scope dma, type rw */ typedef struct { unsigned int cont_data : 1; unsigned int dummy1 : 31; } reg_dma_rw_cmd; #define REG_RD_ADDR_dma_rw_cmd 128 #define REG_WR_ADDR_dma_rw_cmd 128 /* Register rw_cfg, scope dma, type rw */ typedef struct { unsigned int en : 1; unsigned int stop : 1; unsigned int dummy1 : 30; } reg_dma_rw_cfg; #define REG_RD_ADDR_dma_rw_cfg 132 #define REG_WR_ADDR_dma_rw_cfg 132 /* Register rw_stat, scope dma, type rw */ typedef struct { unsigned int mode : 5; unsigned int list_state : 3; unsigned int stream_cmd_src : 8; unsigned int dummy1 : 8; unsigned int buf : 8; } reg_dma_rw_stat; #define REG_RD_ADDR_dma_rw_stat 136 #define REG_WR_ADDR_dma_rw_stat 136 /* Register rw_intr_mask, scope dma, type rw */ typedef struct { unsigned int group : 1; unsigned int ctxt : 1; unsigned int data : 1; unsigned int in_eop : 1; unsigned int stream_cmd : 1; unsigned int dummy1 : 27; } reg_dma_rw_intr_mask; #define REG_RD_ADDR_dma_rw_intr_mask 140 #define REG_WR_ADDR_dma_rw_intr_mask 140 /* Register rw_ack_intr, scope dma, type rw */ typedef struct { unsigned int group : 1; unsigned int ctxt : 1; unsigned int data : 1; unsigned int in_eop : 1; unsigned int stream_cmd : 1; unsigned int dummy1 : 27; } reg_dma_rw_ack_intr; #define REG_RD_ADDR_dma_rw_ack_intr 144 #define REG_WR_ADDR_dma_rw_ack_intr 144 /* Register r_intr, scope dma, type r */ typedef struct { unsigned int group : 1; unsigned int ctxt : 1; unsigned int data : 1; unsigned int in_eop : 1; unsigned int stream_cmd : 1; unsigned int dummy1 : 27; } reg_dma_r_intr; #define REG_RD_ADDR_dma_r_intr 148 /* Register r_masked_intr, scope dma, type r */ typedef struct { unsigned int group : 1; unsigned int ctxt : 1; unsigned int data : 1; unsigned int in_eop : 1; unsigned int stream_cmd : 1; unsigned int dummy1 : 27; } reg_dma_r_masked_intr; #define REG_RD_ADDR_dma_r_masked_intr 152 /* Register rw_stream_cmd, scope dma, type rw */ typedef struct { unsigned int cmd : 10; unsigned int dummy1 : 6; unsigned int n : 8; unsigned int dummy2 : 7; unsigned int busy : 1; } reg_dma_rw_stream_cmd; #define REG_RD_ADDR_dma_rw_stream_cmd 156 #define REG_WR_ADDR_dma_rw_stream_cmd 156 /* Constants */ enum { regk_dma_ack_pkt = 0x00000100, regk_dma_anytime = 0x00000001, regk_dma_array = 0x00000008, regk_dma_burst = 0x00000020, regk_dma_client = 0x00000002, regk_dma_copy_next = 0x00000010, regk_dma_copy_up = 0x00000020, regk_dma_data_at_eol = 0x00000001, regk_dma_dis_c = 0x00000010, regk_dma_dis_g = 0x00000020, regk_dma_idle = 0x00000001, regk_dma_intern = 0x00000004, regk_dma_load_c = 0x00000200, regk_dma_load_c_n = 0x00000280, regk_dma_load_c_next = 0x00000240, regk_dma_load_d = 0x00000140, regk_dma_load_g = 0x00000300, regk_dma_load_g_down = 0x000003c0, regk_dma_load_g_next = 0x00000340, regk_dma_load_g_up = 0x00000380, regk_dma_next_en = 0x00000010, regk_dma_next_pkt = 0x00000010, regk_dma_no = 0x00000000, regk_dma_only_at_wait = 0x00000000, regk_dma_restore = 0x00000020, regk_dma_rst = 0x00000001, regk_dma_running = 0x00000004, regk_dma_rw_cfg_default = 0x00000000, regk_dma_rw_cmd_default = 0x00000000, regk_dma_rw_intr_mask_default = 0x00000000, regk_dma_rw_stat_default = 0x00000101, regk_dma_rw_stream_cmd_default = 0x00000000, regk_dma_save_down = 0x00000020, regk_dma_save_up = 0x00000020, regk_dma_set_reg = 0x00000050, regk_dma_set_w_size1 = 0x00000190, regk_dma_set_w_size2 = 0x000001a0, regk_dma_set_w_size4 = 0x000001c0, regk_dma_stopped = 0x00000002, regk_dma_store_c = 0x00000002, regk_dma_store_descr = 0x00000000, regk_dma_store_g = 0x00000004, regk_dma_store_md = 0x00000001, regk_dma_sw = 0x00000008, regk_dma_update_down = 0x00000020, regk_dma_yes = 0x00000001 }; #endif /* __dma_defs_h */ [-- Attachment #4: dma.h --] [-- Type: application/octet-stream, Size: 4708 bytes --] /* $Id: dma.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ * * DMA C definitions and help macros * */ #ifndef dma_h #define dma_h /* registers */ /* Really needed, since both are listed in sw.list? */ #include "dma_defs.h" /* descriptors */ // ------------------------------------------------------------ dma_descr_group typedef struct dma_descr_group { struct dma_descr_group *next; unsigned eol : 1; unsigned tol : 1; unsigned bol : 1; unsigned : 1; unsigned intr : 1; unsigned : 2; unsigned en : 1; unsigned : 7; unsigned dis : 1; unsigned md : 16; struct dma_descr_group *up; union { struct dma_descr_context *context; struct dma_descr_group *group; } down; } dma_descr_group; // ---------------------------------------------------------- dma_descr_context typedef struct dma_descr_context { struct dma_descr_context *next; unsigned eol : 1; unsigned : 3; unsigned intr : 1; unsigned : 1; unsigned store_mode : 1; unsigned en : 1; unsigned : 7; unsigned dis : 1; unsigned md0 : 16; unsigned md1; unsigned md2; unsigned md3; unsigned md4; struct dma_descr_data *saved_data; char *saved_data_buf; } dma_descr_context; // ------------------------------------------------------------- dma_descr_data typedef struct dma_descr_data { struct dma_descr_data *next; char *buf; unsigned eol : 1; unsigned : 2; unsigned out_eop : 1; unsigned intr : 1; unsigned wait : 1; unsigned : 2; unsigned : 3; unsigned in_eop : 1; unsigned : 4; unsigned md : 16; char *after; } dma_descr_data; // --------------------------------------------------------------------- macros // enable DMA channel #define DMA_ENABLE( inst ) \ do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\ e.en = regk_dma_yes; \ REG_WR( dma, inst, rw_cfg, e); } while( 0 ) // reset DMA channel #define DMA_RESET( inst ) \ do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\ r.en = regk_dma_no; \ REG_WR( dma, inst, rw_cfg, r); } while( 0 ) // stop DMA channel #define DMA_STOP( inst ) \ do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\ s.stop = regk_dma_yes; \ REG_WR( dma, inst, rw_cfg, s); } while( 0 ) // continue DMA channel operation #define DMA_CONTINUE( inst ) \ do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\ c.stop = regk_dma_no; \ REG_WR( dma, inst, rw_cfg, c); } while( 0 ) // give stream command #define DMA_WR_CMD( inst, cmd_par ) \ do { reg_dma_rw_stream_cmd r = {0}; \ do { r = REG_RD( dma, inst, rw_stream_cmd ); } while( r.busy ); \ r.cmd = (cmd_par); \ REG_WR( dma, inst, rw_stream_cmd, r ); \ } while( 0 ) // load: g,c,d:burst #define DMA_START_GROUP( inst, group_descr ) \ do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \ DMA_WR_CMD( inst, regk_dma_load_g ); \ DMA_WR_CMD( inst, regk_dma_load_c ); \ DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ } while( 0 ) // load: c,d:burst #define DMA_START_CONTEXT( inst, ctx_descr ) \ do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \ DMA_WR_CMD( inst, regk_dma_load_c ); \ DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ } while( 0 ) // if the DMA is at the end of the data list, the last data descr is reloaded #define DMA_CONTINUE_DATA( inst ) \ do { reg_dma_rw_cmd c = {0}; \ c.cont_data = regk_dma_yes;\ REG_WR( dma, inst, rw_cmd, c ); } while( 0 ) #endif [-- Attachment #5: ata_defs.h --] [-- Type: application/octet-stream, Size: 6658 bytes --] #ifndef __ata_defs_h #define __ata_defs_h /* * This file is autogenerated from * file: ../../inst/ata/rtl/ata_regs.r * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp * last modfied: Mon Apr 11 16:06:25 2005 * * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r * id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ * Any changes here will be lost. * * -*- buffer-read-only: t -*- */ /* Main access macros */ #ifndef REG_RD #define REG_RD( scope, inst, reg ) \ REG_READ( reg_##scope##_##reg, \ (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_WR #define REG_WR( scope, inst, reg, val ) \ REG_WRITE( reg_##scope##_##reg, \ (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) #endif #ifndef REG_RD_VECT #define REG_RD_VECT( scope, inst, reg, index ) \ REG_READ( reg_##scope##_##reg, \ (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif #ifndef REG_WR_VECT #define REG_WR_VECT( scope, inst, reg, index, val ) \ REG_WRITE( reg_##scope##_##reg, \ (inst) + REG_WR_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg, (val) ) #endif #ifndef REG_RD_INT #define REG_RD_INT( scope, inst, reg ) \ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_WR_INT #define REG_WR_INT( scope, inst, reg, val ) \ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) #endif #ifndef REG_RD_INT_VECT #define REG_RD_INT_VECT( scope, inst, reg, index ) \ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif #ifndef REG_WR_INT_VECT #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg, (val) ) #endif #ifndef REG_TYPE_CONV #define REG_TYPE_CONV( type, orgtype, val ) \ ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) #endif #ifndef reg_page_size #define reg_page_size 8192 #endif #ifndef REG_ADDR #define REG_ADDR( scope, inst, reg ) \ ( (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_ADDR_VECT #define REG_ADDR_VECT( scope, inst, reg, index ) \ ( (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif /* C-code for register scope ata */ /* Register rw_ctrl0, scope ata, type rw */ typedef struct { unsigned int pio_hold : 6; unsigned int pio_strb : 6; unsigned int pio_setup : 6; unsigned int dma_hold : 6; unsigned int dma_strb : 6; unsigned int rst : 1; unsigned int en : 1; } reg_ata_rw_ctrl0; #define REG_RD_ADDR_ata_rw_ctrl0 12 #define REG_WR_ADDR_ata_rw_ctrl0 12 /* Register rw_ctrl1, scope ata, type rw */ typedef struct { unsigned int udma_tcyc : 4; unsigned int udma_tdvs : 4; unsigned int dummy1 : 24; } reg_ata_rw_ctrl1; #define REG_RD_ADDR_ata_rw_ctrl1 16 #define REG_WR_ADDR_ata_rw_ctrl1 16 /* Register rw_ctrl2, scope ata, type rw */ typedef struct { unsigned int data : 16; unsigned int dummy1 : 3; unsigned int dma_size : 1; unsigned int multi : 1; unsigned int hsh : 2; unsigned int trf_mode : 1; unsigned int rw : 1; unsigned int addr : 3; unsigned int cs0 : 1; unsigned int cs1 : 1; unsigned int sel : 2; } reg_ata_rw_ctrl2; #define REG_RD_ADDR_ata_rw_ctrl2 0 #define REG_WR_ADDR_ata_rw_ctrl2 0 /* Register rs_stat_data, scope ata, type rs */ typedef struct { unsigned int data : 16; unsigned int dav : 1; unsigned int busy : 1; unsigned int dummy1 : 14; } reg_ata_rs_stat_data; #define REG_RD_ADDR_ata_rs_stat_data 4 /* Register r_stat_data, scope ata, type r */ typedef struct { unsigned int data : 16; unsigned int dav : 1; unsigned int busy : 1; unsigned int dummy1 : 14; } reg_ata_r_stat_data; #define REG_RD_ADDR_ata_r_stat_data 8 /* Register rw_trf_cnt, scope ata, type rw */ typedef struct { unsigned int cnt : 17; unsigned int dummy1 : 15; } reg_ata_rw_trf_cnt; #define REG_RD_ADDR_ata_rw_trf_cnt 20 #define REG_WR_ADDR_ata_rw_trf_cnt 20 /* Register r_stat_misc, scope ata, type r */ typedef struct { unsigned int crc : 16; unsigned int dummy1 : 16; } reg_ata_r_stat_misc; #define REG_RD_ADDR_ata_r_stat_misc 24 /* Register rw_intr_mask, scope ata, type rw */ typedef struct { unsigned int bus0 : 1; unsigned int bus1 : 1; unsigned int bus2 : 1; unsigned int bus3 : 1; unsigned int dummy1 : 28; } reg_ata_rw_intr_mask; #define REG_RD_ADDR_ata_rw_intr_mask 28 #define REG_WR_ADDR_ata_rw_intr_mask 28 /* Register rw_ack_intr, scope ata, type rw */ typedef struct { unsigned int bus0 : 1; unsigned int bus1 : 1; unsigned int bus2 : 1; unsigned int bus3 : 1; unsigned int dummy1 : 28; } reg_ata_rw_ack_intr; #define REG_RD_ADDR_ata_rw_ack_intr 32 #define REG_WR_ADDR_ata_rw_ack_intr 32 /* Register r_intr, scope ata, type r */ typedef struct { unsigned int bus0 : 1; unsigned int bus1 : 1; unsigned int bus2 : 1; unsigned int bus3 : 1; unsigned int dummy1 : 28; } reg_ata_r_intr; #define REG_RD_ADDR_ata_r_intr 36 /* Register r_masked_intr, scope ata, type r */ typedef struct { unsigned int bus0 : 1; unsigned int bus1 : 1; unsigned int bus2 : 1; unsigned int bus3 : 1; unsigned int dummy1 : 28; } reg_ata_r_masked_intr; #define REG_RD_ADDR_ata_r_masked_intr 40 /* Constants */ enum { regk_ata_active = 0x00000001, regk_ata_byte = 0x00000001, regk_ata_data = 0x00000001, regk_ata_dma = 0x00000001, regk_ata_inactive = 0x00000000, regk_ata_no = 0x00000000, regk_ata_nodata = 0x00000000, regk_ata_pio = 0x00000000, regk_ata_rd = 0x00000001, regk_ata_reg = 0x00000000, regk_ata_rw_ctrl0_default = 0x00000000, regk_ata_rw_ctrl2_default = 0x00000000, regk_ata_rw_intr_mask_default = 0x00000000, regk_ata_udma = 0x00000002, regk_ata_word = 0x00000000, regk_ata_wr = 0x00000000, regk_ata_yes = 0x00000001 }; #endif /* __ata_defs_h */ ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: New IDE driver for review 2005-06-09 12:54 ` Mikael Starvik @ 2005-06-09 15:10 ` Bartlomiej Zolnierkiewicz 0 siblings, 0 replies; 9+ messages in thread From: Bartlomiej Zolnierkiewicz @ 2005-06-09 15:10 UTC (permalink / raw) To: Mikael Starvik; +Cc: linux-ide On 6/9/05, Mikael Starvik <mikael.starvik@axis.com> wrote: > Ok, updated driver and requested include files attached. Thanks. > The drivers are similar but it would still require many ugly ifdef:s or > similar to combine them. I could of course extract the stuff that is the > same to a common file to make the arch-specific files smaller. These drivers > are rarley touched so I see no major maintanence benefit by combining them. I still would like to see one driver: * less maintenance for IDE people * better readability of ide-v10.c (IDE specific stuff separated from arch specific stuff) * good opportunity to cleanup ide-v10.c a bit this won't require many ugly ifdef's, ie. #ifdef v10 static void etrax_ide_set_pio(u8 setup, u8 strobe, u8 hold) { *R_ATA_CONFIG = IO_FIELD(R_ATA_CONFIG, enable, 1 ) | IO_FIELD(R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE) | IO_FIELD(R_ATA_CONFIG, dma_hold, ATA_DMA2_HOLD) | IO_FIELD(R_ATA_CONFIG, pio_setup, setup) | IO_FIELD(R_ATA_CONFIG, pio_strobe, strobe) | IO_FIELD(R_ATA_CONFIG, pio_hold, hold); } ... #else static void etrax_ide_set_pio(u8 setup, u8 strobe, u8 hold) { reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); ctrl0.pio_setup = setup; ctrl0.pio_strb = strobe; ctrl0.pio_hold = hold; REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); } ... #endif and later just use etrax_ide_set_pio() Bartlomiej ^ permalink raw reply [flat|nested] 9+ messages in thread
* New IDE driver for review
@ 2005-06-09 7:18 Mikael Starvik
2005-06-09 10:14 ` Bartlomiej Zolnierkiewicz
0 siblings, 1 reply; 9+ messages in thread
From: Mikael Starvik @ 2005-06-09 7:18 UTC (permalink / raw)
To: linux-ide
[-- Attachment #1: Type: text/plain, Size: 457 bytes --]
I am about to release a new subarchitecture to the cris architcecture.
A part of this release is a new IDE driver. Basically just a port of
the IDE driver for the old architecture with the addition of UDMA 0-2.
The driver is attached if anyone wants to review it before submission.
I understand if no one is interrested in taking a look at it (CRIS
is really a minor arch).
If no one objects I'll send this to Andrew after the 2.6.12 release.
/Mikael
[-- Attachment #2: ide-v32.c --]
[-- Type: application/octet-stream, Size: 24066 bytes --]
/* $Id: ide-v32.c,v 1.5 2005/06/09 07:11:54 starvik Exp $
*
* Etrax specific IDE functions, like init and PIO-mode setting etc.
* Almost the entire ide.c is used for the rest of the Etrax ATA driver.
* Copyright (c) 2000-2004 Axis Communications AB
*
* Authors: Bjorn Wesen (initial version)
* Mikael Starvik (crisv32 port)
*/
/* Regarding DMA:
*
* There are two forms of DMA - "DMA handshaking" between the interface and the drive,
* and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
* something built-in in the Etrax. However only some drives support the DMA-mode handshaking
* on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
* device can't do DMA handshaking for some stupid reason. We don't need to do that.
*/
#undef REALLY_SLOW_IO /* most systems can safely undef this */
#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>
#include <asm/io.h>
#include <asm/arch/hwregs/ata_defs.h>
#include <asm/arch/hwregs/dma_defs.h>
#include <asm/arch/hwregs/dma.h>
#include <asm/dma.h>
#include <asm/arch/pinmux.h>
/* number of DMA descriptors */
#define MAX_DMA_DESCRS 64
/* number of times to retry busy-flags when reading/writing IDE-registers
* this can't be too high because a hung harddisk might cause the watchdog
* to trigger (sometimes INB and OUTB are called with irq's disabled)
*/
#define IDE_REGISTER_TIMEOUT 300
#define LOWDB(x)
#define D(x)
int crisv32_ide_ack_intr(ide_hwif_t* hwif)
{
reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2,
int, hwif->io_ports[0]);
REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel);
return 1;
}
void
crisv32_ide_outw(unsigned short data, unsigned long reg) {
int timeleft;
reg_ata_rs_stat_data stat_data;
LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg));
/* note the lack of handling any timeouts. we stop waiting, but we don't
* really notify anybody.
*/
timeleft = IDE_REGISTER_TIMEOUT;
/* wait for busy flag */
do {
timeleft--;
stat_data = REG_RD(ata, regi_ata, rs_stat_data);
} while(timeleft && stat_data.busy);
/*
* Fall through at a timeout, so the ongoing command will be
* aborted by the write below, which is expected to be a dummy
* command to the command register. This happens when a faulty
* drive times out on a command. See comment on timeout in
* INB.
*/
if(!timeleft)
printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
REG_WR_INT(ata, regi_ata, rw_ctrl2, reg | data); /* write data to the drive's register */
timeleft = IDE_REGISTER_TIMEOUT;
/* wait for transmitter ready */
do {
timeleft--;
stat_data = REG_RD(ata, regi_ata, rs_stat_data);
} while(timeleft && stat_data.busy);
}
void
crisv32_ide_outb(unsigned char data, unsigned long reg)
{
crisv32_ide_outw(data, reg);
}
void
crisv32_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
{
crisv32_ide_outw(addr, port);
}
unsigned short
crisv32_ide_inw(unsigned long reg) {
int timeleft;
reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, unsigned long, reg);
reg_ata_rs_stat_data stat_data;
timeleft = IDE_REGISTER_TIMEOUT;
/* wait for busy flag */
do {
timeleft--;
stat_data = REG_RD(ata, regi_ata, rs_stat_data);
} while(timeleft && stat_data.busy);
if(!timeleft) {
/*
* If we're asked to read the status register, like for
* example when a command does not complete for an
* extended time, but the ATA interface is stuck in a
* busy state at the *ETRAX* ATA interface level (as has
* happened repeatedly with at least one bad disk), then
* the best thing to do is to pretend that we read
* "busy" in the status register, so the IDE driver will
* time-out, abort the ongoing command and perform a
* reset sequence. Note that the subsequent OUT_BYTE
* call will also timeout on busy, but as long as the
* write is still performed, everything will be fine.
*/
if (ctrl2.addr == IDE_STATUS_OFFSET)
return BUSY_STAT;
else
/* For other rare cases we assume 0 is good enough. */
return 0;
}
ctrl2.rw = regk_ata_rd;
REG_WR(ata, regi_ata, rw_ctrl2, ctrl2);
timeleft = IDE_REGISTER_TIMEOUT;
/* wait for available */
do {
timeleft--;
stat_data = REG_RD(ata, regi_ata, rs_stat_data);
} while(timeleft && !stat_data.dav);
if(!timeleft)
return 0;
LOWDB(printk("inb: 0x%x from reg 0x%x\n", stat_data.data & 0xff, reg));
return (unsigned short)stat_data.data;
}
unsigned char
crisv32_ide_inb(unsigned long reg)
{
return (unsigned char)crisv32_ide_inw(reg);
}
#define ATA_UDMA2_CYC 2
#define ATA_UDMA2_DVS 3
#define ATA_UDMA1_CYC 2
#define ATA_UDMA1_DVS 4
#define ATA_UDMA0_CYC 4
#define ATA_UDMA0_DVS 6
#define ATA_DMA2_STROBE 7
#define ATA_DMA2_HOLD 1
#define ATA_DMA1_STROBE 8
#define ATA_DMA1_HOLD 3
#define ATA_DMA0_STROBE 25
#define ATA_DMA0_HOLD 19
#define ATA_PIO4_SETUP 3
#define ATA_PIO4_STROBE 7
#define ATA_PIO4_HOLD 1
#define ATA_PIO3_SETUP 3
#define ATA_PIO3_STROBE 9
#define ATA_PIO3_HOLD 3
#define ATA_PIO2_SETUP 3
#define ATA_PIO2_STROBE 13
#define ATA_PIO2_HOLD 5
#define ATA_PIO1_SETUP 5
#define ATA_PIO1_STROBE 23
#define ATA_PIO1_HOLD 9
#define ATA_PIO0_SETUP 9
#define ATA_PIO0_STROBE 39
#define ATA_PIO0_HOLD 9
static int crisv32_dma_check (ide_drive_t *drive);
static int crisv32_dma_end (ide_drive_t *drive);
static int crisv32_dma_setup (ide_drive_t *drive);
static void crisv32_dma_exec_cmd (ide_drive_t *drive, u8 command);
static int crisv32_dma_test_irq(ide_drive_t *drive);
static void crisv32_dma_start(ide_drive_t *drive);
static void crisv32_ide_input_data (ide_drive_t *drive, void *, unsigned int);
static void crisv32_ide_output_data (ide_drive_t *drive, void *, unsigned int);
static void crisv32_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int);
static void crisv32_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int);
static int crisv32_dma_off (ide_drive_t *drive);
static int crisv32_dma_on (ide_drive_t *drive);
static void tune_crisv32_ide(ide_drive_t *drive, byte pio)
{
reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0);
reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1);
if (pio <= 4)
pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
switch(pio)
{
case 0:
ctrl0.pio_setup = ATA_PIO0_SETUP;
ctrl0.pio_strb = ATA_PIO0_STROBE;
ctrl0.pio_hold = ATA_PIO0_HOLD;
break;
case 1:
ctrl0.pio_setup = ATA_PIO1_SETUP;
ctrl0.pio_strb = ATA_PIO1_STROBE;
ctrl0.pio_hold = ATA_PIO1_HOLD;
break;
case 2:
ctrl0.pio_setup = ATA_PIO2_SETUP;
ctrl0.pio_strb = ATA_PIO2_STROBE;
ctrl0.pio_hold = ATA_PIO2_HOLD;
break;
case 3:
ctrl0.pio_setup = ATA_PIO3_SETUP;
ctrl0.pio_strb = ATA_PIO3_STROBE;
ctrl0.pio_hold = ATA_PIO3_HOLD;
break;
case 4:
ctrl0.pio_setup = ATA_PIO4_SETUP;
ctrl0.pio_strb = ATA_PIO4_STROBE;
ctrl0.pio_hold = ATA_PIO4_HOLD;
break;
}
REG_WR(ata, regi_ata, rw_ctrl1, ctrl1);
REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
}
static int speed_crisv32_ide(ide_drive_t *drive, byte speed)
{
reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0);
reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1);
switch(speed)
{
case XFER_UDMA_0:
ctrl1.udma_tcyc = ATA_UDMA0_CYC;
ctrl1.udma_tdvs = ATA_UDMA0_DVS;
break;
case XFER_UDMA_1:
ctrl1.udma_tcyc = ATA_UDMA1_CYC;
ctrl1.udma_tdvs = ATA_UDMA1_DVS;
break;
case XFER_UDMA_2:
ctrl1.udma_tcyc = ATA_UDMA2_CYC;
ctrl1.udma_tdvs = ATA_UDMA2_DVS;
break;
case XFER_MW_DMA_2:
ctrl0.dma_strb = ATA_DMA0_STROBE;
ctrl0.dma_hold = ATA_DMA0_HOLD;
break;
case XFER_MW_DMA_1:
ctrl0.dma_strb = ATA_DMA1_STROBE;
ctrl0.dma_hold = ATA_DMA1_HOLD;
break;
case XFER_MW_DMA_0:
ctrl0.dma_strb = ATA_DMA2_STROBE;
ctrl0.dma_hold = ATA_DMA2_HOLD;
break;
case XFER_PIO_0:
ctrl0.pio_setup = ATA_PIO0_SETUP;
ctrl0.pio_strb = ATA_PIO0_STROBE;
ctrl0.pio_hold = ATA_PIO0_HOLD;
break;
case XFER_PIO_1:
ctrl0.pio_setup = ATA_PIO1_SETUP;
ctrl0.pio_strb = ATA_PIO1_STROBE;
ctrl0.pio_hold = ATA_PIO1_HOLD;
break;
case XFER_PIO_2:
ctrl0.pio_setup = ATA_PIO2_SETUP;
ctrl0.pio_strb = ATA_PIO2_STROBE;
ctrl0.pio_hold = ATA_PIO2_HOLD;
break;
case XFER_PIO_3:
ctrl0.pio_setup = ATA_PIO3_SETUP;
ctrl0.pio_strb = ATA_PIO3_STROBE;
ctrl0.pio_hold = ATA_PIO3_HOLD;
break;
case XFER_PIO_4:
ctrl0.pio_setup = ATA_PIO4_SETUP;
ctrl0.pio_strb = ATA_PIO4_STROBE;
ctrl0.pio_hold = ATA_PIO4_HOLD;
break;
}
REG_WR(ata, regi_ata, rw_ctrl1, ctrl1);
REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
return 0;
}
void __init
init_e100_ide (void)
{
reg_ata_rw_ctrl0 ctrl0 = {0};
reg_ata_rw_ctrl1 ctrl1 = {0};
reg_ata_rw_intr_mask intr_mask = {0};
hw_regs_t hw;
int ide_offsets[IDE_NR_PORTS];
int h;
int i;
reg_ata_rw_ctrl2 ctrl2 = {0};
printk("ide: ETRAX FS built-in ATA DMA controller\n");
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
ctrl2.addr = i;
ctrl2.cs0 = regk_ata_active;
ide_offsets[i] = REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
}
/* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */
ctrl2.addr = 6;
ctrl2.cs1 = regk_ata_active;
ctrl2.cs0 = regk_ata_inactive;
ide_offsets[IDE_CONTROL_OFFSET] = REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
memset(&ctrl2, 0, sizeof(ctrl2));
/* first fill in some stuff in the ide_hwifs fields */
for(h = 0; h < MAX_HWIFS; h++) {
reg_ata_rw_ctrl2 ctrl2 = {.sel = h};
ide_hwif_t *hwif = &ide_hwifs[h];
ide_setup_ports(&hw, REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2),
ide_offsets,
0, 0, crisv32_ide_ack_intr,
ATA_INTR_VECT);
ide_register_hw(&hw, &hwif);
hwif->mmio = 2;
hwif->chipset = ide_etrax100;
hwif->tuneproc = &tune_crisv32_ide;
hwif->speedproc = &speed_crisv32_ide;
hwif->ata_input_data = &crisv32_ide_input_data;
hwif->ata_output_data = &crisv32_ide_output_data;
hwif->atapi_input_bytes = &crisv32_atapi_input_bytes;
hwif->atapi_output_bytes = &crisv32_atapi_output_bytes;
hwif->ide_dma_check = &crisv32_dma_check;
hwif->ide_dma_end = &crisv32_dma_end;
hwif->dma_setup = &crisv32_dma_setup;
hwif->dma_exec_cmd = &crisv32_dma_exec_cmd;
hwif->ide_dma_test_irq = &crisv32_dma_test_irq;
hwif->dma_start = &crisv32_dma_start;
hwif->OUTB = &crisv32_ide_outb;
hwif->OUTW = &crisv32_ide_outw;
hwif->OUTBSYNC = &crisv32_ide_outbsync;
hwif->INB = &crisv32_ide_inb;
hwif->INW = &crisv32_ide_inw;
hwif->ide_dma_host_off = &crisv32_dma_off;
hwif->ide_dma_host_on = &crisv32_dma_on;
hwif->ide_dma_off_quietly = &crisv32_dma_off;
hwif->udma_four = 1;
hwif->ultra_mask = 0x07; /* UDMA 0-2 */
hwif->mwdma_mask = 0x07; /* Multiword DMA 0-2 */
hwif->swdma_mask = 0x07; /* Singleword DMA 0-2 */
hwif->sg_table =
kmalloc(sizeof(struct scatterlist) * PRD_ENTRIES, GFP_KERNEL);
}
/* actually reset and configure the crisv32 ide/ata interface */
REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
/* pull the chosen /reset-line low */
ctrl0.rst = regk_ata_active;
REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
/* wait some */
udelay(25);
/* de-assert bus-reset */
ctrl0.rst = regk_ata_inactive;
REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
ctrl0.en = regk_ata_yes;
ctrl0.dma_strb = ATA_DMA2_STROBE;
ctrl0.dma_hold = ATA_DMA2_HOLD;
ctrl0.pio_setup = ATA_PIO4_SETUP;
ctrl0.pio_strb = ATA_PIO4_STROBE;
ctrl0.pio_hold = ATA_PIO4_HOLD;
REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
ctrl1.udma_tcyc = ATA_UDMA6_CYC;
ctrl1.udma_tdvs = ATA_UDMA6_DVS;
REG_WR(ata, regi_ata, rw_ctrl1, ctrl1);
intr_mask.bus0 = regk_ata_yes;
intr_mask.bus1 = regk_ata_yes;
intr_mask.bus2 = regk_ata_yes;
intr_mask.bus3 = regk_ata_yes;
REG_WR(ata, regi_ata, rw_intr_mask, intr_mask);
crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
crisv32_pinmux_alloc_fixed(pinmux_ata);
crisv32_pinmux_alloc_fixed(pinmux_ata0);
crisv32_pinmux_alloc_fixed(pinmux_ata1);
crisv32_pinmux_alloc_fixed(pinmux_ata2);
crisv32_pinmux_alloc_fixed(pinmux_ata3);
DMA_RESET(regi_dma2);
DMA_ENABLE(regi_dma2);
DMA_RESET(regi_dma3);
DMA_ENABLE(regi_dma3);
DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2);
DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2);
}
static int crisv32_dma_off (ide_drive_t *drive)
{
return 0;
}
static int crisv32_dma_on (ide_drive_t *drive)
{
return 0;
}
static dma_descr_context mycontext __attribute__ ((__aligned__(32)));
static dma_descr_data mydescr __attribute__ ((__aligned__(16)));
/*
* The following routines are mainly used by the ATAPI drivers.
*
* These routines will round up any request for an odd number of bytes,
* so if an odd bytecount is specified, be sure that there's at least one
* extra byte allocated for the buffer.
*/
static void
crisv32_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
{
reg_ata_rw_trf_cnt trf_cnt = {0};
reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
reg_dma_rw_stat status;
unsigned char* d;
D(printk("atapi_input_bytes, buffer 0x%x, count %d\n",
buffer, bytecount));
if(bytecount & 1) {
printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
bytecount++; /* to round off */
}
/* setup DMA descriptor */
mydescr.eol = 1;
mydescr.buf = (char*)virt_to_phys(buffer);
mydescr.after = mydescr.buf + bytecount;
mycontext.saved_data = (dma_descr_data*)virt_to_phys(&mydescr);
mycontext.saved_data_buf = mydescr.buf;
/* start the dma channel */
DMA_START_CONTEXT(regi_dma3, virt_to_phys(&mycontext));
/* initiate a multi word dma read using PIO handshaking */
trf_cnt.cnt = bytecount >> 1;
REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt);
d = buffer;
ctrl2.rw = regk_ata_rd;
ctrl2.trf_mode = regk_ata_dma;
ctrl2.hsh = regk_ata_pio;
ctrl2.multi = regk_ata_yes;
ctrl2.dma_size = regk_ata_word;
REG_WR(ata, regi_ata, rw_ctrl2, ctrl2);
/* wait for completion */
LED_DISK_READ(1);
do
{
status = REG_RD(dma, regi_dma3, rw_stat);
} while(status.list_state != regk_dma_data_at_eol);
LED_DISK_READ(0);
}
static void
crisv32_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
{
reg_ata_rw_trf_cnt trf_cnt = {0};
reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
reg_dma_rw_stat status;
D(printk("atapi_output_bytes, dreg 0x%x, buffer 0x%x, count %d\n",
0, buffer, bytecount));
if(bytecount & 1) {
printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
bytecount++;
}
/* setup DMA descriptor */
mydescr.eol = 1;
mydescr.buf = (char*)virt_to_phys(buffer);
mydescr.after = mydescr.buf + bytecount;
mycontext.saved_data = (dma_descr_data*)virt_to_phys(&mydescr);
mycontext.saved_data_buf = mydescr.buf;
/* start the dma channel */
DMA_START_CONTEXT(regi_dma2, virt_to_phys(&mycontext));
/* initiate a multi word dma write using PIO handshaking */
trf_cnt.cnt = bytecount >> 1;
REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt);
ctrl2.rw = regk_ata_wr;
ctrl2.trf_mode = regk_ata_dma;
ctrl2.hsh = regk_ata_pio;
ctrl2.multi = regk_ata_yes;
ctrl2.dma_size = regk_ata_word;
REG_WR(ata, regi_ata, rw_ctrl2, ctrl2);
/* wait for completion */
LED_DISK_WRITE(1);
LED_DISK_READ(1);
do
{
status = REG_RD(dma, regi_dma2, rw_stat);
} while(status.list_state != regk_dma_data_at_eol);
LED_DISK_WRITE(0);
}
/*
* This is used for most PIO data transfers *from* the IDE interface
*/
static void
crisv32_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
{
crisv32_atapi_input_bytes(drive, buffer, wcount << 2);
}
/*
* This is used for most PIO data transfers *to* the IDE interface
*/
static void
crisv32_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
{
crisv32_atapi_output_bytes(drive, buffer, wcount << 2);
}
/* we only have one DMA channel on the chip for ATA, so we can keep these statically */
static dma_descr_data ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16)));
static unsigned int ata_tot_size;
/*
* crisv32_ide_build_dmatable() prepares a dma request.
* Returns 0 if all went okay, returns 1 otherwise.
*/
static int crisv32_ide_build_dmatable (ide_drive_t *drive)
{
ide_hwif_t *hwif = HWIF(drive);
struct scatterlist* sg;
struct request *rq = HWGROUP(drive)->rq;
unsigned long size, addr;
unsigned int count = 0;
int i = 0;
sg = hwif->sg_table;
ata_tot_size = 0;
if (HWGROUP(drive)->rq->flags & REQ_DRIVE_TASKFILE) {
u8 *virt_addr = rq->buffer;
int sector_count = rq->nr_sectors;
memset(&sg[0], 0, sizeof(*sg));
sg[0].page = virt_to_page(virt_addr);
sg[0].offset = offset_in_page(virt_addr);
sg[0].length = sector_count * SECTOR_SIZE;
hwif->sg_nents = i = 1;
}
else
{
hwif->sg_nents = i = blk_rq_map_sg(drive->queue, rq, hwif->sg_table);
}
while(i) {
/*
* Determine addr and size of next buffer area. We assume that
* individual virtual buffers are always composed linearly in
* physical memory. For example, we assume that any 8kB buffer
* is always composed of two adjacent physical 4kB pages rather
* than two possibly non-adjacent physical 4kB pages.
*/
/* group sequential buffers into one large buffer */
addr = page_to_phys(sg->page) + sg->offset;
size = sg_dma_len(sg);
while (sg++, --i) {
if ((addr + size) != page_to_phys(sg->page) + sg->offset)
break;
size += sg_dma_len(sg);
}
/* did we run out of descriptors? */
if(count >= MAX_DMA_DESCRS) {
printk("%s: too few DMA descriptors\n", drive->name);
return 1;
}
/* however, this case is more difficult - rw_trf_cnt cannot be more
than 65536 words per transfer, so in that case we need to either
1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with
the descriptors, or
2) simply do the request here, and get dma_intr to only ide_end_request on
those blocks that were actually set-up for transfer.
*/
if(ata_tot_size + size > 131072) {
printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
return 1;
}
ata_descrs[count].eol = 0;
ata_descrs[count].buf = (char*)addr;
ata_descrs[count].after = ata_descrs[count].buf + size;
ata_descrs[count].next = (dma_descr_data*)virt_to_phys(&ata_descrs[count + 1]);
count++;
ata_tot_size += size;
}
if (count) {
/* set the end-of-list flag on the last descriptor */
ata_descrs[count - 1].eol = 1;
/* return and say all is ok */
return 0;
}
printk("%s: empty DMA table?\n", drive->name);
return 1; /* let the PIO routines handle this weirdness */
}
static int config_drive_for_dma (ide_drive_t *drive)
{
struct hd_driveid *id = drive->id;
if (id && (id->capability & 1)) {
/* Enable DMA on any drive that supports mword2 DMA */
if ((id->field_valid & 2) &&
((id->dma_mword & 0xff00) || (id->dma_ultra & 0xff00))) {
drive->using_dma = 1;
return 0; /* DMA enabled */
}
}
drive->using_dma = 0;
return 0; /* DMA not enabled */
}
/*
* crisv32_dma_intr() is the handler for disk read/write DMA interrupts
*/
static ide_startstop_t crisv32_dma_intr (ide_drive_t *drive)
{
int i, dma_stat;
byte stat;
LED_DISK_READ(0);
LED_DISK_WRITE(0);
dma_stat = HWIF(drive)->ide_dma_end(drive);
stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */
if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
if (!dma_stat) {
struct request *rq;
rq = HWGROUP(drive)->rq;
for (i = rq->nr_sectors; i > 0;) {
i -= rq->current_nr_sectors;
DRIVER(drive)->end_request(drive, 1, rq->nr_sectors);
}
return ide_stopped;
}
printk("%s: bad DMA status\n", drive->name);
}
return ide_error(drive, "dma_intr", stat);
}
/*
* Functions below initiates/aborts DMA read/write operations on a drive.
*
* The caller is assumed to have selected the drive and programmed the drive's
* sector address using CHS or LBA. All that remains is to prepare for DMA
* and then issue the actual read/write DMA/PIO command to the drive.
*
* For ATAPI devices, we just prepare for DMA and return. The caller should
* then issue the packet command to the drive and call us again with
* ide_dma_begin afterwards.
*
* Returns 0 if all went well.
* Returns 1 if DMA read/write could not be started, in which case
* the caller should revert to PIO for the current request.
*/
static int crisv32_dma_check(ide_drive_t *drive)
{
int speed = ide_dma_speed(drive, 0); /* No UDMA for now */
speed_crisv32_ide(drive, speed);
ide_config_drive_speed(drive, speed);
return config_drive_for_dma (drive);
}
static int crisv32_dma_end(ide_drive_t *drive)
{
drive->waiting_for_dma = 0;
return 0;
}
static int crisv32_prepare_dma(ide_drive_t *drive, int atapi, int reading)
{
struct request *rq = drive->hwif->hwgroup->rq;
if (crisv32_ide_build_dmatable (drive)) {
ide_map_sg(drive, rq);
return 1;
}
return 0;
}
static int crisv32_dma_setup(ide_drive_t *drive)
{
struct request *rq = HWGROUP(drive)->rq;
int ret;
if (rq_data_dir(rq))
ret = crisv32_prepare_dma(drive, 0, 0);
else
ret = crisv32_prepare_dma(drive, 0, 1);
if (ret)
return ret;
drive->waiting_for_dma = 1;
return 0;
}
static void crisv32_dma_exec_cmd(ide_drive_t *drive, u8 command)
{
/* set the irq handler which will finish the request when DMA is done */
ide_set_handler(drive, &crisv32_dma_intr, WAIT_CMD, NULL);
/* issue cmd to drive */
crisv32_ide_outb(command, IDE_COMMAND_REG);
}
static int crisv32_dma_test_irq(ide_drive_t *drive)
{
int intr = REG_RD_INT(ata, regi_ata, r_intr);
reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
return intr & (1 << ctrl2.sel) ? 1 : 0;
}
static void crisv32_dma_start(ide_drive_t *drive)
{
struct request *rq = HWGROUP(drive)->rq;
reg_ata_rw_trf_cnt trf_cnt = {0};
int writing = rq_data_dir(rq);
reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
/* initiate a multi word dma read using DMA handshaking */
mycontext.saved_data = (dma_descr_data*)virt_to_phys(&ata_descrs[0]);
mycontext.saved_data_buf = ata_descrs[0].buf;
if (writing)
DMA_START_CONTEXT(regi_dma2, virt_to_phys(&mycontext));
else
DMA_START_CONTEXT(regi_dma3, virt_to_phys(&mycontext));
trf_cnt.cnt = ata_tot_size >> 1;
ctrl2.rw = writing ? regk_ata_wr : regk_ata_rd;
ctrl2.trf_mode = regk_ata_dma;
if (drive->current_speed >= XFER_UDMA_0) {
/* Due to a "feature" the transfer count has to be one extra word for UDMA. */
trf_cnt.cnt++;
ctrl2.hsh = regk_ata_udma;
}
else
ctrl2.hsh = regk_ata_dma;
ctrl2.multi = regk_ata_yes;
ctrl2.dma_size = regk_ata_word;
REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt);
REG_WR(ata, regi_ata, rw_ctrl2, ctrl2);
if (writing) {
LED_DISK_WRITE(1);
} else {
LED_DISK_READ(1);
}
}
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: New IDE driver for review 2005-06-09 7:18 Mikael Starvik @ 2005-06-09 10:14 ` Bartlomiej Zolnierkiewicz 0 siblings, 0 replies; 9+ messages in thread From: Bartlomiej Zolnierkiewicz @ 2005-06-09 10:14 UTC (permalink / raw) To: Mikael Starvik; +Cc: linux-ide Hi, On 6/9/05, Mikael Starvik <mikael.starvik@axis.com> wrote: > I am about to release a new subarchitecture to the cris architcecture. > A part of this release is a new IDE driver. Basically just a port of > the IDE driver for the old architecture with the addition of UDMA 0-2. > > The driver is attached if anyone wants to review it before submission. > I understand if no one is interrested in taking a look at it (CRIS > is really a minor arch). it depends on the IDE subsystem so... > If no one objects I'll send this to Andrew after the 2.6.12 release. >From the quick review: following files are needed to really understand what the driver is doing... > #include <asm/arch/hwregs/ata_defs.h> > #include <asm/arch/hwregs/dma_defs.h> > #include <asm/arch/hwregs/dma.h> ... > static void tune_crisv32_ide(ide_drive_t *drive, byte pio) > { please use 'u8' instead of 'byte' (everywhere) > reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); > reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1); ctrl1 variable is not modified anywhere in tune_crisv32_ide(), if hardware doesn't require related registers (can't tell more - you haven't attached include files) to be refreshed it can be removed > if (pio <= 4) > pio = ide_get_best_pio_mode(drive, pio, 4, NULL); ide_get_best_pio_mode() call with such parameters returns 'pio', you can remove these two lines > switch(pio) > { > case 0: > ctrl0.pio_setup = ATA_PIO0_SETUP; > ctrl0.pio_strb = ATA_PIO0_STROBE; > ctrl0.pio_hold = ATA_PIO0_HOLD; > break; > case 1: > ctrl0.pio_setup = ATA_PIO1_SETUP; > ctrl0.pio_strb = ATA_PIO1_STROBE; > ctrl0.pio_hold = ATA_PIO1_HOLD; > break; > case 2: > ctrl0.pio_setup = ATA_PIO2_SETUP; > ctrl0.pio_strb = ATA_PIO2_STROBE; > ctrl0.pio_hold = ATA_PIO2_HOLD; > break; > case 3: > ctrl0.pio_setup = ATA_PIO3_SETUP; > ctrl0.pio_strb = ATA_PIO3_STROBE; > ctrl0.pio_hold = ATA_PIO3_HOLD; > break; > case 4: > ctrl0.pio_setup = ATA_PIO4_SETUP; > ctrl0.pio_strb = ATA_PIO4_STROBE; > ctrl0.pio_hold = ATA_PIO4_HOLD; > break; > } > > REG_WR(ata, regi_ata, rw_ctrl1, ctrl1); > REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); > } > > static int speed_crisv32_ide(ide_drive_t *drive, byte speed) > { > reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); > reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1); > > switch(speed) > { > case XFER_UDMA_0: > ctrl1.udma_tcyc = ATA_UDMA0_CYC; > ctrl1.udma_tdvs = ATA_UDMA0_DVS; > break; > case XFER_UDMA_1: > ctrl1.udma_tcyc = ATA_UDMA1_CYC; > ctrl1.udma_tdvs = ATA_UDMA1_DVS; > break; > case XFER_UDMA_2: > ctrl1.udma_tcyc = ATA_UDMA2_CYC; > ctrl1.udma_tdvs = ATA_UDMA2_DVS; > break; > case XFER_MW_DMA_2: > ctrl0.dma_strb = ATA_DMA0_STROBE; > ctrl0.dma_hold = ATA_DMA0_HOLD; > break; is this correct: XFER_MW_DMA_2 -> ATA_DMA0_* ? > case XFER_MW_DMA_0: > ctrl0.dma_strb = ATA_DMA2_STROBE; > ctrl0.dma_hold = ATA_DMA2_HOLD; > break; ditto > case XFER_PIO_0: > ctrl0.pio_setup = ATA_PIO0_SETUP; > ctrl0.pio_strb = ATA_PIO0_STROBE; > ctrl0.pio_hold = ATA_PIO0_HOLD; > break; > case XFER_PIO_1: > ctrl0.pio_setup = ATA_PIO1_SETUP; > ctrl0.pio_strb = ATA_PIO1_STROBE; > ctrl0.pio_hold = ATA_PIO1_HOLD; > break; > case XFER_PIO_2: > ctrl0.pio_setup = ATA_PIO2_SETUP; > ctrl0.pio_strb = ATA_PIO2_STROBE; > ctrl0.pio_hold = ATA_PIO2_HOLD; > break; > case XFER_PIO_3: > ctrl0.pio_setup = ATA_PIO3_SETUP; > ctrl0.pio_strb = ATA_PIO3_STROBE; > ctrl0.pio_hold = ATA_PIO3_HOLD; > break; > case XFER_PIO_4: > ctrl0.pio_setup = ATA_PIO4_SETUP; > ctrl0.pio_strb = ATA_PIO4_STROBE; > ctrl0.pio_hold = ATA_PIO4_HOLD; > break; > } PIO setup code is _identical_ to that in tune_crisv32_ide(), speed_crisv32_ide() can be rewritten to use tune_crisv32_ide(): static int speed_crisv32_ide(ide_drive_t *drive, u8 speed) { reg_ata_rw_ctrl0 ctrl0; reg_ata_rw_ctrl1 ctrl1; if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) return tune_crisv32_ide(drive, speed); ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0); ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1); ... } > REG_WR(ata, regi_ata, rw_ctrl1, ctrl1); > REG_WR(ata, regi_ata, rw_ctrl0, ctrl0); > > return 0; > } > void __init > init_e100_ide (void) > { > hwif->udma_four = 1; why is host side 80-wires cable flag always set? this controller doesn't even support UDMA > 2 > hwif->sg_table = > kmalloc(sizeof(struct scatterlist) * PRD_ENTRIES, GFP_KERNEL); this will memleak memory as hwif->sg_table is allocated during probe > static int crisv32_ide_build_dmatable (ide_drive_t *drive) > { > ide_hwif_t *hwif = HWIF(drive); please use 'drive->hwif' instead of HWIF() (everywhere) > struct scatterlist* sg; > struct request *rq = HWGROUP(drive)->rq; please use 'drive->hwif->hwgroup' instead of HWGROUP() (everywhere) > if (HWGROUP(drive)->rq->flags & REQ_DRIVE_TASKFILE) { > u8 *virt_addr = rq->buffer; > int sector_count = rq->nr_sectors; > memset(&sg[0], 0, sizeof(*sg)); > sg[0].page = virt_to_page(virt_addr); > sg[0].offset = offset_in_page(virt_addr); > sg[0].length = sector_count * SECTOR_SIZE; > hwif->sg_nents = i = 1; > } > else > { > hwif->sg_nents = i = blk_rq_map_sg(drive->queue, rq, hwif->sg_table); > } above code should be replaced by: ide_map_sg(drive, rq); i = hwif->sg_nents; > static ide_startstop_t crisv32_dma_intr (ide_drive_t *drive) > { > int i, dma_stat; > byte stat; > > LED_DISK_READ(0); > LED_DISK_WRITE(0); > > dma_stat = HWIF(drive)->ide_dma_end(drive); > stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */ > if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) { > if (!dma_stat) { > struct request *rq; > rq = HWGROUP(drive)->rq; > for (i = rq->nr_sectors; i > 0;) { > i -= rq->current_nr_sectors; > DRIVER(drive)->end_request(drive, 1, rq->nr_sectors); > } > return ide_stopped; > } > printk("%s: bad DMA status\n", drive->name); > } > return ide_error(drive, "dma_intr", stat); > } this won't even compile with 2.6.12-rc6 (DRIVER() was removed), besides crisv32_dma_intr() can be much simpler: static ide_startstop_t crisv32_dma_intr(ide_drive_t *drive) { LED_DISK_READ(0); LED_DISK_WRITE(0); return ide_dma_intr(drive); } It may be reasonable to merge ide-v10.c and ide-v32.c drivers (using macros to abstract differences etc.) but without seeing register layout for v32 I can't tell for sure (hint: missing include files). Thanks, Bartlomiej ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2005-06-27 15:36 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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[not found] <BFECAF9E178F144FAEF2BF4CE739C668030C7157@exmail1.se.axis.com>
2005-06-27 15:17 ` New IDE driver for review Mikael Starvik
2005-06-27 15:36 ` Bartlomiej Zolnierkiewicz
[not found] <BFECAF9E178F144FAEF2BF4CE739C668030176E7@exmail1.se.axis.com>
2005-06-17 14:16 ` Mikael Starvik
2005-06-20 19:15 ` Bartlomiej Zolnierkiewicz
[not found] <BFECAF9E178F144FAEF2BF4CE739C668030174FD@exmail1.se.axis.com>
2005-06-09 10:29 ` Mikael Starvik
2005-06-09 12:54 ` Mikael Starvik
2005-06-09 15:10 ` Bartlomiej Zolnierkiewicz
2005-06-09 7:18 Mikael Starvik
2005-06-09 10:14 ` Bartlomiej Zolnierkiewicz
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