Re: [PATCH 09/09] sata_mv cache main_irq_mask register in hpriv

["Grant Grundler" <grundler@google.com>]

On Sat, May 17, 2008 at 10:38 AM, Mark Lord <liml@rtr.ca> wrote:
> Part five of simplifying/fixing handling of the main_irq_mask register
> to resolve unexpected interrupt issues observed in 2.6.26-rc*.
>
> Keep a cached copy of the main_irq_mask so that we don't have
> to stall the CPU to read it on every pass through mv_interrupt.
>
> This significantly speeds up interrupt handling, both for sata_mv,
> and for any other driver/device sharing the same PCI IRQ line.

To be precise, it saves about ~1% of cpu cycles of ~2Ghz CPU
as measured by oprofile. "fio" provided the workload by sequentially
reading 4K blocks from 4 normal SATA II disks (about 8K IO/s per disk).
This is expected to be similar to using SSDs.
So not a huge win; just an easy one.

Here is the cost of one MMIO read on a not-to-old intel PCI-e chipset:
0a:00.0 (11ab:7042): sata_mv from CPU0                   SATAHC0Cause
(20014):  1345 cycles   576 ns
0a:00.0 (11ab:7042): sata_mv from CPU0                      main_mask
(1d64):  1302 cycles   558 ns
0a:00.0 (11ab:7042): sata_mv from CPU0                     main_cause
(1d60):  1302 cycles   558 ns

I'll note this is extremely fast since there are no PCI-PCI bridges
and the 7042 controller seems to respond very quickly.
More typical is 1000ns or so.

thanks,
grant

(1) svn co http://svn.gnumonks.org/trunk/mmio_test/

Plus this patch:
    http://iou.parisc-linux.org/~grundler/diff/diff-mmio_test-02