* Re: [RFT] powerpc: convert ppc64e_defconfig to use libata PATA drivers
From: Michael Ellerman @ 2016-11-17 12:04 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras
Cc: linux-ide, linux-kernel, b.zolnierkie
In-Reply-To: <1454514630-29269-20-git-send-email-b.zolnierkie@samsung.com>
On Wed, 2016-03-02 at 15:50:26 UTC, Bartlomiej Zolnierkiewicz wrote:
> IDE subsystem has been deprecated since 2009 and the majority
> (if not all) of Linux distributions have switched to use
> libata for ATA support exclusively. However there are still
> some users (mostly old or/and embedded non-x86 systems) that
> have not converted from using IDE subsystem to libata PATA
> drivers. This doesn't seem to be good thing in the long-term
> for Linux as while there is less and less PATA systems left
> in use:
>
> * testing efforts are divided between two subsystems
>
> * having duplicate drivers for same hardware confuses users
>
> This patch converts ppc64e_defconfig to use libata PATA
> drivers.
>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/4a0b4bfe0101901126dc4dba0ba904
cheers
^ permalink raw reply
* Re: [RFT] powerpc: convert ppc6xx_defconfig to use libata PATA drivers
From: Michael Ellerman @ 2016-11-17 12:04 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras
Cc: linux-ide, linux-kernel, b.zolnierkie
In-Reply-To: <1454514630-29269-21-git-send-email-b.zolnierkie@samsung.com>
On Wed, 2016-03-02 at 15:50:27 UTC, Bartlomiej Zolnierkiewicz wrote:
> IDE subsystem has been deprecated since 2009 and the majority
> (if not all) of Linux distributions have switched to use
> libata for ATA support exclusively. However there are still
> some users (mostly old or/and embedded non-x86 systems) that
> have not converted from using IDE subsystem to libata PATA
> drivers. This doesn't seem to be good thing in the long-term
> for Linux as while there is less and less PATA systems left
> in use:
>
> * testing efforts are divided between two subsystems
>
> * having duplicate drivers for same hardware confuses users
>
> This patch converts ppc6xx_defconfig to use libata PATA
> drivers.
>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/7f10fe36369068341aff05c067a786
cheers
^ permalink raw reply
* Re: [RFT] powerpc: convert amigaone_defconfig to use libata PATA drivers
From: Michael Ellerman @ 2016-11-17 12:04 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras
Cc: linux-ide, linux-kernel, b.zolnierkie
In-Reply-To: <1454514630-29269-12-git-send-email-b.zolnierkie@samsung.com>
On Wed, 2016-03-02 at 15:50:18 UTC, Bartlomiej Zolnierkiewicz wrote:
> IDE subsystem has been deprecated since 2009 and the majority
> (if not all) of Linux distributions have switched to use
> libata for ATA support exclusively. However there are still
> some users (mostly old or/and embedded non-x86 systems) that
> have not converted from using IDE subsystem to libata PATA
> drivers. This doesn't seem to be good thing in the long-term
> for Linux as while there is less and less PATA systems left
> in use:
>
> * testing efforts are divided between two subsystems
>
> * having duplicate drivers for same hardware confuses users
>
> This patch converts amigaone_defconfig to use libata PATA
> drivers.
>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/67f6d66559930eddea06c6bfdaf0e5
cheers
^ permalink raw reply
* Re: [RFT] powerpc: convert ppc64_defconfig to use libata PATA drivers
From: Michael Ellerman @ 2016-11-17 12:04 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras
Cc: linux-ide, linux-kernel, b.zolnierkie
In-Reply-To: <1454514630-29269-19-git-send-email-b.zolnierkie@samsung.com>
On Wed, 2016-03-02 at 15:50:25 UTC, Bartlomiej Zolnierkiewicz wrote:
> IDE subsystem has been deprecated since 2009 and the majority
> (if not all) of Linux distributions have switched to use
> libata for ATA support exclusively. However there are still
> some users (mostly old or/and embedded non-x86 systems) that
> have not converted from using IDE subsystem to libata PATA
> drivers. This doesn't seem to be good thing in the long-term
> for Linux as while there is less and less PATA systems left
> in use:
>
> * testing efforts are divided between two subsystems
>
> * having duplicate drivers for same hardware confuses users
>
> This patch converts ppc64_defconfig to use libata PATA
> drivers.
>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/7ddf3db3d775d09da87f38ab39f261
cheers
^ permalink raw reply
* Re: [RFT] powerpc: convert pmac32_defconfig to use libata PATA drivers
From: Michael Ellerman @ 2016-11-17 12:04 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras
Cc: linux-ide, linux-kernel, b.zolnierkie
In-Reply-To: <1454514630-29269-18-git-send-email-b.zolnierkie@samsung.com>
On Wed, 2016-03-02 at 15:50:24 UTC, Bartlomiej Zolnierkiewicz wrote:
> IDE subsystem has been deprecated since 2009 and the majority
> (if not all) of Linux distributions have switched to use
> libata for ATA support exclusively. However there are still
> some users (mostly old or/and embedded non-x86 systems) that
> have not converted from using IDE subsystem to libata PATA
> drivers. This doesn't seem to be good thing in the long-term
> for Linux as while there is less and less PATA systems left
> in use:
>
> * testing efforts are divided between two subsystems
>
> * having duplicate drivers for same hardware confuses users
>
> This patch converts pmac32_defconfig to use libata PATA
> drivers.
>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/b0d3a074174138b7714533968be723
cheers
^ permalink raw reply
* Re: [RFT] powerpc: convert maple_defconfig to use libata PATA drivers
From: Michael Ellerman @ 2016-11-17 12:04 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras
Cc: linux-ide, linux-kernel, b.zolnierkie
In-Reply-To: <1454514630-29269-16-git-send-email-b.zolnierkie@samsung.com>
On Wed, 2016-03-02 at 15:50:22 UTC, Bartlomiej Zolnierkiewicz wrote:
> IDE subsystem has been deprecated since 2009 and the majority
> (if not all) of Linux distributions have switched to use
> libata for ATA support exclusively. However there are still
> some users (mostly old or/and embedded non-x86 systems) that
> have not converted from using IDE subsystem to libata PATA
> drivers. This doesn't seem to be good thing in the long-term
> for Linux as while there is less and less PATA systems left
> in use:
>
> * testing efforts are divided between two subsystems
>
> * having duplicate drivers for same hardware confuses users
>
> This patch converts maple_defconfig to use libata PATA
> drivers.
>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/c1f9d2938bd75c0245f640ad30d81e
cheers
^ permalink raw reply
* Re: [RFT] powerpc: convert g5_defconfig to use libata PATA drivers
From: Michael Ellerman @ 2016-11-17 12:04 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras
Cc: linux-ide, linux-kernel, b.zolnierkie
In-Reply-To: <1454514630-29269-15-git-send-email-b.zolnierkie@samsung.com>
On Wed, 2016-03-02 at 15:50:21 UTC, Bartlomiej Zolnierkiewicz wrote:
> IDE subsystem has been deprecated since 2009 and the majority
> (if not all) of Linux distributions have switched to use
> libata for ATA support exclusively. However there are still
> some users (mostly old or/and embedded non-x86 systems) that
> have not converted from using IDE subsystem to libata PATA
> drivers. This doesn't seem to be good thing in the long-term
> for Linux as while there is less and less PATA systems left
> in use:
>
> * testing efforts are divided between two subsystems
>
> * having duplicate drivers for same hardware confuses users
>
> This patch converts g5_defconfig to use libata PATA drivers.
>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/b10fd396376c9b1b1f5b0a3980b487
cheers
^ permalink raw reply
* Re: [RFT] powerpc: convert chrp32_defconfig to use libata PATA drivers
From: Michael Ellerman @ 2016-11-17 12:04 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras
Cc: linux-ide, linux-kernel, b.zolnierkie
In-Reply-To: <1454514630-29269-14-git-send-email-b.zolnierkie@samsung.com>
On Wed, 2016-03-02 at 15:50:20 UTC, Bartlomiej Zolnierkiewicz wrote:
> IDE subsystem has been deprecated since 2009 and the majority
> (if not all) of Linux distributions have switched to use
> libata for ATA support exclusively. However there are still
> some users (mostly old or/and embedded non-x86 systems) that
> have not converted from using IDE subsystem to libata PATA
> drivers. This doesn't seem to be good thing in the long-term
> for Linux as while there is less and less PATA systems left
> in use:
>
> * testing efforts are divided between two subsystems
>
> * having duplicate drivers for same hardware confuses users
>
> This patch converts chrp32_defconfig to use libata PATA
> drivers.
>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/f22cc4d7bb268ffc585a5f8593138b
cheers
^ permalink raw reply
* Re: [RFT] powerpc: convert cell_defconfig to use libata PATA drivers
From: Michael Ellerman @ 2016-11-17 12:04 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras
Cc: linux-ide, linux-kernel, b.zolnierkie
In-Reply-To: <1454514630-29269-13-git-send-email-b.zolnierkie@samsung.com>
On Wed, 2016-03-02 at 15:50:19 UTC, Bartlomiej Zolnierkiewicz wrote:
> IDE subsystem has been deprecated since 2009 and the majority
> (if not all) of Linux distributions have switched to use
> libata for ATA support exclusively. However there are still
> some users (mostly old or/and embedded non-x86 systems) that
> have not converted from using IDE subsystem to libata PATA
> drivers. This doesn't seem to be good thing in the long-term
> for Linux as while there is less and less PATA systems left
> in use:
>
> * testing efforts are divided between two subsystems
>
> * having duplicate drivers for same hardware confuses users
>
> This patch converts cell_defconfig to use libata PATA drivers.
>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/8020c1220dd4ff324698668f067746
cheers
^ permalink raw reply
* Re: powerpc: disable IDE subsystem in pasemi_defconfig
From: Michael Ellerman @ 2016-11-17 12:04 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras
Cc: Olof Johansson, linux-ide, linux-kernel, b.zolnierkie
In-Reply-To: <1454514630-29269-17-git-send-email-b.zolnierkie@samsung.com>
On Wed, 2016-03-02 at 15:50:23 UTC, Bartlomiej Zolnierkiewicz wrote:
> This patch disables deprecated IDE subsystem in pasemi_defconfig
> (no IDE host drivers are selected in this config so there is no valid
> reason to enable IDE subsystem itself).
>
> Cc: Olof Johansson <olof@lixom.net>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/23bf36cd120f97e85ce089c841197f
cheers
^ permalink raw reply
* [PATCH 2/2] arm64: dts: updated sata node on ls1046a dts
From: yuantian.tang @ 2016-11-17 7:59 UTC (permalink / raw)
To: tj
Cc: robh+dt, mark.rutland, catalin.marinas, will.deacon, shawnguo,
linux-ide, devicetree, linux-kernel, linux-arm-kernel,
Tang Yuantian, Tang Yuantian
In-Reply-To: <1479369560-9188-1-git-send-email-yuantian.tang@nxp.com>
From: Tang Yuantian <Yuantian.Tang@nxp.com>
On ls1046a soc, sata ecc should be disabled. So added sata ecc
register address so that driver can get this information.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..88aaaf1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -507,7 +507,9 @@
sata: sata@3200000 {
compatible = "fsl,ls1046a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>;
+ reg = <0x0 0x3200000 0x0 0x10000>,
+ <0x0 0x20140520 0x0 0x4>;
+ reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
};
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: ahci-fsl-qoriq: added explanation for reg-names
From: yuantian.tang @ 2016-11-17 7:59 UTC (permalink / raw)
To: tj
Cc: robh+dt, mark.rutland, catalin.marinas, will.deacon, shawnguo,
linux-ide, devicetree, linux-kernel, linux-arm-kernel,
Tang Yuantian, Tang Yuantian
From: Tang Yuantian <Yuantian.Tang@nxp.com>
Added explanation for reg-names to make it more clear.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
---
Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
index fc33ca0..80cf10c 100644
--- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
@@ -10,6 +10,8 @@ Required properties:
Optional properties:
- dma-coherent: Enable AHCI coherent DMA operation.
- reg-names: register area names when there are more than 1 register area.
+ example: 'ahci' is for sata controller register.
+ 'sata-ecc' is for sata ecc register.
Examples:
sata@3200000 {
--
2.1.0.27.g96db324
^ permalink raw reply related
* 14298 linux-ide
From: mitch_128 @ 2016-11-17 6:54 UTC (permalink / raw)
To: linux-ide
[-- Attachment #1: EMAIL_261637948_linux-ide.zip --]
[-- Type: application/zip, Size: 3313 bytes --]
^ permalink raw reply
* Re: [PATCH 1/2] ahci: qoriq: added a condition to enable dma coherence
From: Robin Murphy @ 2016-11-16 16:02 UTC (permalink / raw)
To: yuantian.tang, tj; +Cc: linux-ide, linux-kernel, linux-arm-kernel
In-Reply-To: <1479265879-48840-1-git-send-email-yuantian.tang@nxp.com>
On 16/11/16 03:11, yuantian.tang@nxp.com wrote:
> From: Tang Yuantian <Yuantian.Tang@nxp.com>
>
> Enable DMA coherence in SATA controller on condition that
> dma-coherent property exists in sata node in DTS.
>
> Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
> ---
> drivers/ata/ahci_qoriq.c | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
> index 9884c8c..45c88de 100644
> --- a/drivers/ata/ahci_qoriq.c
> +++ b/drivers/ata/ahci_qoriq.c
> @@ -59,6 +59,7 @@ struct ahci_qoriq_priv {
> struct ccsr_ahci *reg_base;
> enum ahci_qoriq_type type;
> void __iomem *ecc_addr;
> + bool is_dmacoherent;
> };
>
> static const struct of_device_id ahci_qoriq_of_match[] = {
> @@ -164,26 +165,31 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
> writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> - writel(AHCI_PORT_AXICC_CFG, reg_base + LS1021A_AXICC_ADDR);
> + if (qpriv->is_dmacoherent)
> + writel(AHCI_PORT_AXICC_CFG,
> + reg_base + LS1021A_AXICC_ADDR);
> break;
>
> case AHCI_LS1043A:
> writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> - writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> + if (qpriv->is_dmacoherent)
> + writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> break;
>
> case AHCI_LS2080A:
> writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> - writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> + if (qpriv->is_dmacoherent)
> + writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> break;
>
> case AHCI_LS1046A:
> writel(LS1046A_SATA_ECC_DIS, qpriv->ecc_addr);
> writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> - writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> + if (qpriv->is_dmacoherent)
> + writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> break;
> }
>
> @@ -221,6 +227,7 @@ static int ahci_qoriq_probe(struct platform_device *pdev)
> if (IS_ERR(qoriq_priv->ecc_addr))
> return PTR_ERR(qoriq_priv->ecc_addr);
> }
> + qoriq_priv->is_dmacoherent = of_property_read_bool(np, "dma-coherent");
Better to use of_dma_is_coherent(np) rather than open-coding it.
Robin.
>
> rc = ahci_platform_enable_resources(hpriv);
> if (rc)
>
^ permalink raw reply
* Re: [PATCH 2/2] ahci: qoriq: report warning when ecc register is missing
From: Mathieu Poirier @ 2016-11-16 15:56 UTC (permalink / raw)
To: yuantian.tang; +Cc: tj, linux-ide, linux-kernel, linux-arm-kernel
In-Reply-To: <1479265879-48840-2-git-send-email-yuantian.tang@nxp.com>
On Wed, Nov 16, 2016 at 11:11:19AM +0800, yuantian.tang@nxp.com wrote:
> From: Tang Yuantian <Yuantian.Tang@nxp.com>
>
> For ls1021a and ls1046a socs, sata ecc must be disabled.
> If ecc register is not found in sata node in dts, report
> a warning.
Hi Yuantian,
What happens if sata ecc is _not_ disaled on those socs? Can the driver still
work? If not then it is probably a better idea to return an error code that can
prevent the driver from initialising.
Thanks,
Mathieu
>
> Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
> ---
> drivers/ata/ahci_qoriq.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
> index 45c88de..66eb4b5 100644
> --- a/drivers/ata/ahci_qoriq.c
> +++ b/drivers/ata/ahci_qoriq.c
> @@ -158,6 +158,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
>
> switch (qpriv->type) {
> case AHCI_LS1021A:
> + WARN_ON(!qpriv->ecc_addr);
> writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
> writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
> @@ -185,6 +186,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> break;
>
> case AHCI_LS1046A:
> + WARN_ON(!qpriv->ecc_addr);
> writel(LS1046A_SATA_ECC_DIS, qpriv->ecc_addr);
> writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> --
> 2.1.0.27.g96db324
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 2/2] ahci: qoriq: report warning when ecc register is missing
From: yuantian.tang @ 2016-11-16 3:11 UTC (permalink / raw)
To: tj; +Cc: linux-ide, linux-kernel, linux-arm-kernel, Tang Yuantian
In-Reply-To: <1479265879-48840-1-git-send-email-yuantian.tang@nxp.com>
From: Tang Yuantian <Yuantian.Tang@nxp.com>
For ls1021a and ls1046a socs, sata ecc must be disabled.
If ecc register is not found in sata node in dts, report
a warning.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
---
drivers/ata/ahci_qoriq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 45c88de..66eb4b5 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -158,6 +158,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
switch (qpriv->type) {
case AHCI_LS1021A:
+ WARN_ON(!qpriv->ecc_addr);
writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
@@ -185,6 +186,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
break;
case AHCI_LS1046A:
+ WARN_ON(!qpriv->ecc_addr);
writel(LS1046A_SATA_ECC_DIS, qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 1/2] ahci: qoriq: added a condition to enable dma coherence
From: yuantian.tang @ 2016-11-16 3:11 UTC (permalink / raw)
To: tj; +Cc: linux-ide, linux-kernel, linux-arm-kernel, Tang Yuantian
From: Tang Yuantian <Yuantian.Tang@nxp.com>
Enable DMA coherence in SATA controller on condition that
dma-coherent property exists in sata node in DTS.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
---
drivers/ata/ahci_qoriq.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 9884c8c..45c88de 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -59,6 +59,7 @@ struct ahci_qoriq_priv {
struct ccsr_ahci *reg_base;
enum ahci_qoriq_type type;
void __iomem *ecc_addr;
+ bool is_dmacoherent;
};
static const struct of_device_id ahci_qoriq_of_match[] = {
@@ -164,26 +165,31 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- writel(AHCI_PORT_AXICC_CFG, reg_base + LS1021A_AXICC_ADDR);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG,
+ reg_base + LS1021A_AXICC_ADDR);
break;
case AHCI_LS1043A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
case AHCI_LS2080A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
case AHCI_LS1046A:
writel(LS1046A_SATA_ECC_DIS, qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
}
@@ -221,6 +227,7 @@ static int ahci_qoriq_probe(struct platform_device *pdev)
if (IS_ERR(qoriq_priv->ecc_addr))
return PTR_ERR(qoriq_priv->ecc_addr);
}
+ qoriq_priv->is_dmacoherent = of_property_read_bool(np, "dma-coherent");
rc = ahci_platform_enable_resources(hpriv);
if (rc)
--
2.1.0.27.g96db324
^ permalink raw reply related
* Re: [PATCH 0/5] ahci: nvme remap support
From: Christoph Hellwig @ 2016-11-15 18:52 UTC (permalink / raw)
To: Dan Williams; +Cc: tj, keith.busch, linux-ide, linux-nvme
In-Reply-To: <147709592108.3733.7194541797066785254.stgit@dwillia2-desk3.amr.corp.intel.com>
As it's been a few weeks since this initial posting: What's the
status of either getting the magic chipset handshake mode published
to take the chipset out of this degraded mode, or implementing a bridge
driver like VMD?
It seems devices supporting this "slow down the devices and make life
hell for the OS" mode are getting more common, so we'll have to do
something about it.
^ permalink raw reply
* Re: [PATCH] ata: xgene: Enable NCQ support for APM X-Gene SATA controller hardware v1.1
From: Tejun Heo @ 2016-11-15 16:21 UTC (permalink / raw)
To: Rameshwar Sahu
Cc: Olof Johansson, linux-scsi, linux-ide, Devicetree List, linux-arm,
Don Dutile, Jon Masters, patches
In-Reply-To: <CAFd313ycmpdp7wHCVRJrigJV31hLwBGOo=FNENwgFnNKyVkQBA@mail.gmail.com>
Hello, Rameshwar.
On Fri, Nov 11, 2016 at 01:36:28PM +0530, Rameshwar Sahu wrote:
> Hi Tejun,
>
> On Wed, Nov 9, 2016 at 10:15 PM, Tejun Heo <tj@kernel.org> wrote:
> > Hello,
> >
> > On Wed, Sep 14, 2016 at 04:15:00PM +0530, Rameshwar Sahu wrote:
> >> > @@ -821,8 +823,6 @@ static int xgene_ahci_probe(struct platform_device
> >> > *pdev)
> >> > dev_warn(&pdev->dev, "%s: Error reading
> >> > device info. Assume version1\n",
> >> > __func__);
> >> > version = XGENE_AHCI_V1;
> >> > - } else if (info->valid & ACPI_VALID_CID) {
> >> > - version = XGENE_AHCI_V2;
> >
> > Can you please explain this part a bit? Everything else looks good to
> > me.
>
> Here we should not assume XGENE_AHCI_V2 always in case of having valid
> _CID in ACPI table.
> I need to remove this assumption because V1_1 has also valid _CID for
> backward compatibly with v1.
Can you please repost with the above explanation added to the commit
message?
Thanks!
--
tejun
^ permalink raw reply
* Re: [PATCH 3/4] pata: imx: add support of setting timings for PIO modes
From: Bartlomiej Zolnierkiewicz @ 2016-11-14 14:22 UTC (permalink / raw)
To: Vladimir Zapolskiy; +Cc: Tejun Heo, linux-ide, Sergei Shtylyov
In-Reply-To: <20161109005638.17691-4-vz@mleia.com>
Hi,
On Wednesday, November 09, 2016 02:56:37 AM Vladimir Zapolskiy wrote:
> The controller is capable to operate in up to PIO4 mode, however
> before the change the driver relies on timing settings done by
> a bootloader for PIO0 mode only. The change adds more flexibility
> in PIO mode selection at runtime and makes the driver to work even if
> bootloader does not preset ATA timings.
>
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> ---
> drivers/ata/pata_imx.c | 47 ++++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 46 insertions(+), 1 deletion(-)
[...]
> +static void pata_imx_set_timing(struct ata_device *adev,
> + struct pata_imx_priv *priv)
> +{
> + struct ata_timing timing;
> + unsigned long clkrate;
> + u32 T, mode;
> +
> + clkrate = clk_get_rate(priv->clk);
> +
> + if (adev->pio_mode < XFER_PIO_0 || adev->pio_mode > XFER_PIO_4 ||
> + !clkrate)
No need check for adev->pio_mode < XFER_PIO_0 || adev->pio_mode > XFER_PIO_4
as the libata core code guarantees that these conditions will never happen.
Also you should at least print an error on !clkrate condition. [ IMHO it
is actually better to BUG_ON() on this condition as the further operations
may be risky for the data integrity (wrong PIO timings may be used). ]
> + return;
> +
> + T = 1000000000 / clkrate;
> + ata_timing_compute(adev, adev->pio_mode, &timing, T * 1000, 0);
> +
> + mode = adev->pio_mode - XFER_PIO_0;
> +
> + writeb(3, priv->host_regs + PATA_IMX_ATA_TIME_OFF);
> + writeb(3, priv->host_regs + PATA_IMX_ATA_TIME_ON);
> + writeb(timing.setup, priv->host_regs + PATA_IMX_ATA_TIME_1);
> + writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2W);
> + writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2R);
> + writeb(1, priv->host_regs + PATA_IMX_ATA_TIME_PIO_RDX);
> +
> + writeb(pio_t4[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_4);
> + writeb(pio_t9[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_9);
> + writeb(pio_tA[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_AX);
> +}
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
^ permalink raw reply
* PLEASE VIEW THE ATTACHED FILE AND CONTACT ME.
From: Dr. Felix Collins @ 2016-11-14 7:43 UTC (permalink / raw)
In-Reply-To: <1666584935.3489547.1479109399212.ref@mail.yahoo.com>
[-- Attachment #1: Type: text/plain, Size: 1 bytes --]
[-- Attachment #2: FROM FIRST NATIONAL BANK OF SOUTH AFRICA (F.N.B)..rtf --]
[-- Type: application/msword, Size: 3007 bytes --]
^ permalink raw reply
* 42805 linux-ide
From: lucia.germino @ 2016-11-12 14:28 UTC (permalink / raw)
To: linux-ide
[-- Attachment #1: MESSAGE_47440230_linux-ide.zip --]
[-- Type: application/zip, Size: 3845 bytes --]
^ permalink raw reply
* Re: [PATCH] ata: xgene: Enable NCQ support for APM X-Gene SATA controller hardware v1.1
From: Rameshwar Sahu @ 2016-11-11 8:06 UTC (permalink / raw)
To: Tejun Heo
Cc: Olof Johansson, linux-scsi-u79uwXL29TY76Z2rM5mHXA,
linux-ide-u79uwXL29TY76Z2rM5mHXA, Devicetree List, linux-arm,
Don Dutile, Jon Masters, patches
In-Reply-To: <20161109164531.GA14630-piEFEHQLUPpN0TnZuCh8vA@public.gmane.org>
Hi Tejun,
On Wed, Nov 9, 2016 at 10:15 PM, Tejun Heo <tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> Hello,
>
> On Wed, Sep 14, 2016 at 04:15:00PM +0530, Rameshwar Sahu wrote:
>> > @@ -821,8 +823,6 @@ static int xgene_ahci_probe(struct platform_device
>> > *pdev)
>> > dev_warn(&pdev->dev, "%s: Error reading
>> > device info. Assume version1\n",
>> > __func__);
>> > version = XGENE_AHCI_V1;
>> > - } else if (info->valid & ACPI_VALID_CID) {
>> > - version = XGENE_AHCI_V2;
>
> Can you please explain this part a bit? Everything else looks good to
> me.
Here we should not assume XGENE_AHCI_V2 always in case of having valid
_CID in ACPI table.
I need to remove this assumption because V1_1 has also valid _CID for
backward compatibly with v1.
>
> Thanks.
>
> --
> tejun
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 3/4] pata: imx: add support of setting timings for PIO modes
From: Tejun Heo @ 2016-11-10 16:10 UTC (permalink / raw)
To: Vladimir Zapolskiy; +Cc: Sergei Shtylyov, Bartlomiej Zolnierkiewicz, linux-ide
In-Reply-To: <ed9bacd7-b6f4-811b-c082-ae4235a747c6@mleia.com>
Hello, Vladimir, Sergei.
On Thu, Nov 10, 2016 at 03:33:22AM +0200, Vladimir Zapolskiy wrote:
> thank you for review, I see that Tejun has applied the changes,
> anyway I'll answer your questions.
Oh, please submit incremental patches as necessary.
> > > @@ -31,6 +40,10 @@
> > > #define PATA_IMX_DRIVE_DATA 0xA0
> > > #define PATA_IMX_DRIVE_CONTROL 0xD8
> > >
> > > +static u32 pio_t4[] = { 30, 20, 15, 10, 10 };
> > > +static u32 pio_t9[] = { 20, 15, 10, 10, 10 };
> > > +static u32 pio_tA[] = { 35, 35, 35, 35, 35 };
> >
> > Perhaps it makes sense to extend the 'struct ata_timing'...
> >
> > [...]
>
> As you guess the numbers are taken right from the ATAPI spec,
> however I haven't found the second ATA controller driver sumbitted
> upstream, which reuses these timings, so probably generalization
> is not needed here. Anyway I would prefer if maintainers do it,
> if they think that it makes sense.
Given that its usage isn't likely to be further expanded, I don't
think it matters that much either way, but it does make sense to put
them in ata_timing. I'd be happy to apply such a patch.
> > What do those registers mean?
>
> You may find a better description from i.MX27 or i.MX31 Reference Manual
> than my retelling, the docs are open.
>
> toff/ton timings are used to avoid bus contention when switching
> BUFFER_EN signal and data writing period. AFAIK these timings are
> specific to the controller only.
>
> > > + writeb(timing.setup, priv->host_regs + PATA_IMX_ATA_TIME_1);
> > > + writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2W);
> > > + writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2R);
> > > + writeb(1, priv->host_regs + PATA_IMX_ATA_TIME_PIO_RDX);
> >
> > And this one?
>
> This is trd timing from the ATA/ATAPI spec, "Read Data Valid to IORDY
> active", its minimal value is defined as 0.
Add comments for these explanations maybe?
> > > +
> > > + writeb(pio_t4[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_4);
> > > + writeb(pio_t9[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_9);
> > > + writeb(pio_tA[mode] / T + 1, priv->host_regs +
> > > PATA_IMX_ATA_TIME_AX);
> >
> > DIV_ROUND_UP(x, T)?
>
> Yes, it is reasonable.
And also for this cleanup?
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 3/4] pata: imx: add support of setting timings for PIO modes
From: Vladimir Zapolskiy @ 2016-11-10 1:33 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: Tejun Heo, Bartlomiej Zolnierkiewicz, linux-ide
In-Reply-To: <23fb0678-db2a-a0ff-65a3-3174720b0ee8@cogentembedded.com>
Hi Sergei,
thank you for review, I see that Tejun has applied the changes,
anyway I'll answer your questions.
On 11/09/2016 11:39 AM, Sergei Shtylyov wrote:
> Hello.
>
> On 11/9/2016 3:56 AM, Vladimir Zapolskiy wrote:
>
>> The controller is capable to operate in up to PIO4 mode, however
>> before the change the driver relies on timing settings done by
>> a bootloader for PIO0 mode only. The change adds more flexibility
>> in PIO mode selection at runtime and makes the driver to work even if
> ^^ not needed
>
>> bootloader does not preset ATA timings.
>>
>> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
>> ---
>> drivers/ata/pata_imx.c | 47
>> ++++++++++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 46 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/ata/pata_imx.c b/drivers/ata/pata_imx.c
>> index 00df18b..8f13c9f 100644
>> --- a/drivers/ata/pata_imx.c
>> +++ b/drivers/ata/pata_imx.c
> [...]
>> @@ -31,6 +40,10 @@
>> #define PATA_IMX_DRIVE_DATA 0xA0
>> #define PATA_IMX_DRIVE_CONTROL 0xD8
>>
>> +static u32 pio_t4[] = { 30, 20, 15, 10, 10 };
>> +static u32 pio_t9[] = { 20, 15, 10, 10, 10 };
>> +static u32 pio_tA[] = { 35, 35, 35, 35, 35 };
>
> Perhaps it makes sense to extend the 'struct ata_timing'...
>
> [...]
As you guess the numbers are taken right from the ATAPI spec,
however I haven't found the second ATA controller driver sumbitted
upstream, which reuses these timings, so probably generalization
is not needed here. Anyway I would prefer if maintainers do it,
if they think that it makes sense.
>> @@ -38,11 +51,43 @@ struct pata_imx_priv {
>> u32 ata_ctl;
>> };
>>
>> +static void pata_imx_set_timing(struct ata_device *adev,
>> + struct pata_imx_priv *priv)
>> +{
>> + struct ata_timing timing;
>> + unsigned long clkrate;
>> + u32 T, mode;
>> +
>> + clkrate = clk_get_rate(priv->clk);
>> +
>> + if (adev->pio_mode < XFER_PIO_0 || adev->pio_mode > XFER_PIO_4 ||
>> + !clkrate)
>> + return;
>> +
>> + T = 1000000000 / clkrate;
>> + ata_timing_compute(adev, adev->pio_mode, &timing, T * 1000, 0);
>> +
>> + mode = adev->pio_mode - XFER_PIO_0;
>> +
>> + writeb(3, priv->host_regs + PATA_IMX_ATA_TIME_OFF);
>> + writeb(3, priv->host_regs + PATA_IMX_ATA_TIME_ON);
>
> What do those registers mean?
You may find a better description from i.MX27 or i.MX31 Reference Manual
than my retelling, the docs are open.
toff/ton timings are used to avoid bus contention when switching
BUFFER_EN signal and data writing period. AFAIK these timings are
specific to the controller only.
>> + writeb(timing.setup, priv->host_regs + PATA_IMX_ATA_TIME_1);
>> + writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2W);
>> + writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2R);
>> + writeb(1, priv->host_regs + PATA_IMX_ATA_TIME_PIO_RDX);
>
> And this one?
This is trd timing from the ATA/ATAPI spec, "Read Data Valid to IORDY
active", its minimal value is defined as 0.
>> +
>> + writeb(pio_t4[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_4);
>> + writeb(pio_t9[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_9);
>> + writeb(pio_tA[mode] / T + 1, priv->host_regs +
>> PATA_IMX_ATA_TIME_AX);
>
> DIV_ROUND_UP(x, T)?
Yes, it is reasonable.
--
With best wishes,
Vladimir
^ permalink raw reply
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