* [PATCH] ahci: always fall back to single-MSI mode
From: Christoph Hellwig @ 2016-11-18 13:09 UTC (permalink / raw)
To: tj; +Cc: michael, linux-ide
Don't try to guess what the errors from pci_irq_alloc_vectors mean, as
that's too fragile. Instead always try allocating a single vector
when multi-MSI mode fails. This makes various intel Desktop and
Laptop CPUs use MSI again.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reported-by: Michael Marley <michael@michaelmarley.com>
Tested-by: Michael Marley <michael@michaelmarley.com>
Fixes: 0b9e2988ab22 ("ahci: use pci_alloc_irq_vectors")
---
drivers/ata/ahci.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 9669fc7..74f4c66 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1436,13 +1436,6 @@ static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
"ahci: MRSM is on, fallback to single MSI\n");
pci_free_irq_vectors(pdev);
}
-
- /*
- * -ENOSPC indicated we don't have enough vectors. Don't bother
- * trying a single vectors for any other error:
- */
- if (nvec < 0 && nvec != -ENOSPC)
- return nvec;
}
/*
--
2.1.4
^ permalink raw reply related
* Re: [PATCH 1/2] dt-bindings: ahci-fsl-qoriq: added explanation for reg-names
From: Rob Herring @ 2016-11-18 14:21 UTC (permalink / raw)
To: yuantian.tang
Cc: mark.rutland, devicetree, catalin.marinas, will.deacon,
linux-kernel, linux-ide, tj, shawnguo, linux-arm-kernel
In-Reply-To: <1479369560-9188-1-git-send-email-yuantian.tang@nxp.com>
On Thu, Nov 17, 2016 at 03:59:19PM +0800, yuantian.tang@nxp.com wrote:
> From: Tang Yuantian <Yuantian.Tang@nxp.com>
>
> Added explanation for reg-names to make it more clear.
>
> Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
> ---
> Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
> index fc33ca0..80cf10c 100644
> --- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
> +++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
> @@ -10,6 +10,8 @@ Required properties:
> Optional properties:
> - dma-coherent: Enable AHCI coherent DMA operation.
> - reg-names: register area names when there are more than 1 register area.
> + example: 'ahci' is for sata controller register.
> + 'sata-ecc' is for sata ecc register.
This is not an example, but should be exactly what names are used.
When is there more than one area? That should be defined by the
compatible string and spelled out here.
Rob
^ permalink raw reply
* Re: [PATCH 0/5] ahci: nvme remap support
From: Dan Williams @ 2016-11-19 6:12 UTC (permalink / raw)
To: Christoph Hellwig
Cc: Tejun Heo, Keith Busch, IDE/ATA development list, linux-nvme
In-Reply-To: <20161115185207.GB5854@lst.de>
On Tue, Nov 15, 2016 at 10:52 AM, Christoph Hellwig <hch@lst.de> wrote:
> As it's been a few weeks since this initial posting: What's the
> status of either getting the magic chipset handshake mode published
> to take the chipset out of this degraded mode, or implementing a bridge
> driver like VMD?
The setting is done via write-once registers (once per reset), so
there is no mechanism for an OS to undo it.
> It seems devices supporting this "slow down the devices and make life
> hell for the OS" mode are getting more common, so we'll have to do
> something about it.
To my knowledge all platforms that ship this configuration now already
ship a BIOS, or have an updated BIOS available, that allows the
platform to be placed into AHCI mode.
Setting the controller to AHCI mode is the best option for running
Linux on these systems.
^ permalink raw reply
* [Bug 185531] pata_hpt366 irq xx: nobody cared
From: bugzilla-daemon @ 2016-11-19 7:15 UTC (permalink / raw)
To: linux-ide
In-Reply-To: <bug-185531-11633@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=185531
--- Comment #1 from Ilario Gottardello <ilario.gottardello@gmail.com> ---
Upgraded ubuntu tu 16.10, problem remains:
[ 157.920408] irq 19: nobody cared (try booting with the "irqpoll" option)
[ 157.920412] CPU: 2 PID: 0 Comm: swapper/2 Tainted: P OE
4.8.0-27-generic #29-Ubuntu
[ 157.920413] Hardware name: System manufacturer System Product Name/P8H67-V,
BIOS 3707 07/12/2013
[ 157.920414] 0000000000200086 49f34aec7d2664cd ffff929caf283e78
ffffffffb342f5b2
[ 157.920416] ffff929c9f6bb400 ffff929c9f6bb4b4 ffff929caf283ea8
ffffffffb30e2b65
[ 157.920417] ffff929c9f6bb400 0000000000000000 ffffffffb3f5a100
0000000000000072
[ 157.920419] Call Trace:
[ 157.920419] <IRQ> [<ffffffffb342f5b2>] dump_stack+0x63/0x81
[ 157.920429] [<ffffffffb30e2b65>] __report_bad_irq+0x35/0xc0
[ 157.920430] [<ffffffffb30e2ef3>] note_interrupt+0x243/0x290
[ 157.920431] [<ffffffffb30e0014>] handle_irq_event_percpu+0x54/0x80
[ 157.920433] [<ffffffffb30e007e>] handle_irq_event+0x3e/0x60
[ 157.920433] [<ffffffffb30e35ef>] handle_fasteoi_irq+0x9f/0x150
[ 157.920435] [<ffffffffb303021a>] handle_irq+0x1a/0x30
[ 157.920437] [<ffffffffb38a18db>] do_IRQ+0x4b/0xd0
[ 157.920439] [<ffffffffb389f9c2>] common_interrupt+0x82/0x82
[ 157.920439] <EOI> [<ffffffffb371d29f>] ? cpuidle_enter_state+0x11f/0x2c0
[ 157.920443] [<ffffffffb371d477>] cpuidle_enter+0x17/0x20
[ 157.920445] [<ffffffffb30c791a>] call_cpuidle+0x2a/0x50
[ 157.920445] [<ffffffffb30c7d00>] cpu_startup_entry+0x2a0/0x350
[ 157.920447] [<ffffffffb30518a1>] start_secondary+0x151/0x190
[ 157.920448] handlers:
[ 157.920450] [<ffffffffb3638d90>] ata_bmdma_interrupt
[ 157.920451] [<ffffffffb3638d90>] ata_bmdma_interrupt
[ 157.920452] Disabling IRQ #19
--
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^ permalink raw reply
* [Bug 188141] New: PCI0680 can't work reliably in UDMA mode over 33
From: bugzilla-daemon @ 2016-11-19 7:46 UTC (permalink / raw)
To: linux-ide
https://bugzilla.kernel.org/show_bug.cgi?id=188141
Bug ID: 188141
Summary: PCI0680 can't work reliably in UDMA mode over 33
Product: IO/Storage
Version: 2.5
Kernel Version: 4.8.0-27-generic #29-Ubuntu SMP Thu Oct 20 21:03:13
UTC 2016 x86_64 x86_64 x86_64 GNU/Linux
Hardware: All
OS: Linux
Tree: Mainline
Status: NEW
Severity: high
Priority: P1
Component: IDE
Assignee: io_ide@kernel-bugs.osdl.org
Reporter: ilario.gottardello@gmail.com
Regression: No
Subsituting an HPT366 IDE controller with a Silicon Image, Inc. PCI0680 Ultra
ATA-133 Host Controller (rev 02) (so same pci slot / cables / hard drives), it
immediately fails to read data from the disks, slowing down the link to
UDMA/33.
Here the log on dmesg:
[ 526.912245] ata3.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[ 526.912252] ata3.00: failed command: READ DMA EXT
[ 526.912258] ata3.00: cmd 25/00:00:4f:98:ee/00:04:01:00:00/e0 tag 0 dma
524288 in
res 40/00:00:00:4f:c2/00:00:00:00:00/00 Emask 0x4
(timeout)
[ 526.912261] ata3.00: status: { DRDY }
[ 531.951419] ata3: link is slow to respond, please be patient (ready=0)
[ 536.930691] ata3: device not ready (errno=-16), forcing hardreset
[ 536.930705] ata3: soft resetting link
[ 537.145123] ata3.00: configured for UDMA/133
[ 537.145138] ata3: EH complete
[ 569.918070] ata3.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[ 569.918076] ata3.00: failed command: READ DMA
[ 569.918083] ata3.00: cmd c8/00:50:ef:ba:2f/00:00:00:00:00/e1 tag 0 dma 40960
in
res 40/00:00:00:4f:c2/00:00:00:00:00/00 Emask 0x4
(timeout)
[ 569.918086] ata3.00: status: { DRDY }
[ 574.957860] ata3: link is slow to respond, please be patient (ready=0)
[ 579.945773] ata3: device not ready (errno=-16), forcing hardreset
[ 579.945788] ata3: soft resetting link
[ 580.159919] ata3.00: configured for UDMA/133
[ 580.159933] ata3: EH complete
[ 612.924604] ata3.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[ 612.924610] ata3.00: failed command: READ DMA EXT
[ 612.924616] ata3.00: cmd 25/00:00:4f:10:da/00:04:01:00:00/e0 tag 0 dma
524288 in
res 40/00:00:00:4f:c2/00:00:00:00:00/00 Emask 0x4
(timeout)
[ 612.924619] ata3.00: status: { DRDY }
[ 617.968302] ata3: link is slow to respond, please be patient (ready=0)
[ 622.948039] ata3: device not ready (errno=-16), forcing hardreset
[ 622.948053] ata3: soft resetting link
[ 623.162218] ata3.00: configured for UDMA/133
[ 623.162232] ata3: EH complete
[ 655.930086] ata3.00: limiting speed to UDMA/100:PIO4
[ 655.930089] ata3.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[ 655.930095] ata3.00: failed command: READ DMA EXT
[ 655.930101] ata3.00: cmd 25/00:a8:8f:4e:a8/00:02:01:00:00/e0 tag 0 dma
348160 in
res 40/00:00:00:4f:c2/00:00:00:00:00/00 Emask 0x4
(timeout)
[ 655.930104] ata3.00: status: { DRDY }
[ 660.933621] ata3: link is slow to respond, please be patient (ready=0)
[ 665.985242] ata3: device not ready (errno=-16), forcing hardreset
[ 665.985256] ata3: soft resetting link
[ 666.180539] ata3.00: configured for UDMA/100
[ 666.180553] ata3: EH complete
[ 698.934573] ata3.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[ 698.934580] ata3.00: failed command: READ DMA EXT
[ 698.934586] ata3.00: cmd 25/00:00:f7:ad:aa/00:08:01:00:00/e0 tag 0 dma
1048576 in
res 40/00:00:00:4f:c2/00:00:00:00:00/00 Emask 0x4
(timeout)
[ 698.934589] ata3.00: status: { DRDY }
[ 703.986089] ata3: link is slow to respond, please be patient (ready=0)
[ 708.969586] ata3: device not ready (errno=-16), forcing hardreset
[ 708.969600] ata3: soft resetting link
[ 709.164047] ata3.00: configured for UDMA/100
[ 709.164063] ata3: EH complete
[ 741.938477] ata3.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[ 741.938484] ata3.00: failed command: READ DMA EXT
[ 741.938489] ata3.00: cmd 25/00:00:47:9f:a3/00:08:01:00:00/e0 tag 0 dma
1048576 in
res 40/00:00:00:4f:c2/00:00:00:00:00/00 Emask 0x4
(timeout)
[ 741.938492] ata3.00: status: { DRDY }
[ 746.977880] ata3: link is slow to respond, please be patient (ready=0)
[ 751.957395] ata3: device not ready (errno=-16), forcing hardreset
[ 751.957410] ata3: soft resetting link
[ 752.152040] ata3.00: configured for UDMA/100
[ 752.152055] ata3: EH complete
[ 784.941944] ata3.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[ 784.941951] ata3.00: failed command: READ DMA EXT
[ 784.941958] ata3.00: cmd 25/00:08:47:ac:da/00:04:01:00:00/e0 tag 0 dma
528384 in
res 40/00:00:00:4f:c2/00:00:00:00:00/00 Emask 0x4
(timeout)
[ 784.941961] ata3.00: status: { DRDY }
[ 789.985298] ata3: link is slow to respond, please be patient (ready=0)
[ 794.988755] ata3: device not ready (errno=-16), forcing hardreset
[ 794.988768] ata3: soft resetting link
[ 795.183363] ata3.00: configured for UDMA/100
[ 795.183377] ata3: EH complete
[ 827.945045] ata3.00: limiting speed to UDMA/33:PIO4
[ 827.945047] ata3.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[ 827.945051] ata3.00: failed command: READ DMA
[ 827.945055] ata3.00: cmd c8/00:58:9f:ed:a4/00:00:00:00:00/e1 tag 0 dma 45056
in
res 40/00:00:00:4f:c2/00:00:00:00:00/00 Emask 0x4
(timeout)
[ 827.945056] ata3.00: status: { DRDY }
[ 832.996422] ata3: link is slow to respond, please be patient (ready=0)
[ 837.983822] ata3: device not ready (errno=-16), forcing hardreset
[ 837.983836] ata3: soft resetting link
[ 838.178364] ata3.00: configured for UDMA/33
[ 838.178377] ata3: EH complete
--
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You are watching the assignee of the bug.
^ permalink raw reply
* 6869 linux-ide
From: beautyink @ 2016-11-19 13:30 UTC (permalink / raw)
To: linux-ide
[-- Attachment #1: EMAIL_579870443386_linux-ide.zip --]
[-- Type: application/zip, Size: 12520 bytes --]
^ permalink raw reply
* Re: [PATCH] ahci: always fall back to single-MSI mode
From: Tejun Heo @ 2016-11-21 16:08 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: michael, linux-ide
In-Reply-To: <1479474546-4413-1-git-send-email-hch@lst.de>
On Fri, Nov 18, 2016 at 02:09:06PM +0100, Christoph Hellwig wrote:
> Don't try to guess what the errors from pci_irq_alloc_vectors mean, as
> that's too fragile. Instead always try allocating a single vector
> when multi-MSI mode fails. This makes various intel Desktop and
> Laptop CPUs use MSI again.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> Reported-by: Michael Marley <michael@michaelmarley.com>
> Tested-by: Michael Marley <michael@michaelmarley.com>
> Fixes: 0b9e2988ab22 ("ahci: use pci_alloc_irq_vectors")
Applied to libata/for-4.9-fixes.
Thanks.
--
tejun
^ permalink raw reply
* (( UNO/WBO ))
From: U / N @ 2016-11-23 15:13 UTC (permalink / raw)
To: Recipients
Congratulations Beneficiary,
For more information please contact:
Name: Mrs. Sarah Amadi
Email: sarahamadi1970@gmail.com
Yours Faithfully,
Mr. Wu Hongbo
Under-Secretary-General for Economic and Social Affairs
^ permalink raw reply
* 26728 linux-ide
From: obsexitos @ 2016-11-24 6:07 UTC (permalink / raw)
To: linux-ide
[-- Attachment #1: INFO_763192453704_linux-ide.zip --]
[-- Type: application/zip, Size: 2556 bytes --]
^ permalink raw reply
* [PATCH v2 3/3] dt-bindings: ata: ahci_tegra: Add tegra210 AHCI
From: Preetham Chandru Ramchandra @ 2016-11-24 7:43 UTC (permalink / raw)
To: tj, swarren, thierry.reding, preetham260
Cc: ldewangan, linux-ide, vbyravarasu, pkunapuli, Preetham Chandru R
In-Reply-To: <1479973418-21351-1-git-send-email-pchandru@nvidia.com>
From: Preetham Chandru R <pchandru@nvidia.com>
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
---
.../bindings/ata/nvidia,tegra124-ahci.txt | 48 ++++++++++++++++------
1 file changed, 36 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
index 66c83c3..446214f 100644
--- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
+++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
@@ -1,9 +1,9 @@
-Tegra124 SoC SATA AHCI controller
+Tegra SoC SATA AHCI controller
Required properties :
-- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise,
- must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
- is tegra132.
+- compatible : Must be one of:
+ - Tegra124 : "nvidia,tegra124-ahci"
+ - Tegra210 : "nvidia,tegra210-ahci"
- reg : Should contain 2 entries:
- AHCI register set (SATA BAR5)
- SATA register set
@@ -13,8 +13,6 @@ Required properties :
- clock-names : Must include the following entries:
- sata
- sata-oob
- - cml1
- - pll_e
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
@@ -24,9 +22,35 @@ Required properties :
- phys : Must contain an entry for each entry in phy-names.
See ../phy/phy-bindings.txt for details.
- phy-names : Must include the following entries:
- - sata-phy : XUSB PADCTL SATA PHY
-- hvdd-supply : Defines the SATA HVDD regulator
-- vddio-supply : Defines the SATA VDDIO regulator
-- avdd-supply : Defines the SATA AVDD regulator
-- target-5v-supply : Defines the SATA 5V power regulator
-- target-12v-supply : Defines the SATA 12V power regulator
+ - For T124:
+ - sata-phy : XUSB PADCTL SATA PHY
+ - For T210:
+ - sata-0
+- For T124:
+ - hvdd-supply : Defines the SATA HVDD regulator
+ - vddio-supply : Defines the SATA VDDIO regulator
+ - avdd-supply : Defines the SATA AVDD regulator
+ - target-5v-supply : Defines the SATA 5V power regulator
+- For T210:
+ - l0-hvddio-sata-supply : Defines the SATA HVDDIO regulator
+ - l0-dvddio-sata-supply : Defines the SATA DVDDIO regulator
+ - hvdd-pex-pll-e-supply : Defines the PEX PLL_E regulator
+ - dvdd-sata-pll-supply : Defines the SATA PLL regulator
+ - hvdd-sata-supply : Defines the SATA HVDD regulator
+- nvidia,disable-features : Must include the following entries:
+ - devslp
+ - dipm
+
+Optional properties:
+- clock-names :
+ - cml1 :
+ cml1 clock is required by phy so it is optional to define
+ here as phy driver will be enabling this clock.
+ - pll_e :
+ pll_e is the parent of cml1 clock so it is optional to define
+ here as phy driver will be enabling this clock.
+- nvidia,disable-features :
+ - hipm
+ - ncq
+ - partial
+ - slumber
--
2.1.4
^ permalink raw reply related
* [PATCH v2 0/3] ADD AHCI support for tegra210
From: Preetham Chandru Ramchandra @ 2016-11-24 7:43 UTC (permalink / raw)
To: tj, swarren, thierry.reding, preetham260
Cc: ldewangan, linux-ide, vbyravarasu, pkunapuli, Preetham Chandru R
From: Preetham Chandru R <pchandru@nvidia.com>
1. ADD AHCI support for tegra210
2. Add support to disable DIPM, HIPM, DevSlp,
partial, slumber, NCQ features from DT.
3. Extend the tegra AHCI controller device tree binding with tegra210
---
Preetham Chandru R (3):
ata: ahci_tegra: add support for tegra210
ata: ahci_tegra: Add support to disable features
dt-bindings: ata: ahci_tegra: Add tegra210 AHCI support
.../bindings/ata/nvidia,tegra124-ahci.txt | 48 +-
drivers/ata/ahci_tegra.c | 581 ++++++++++++++++-----
2 files changed, 483 insertions(+), 146 deletions(-)
--
2.1.4
^ permalink raw reply
* [PATCH v2 2/3] ata: ahci_tegra: Add support to disable features
From: Preetham Chandru Ramchandra @ 2016-11-24 7:43 UTC (permalink / raw)
To: tj, swarren, thierry.reding, preetham260
Cc: ldewangan, linux-ide, vbyravarasu, pkunapuli, Preetham Chandru R
In-Reply-To: <1479973418-21351-1-git-send-email-pchandru@nvidia.com>
From: Preetham Chandru R <pchandru@nvidia.com>
Add support to disable DIPM, HIPM, DevSlp, partial, slumber and NCQ
features from DT. By default these features are enabled.
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
---
v2:
* This change was created by seperating
"ata: ahci_tegra: add support for tegra210" from v1
drivers/ata/ahci_tegra.c | 107 ++++++++++++++++++++++++++++++++++++-----------
1 file changed, 82 insertions(+), 25 deletions(-)
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index d12e2a9..443c3e8 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata/ahci_tegra.c
@@ -329,7 +329,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
return ret;
}
-static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
+static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
{
struct tegra_ahci_priv *tegra = hpriv->plat_data;
@@ -345,6 +345,85 @@ static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
regulator_bulk_disable(tegra->soc_data->num_supplies, tegra->supplies);
}
+static void tegra_ahci_host_stop(struct ata_host *host)
+{
+ struct ahci_host_priv *hpriv = host->private_data;
+
+ tegra_ahci_controller_deinit(hpriv);
+}
+
+static struct ata_port_operations ahci_tegra_port_ops = {
+ .inherits = &ahci_ops,
+ .host_stop = tegra_ahci_host_stop,
+};
+
+static struct ata_port_info ahci_tegra_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &ahci_tegra_port_ops,
+};
+
+static void tegra_ahci_disable_devslp(struct tegra_ahci_priv *tegra)
+{
+ tegra_ahci_aux_update(tegra, 0, SDS_SUPPORT, SATA_AUX_MISC_CNTL_1_0);
+}
+
+static void tegra_ahci_disable_hipm(struct tegra_ahci_priv *tegra)
+{
+ tegra_ahci_scfg_update(tegra, 0, T_SATA0_AHCI_HBA_CAP_BKDR_SALP,
+ T_SATA0_AHCI_HBA_CAP_BKDR);
+}
+
+static void tegra_ahci_disable_partial(struct tegra_ahci_priv *tegra)
+{
+ tegra_ahci_scfg_update(tegra, 0,
+ T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP,
+ T_SATA0_AHCI_HBA_CAP_BKDR);
+}
+
+static void tegra_ahci_disable_slumber(struct tegra_ahci_priv *tegra)
+{
+ tegra_ahci_scfg_update(tegra, 0,
+ T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP,
+ T_SATA0_AHCI_HBA_CAP_BKDR);
+}
+
+static void tegra_ahci_disable_ncq(struct tegra_ahci_priv *tegra)
+{
+ tegra_ahci_scfg_update(tegra, 0, T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ,
+ T_SATA0_AHCI_HBA_CAP_BKDR);
+}
+
+static void tegra_ahci_disable_features(struct ahci_host_priv *hpriv)
+{
+ struct tegra_ahci_priv *tegra = hpriv->plat_data;
+ struct platform_device *pdev = tegra->pdev;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct property *prop;
+ const char *feature;
+
+ if (of_property_count_strings(np, "nvidia,disable-features") <= 0)
+ return;
+
+ of_property_for_each_string(np, "nvidia,disable-features", prop,
+ feature) {
+ if (!strcmp(feature, "devslp"))
+ tegra_ahci_disable_devslp(tegra);
+ else if (!strcmp(feature, "hipm"))
+ tegra_ahci_disable_hipm(tegra);
+ else if (!strcmp(feature, "ncq"))
+ tegra_ahci_disable_ncq(tegra);
+ else if (!strcmp(feature, "dipm"))
+ ahci_tegra_port_info.flags |= ATA_FLAG_NO_DIPM;
+ else if (!strcmp(feature, "partial"))
+ tegra_ahci_disable_partial(tegra);
+ else if (!strcmp(feature, "slumber"))
+ tegra_ahci_disable_slumber(tegra);
+ }
+}
+
static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
{
struct tegra_ahci_priv *tegra = hpriv->plat_data;
@@ -458,36 +537,14 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
tegra_ahci_sata_update(tegra, 0, SATA_CONFIGURATION_CLK_OVERRIDE,
SATA_CONFIGURATION_0);
+ tegra_ahci_disable_features(hpriv);
+
tegra_ahci_sata_update(tegra, IP_INT_MASK, IP_INT_MASK,
SATA_INTR_MASK_0);
return 0;
}
-static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
-{
- tegra_ahci_power_off(hpriv);
-}
-
-static void tegra_ahci_host_stop(struct ata_host *host)
-{
- struct ahci_host_priv *hpriv = host->private_data;
-
- tegra_ahci_controller_deinit(hpriv);
-}
-
-static struct ata_port_operations ahci_tegra_port_ops = {
- .inherits = &ahci_ops,
- .host_stop = tegra_ahci_host_stop,
-};
-
-static const struct ata_port_info ahci_tegra_port_info = {
- .flags = AHCI_FLAG_COMMON,
- .pio_mask = ATA_PIO4,
- .udma_mask = ATA_UDMA6,
- .port_ops = &ahci_tegra_port_ops,
-};
-
static const struct of_device_id tegra_ahci_of_match[] = {
{
.compatible = "nvidia,tegra124-ahci",
--
2.1.4
^ permalink raw reply related
* [PATCH v2 1/3] ata: ahci_tegra: add support for tegra210
From: Preetham Chandru Ramchandra @ 2016-11-24 7:43 UTC (permalink / raw)
To: tj, swarren, thierry.reding, preetham260
Cc: ldewangan, linux-ide, vbyravarasu, pkunapuli, Preetham Chandru R
In-Reply-To: <1479973418-21351-1-git-send-email-pchandru@nvidia.com>
From: Preetham Chandru R <pchandru@nvidia.com>
Add AHCI support for tegra210
1. Moved tegra124 specifics to tegra124_ahci_init.
2. Separated out the regulators needed for tegra124 and tegra210.
3. Set the LPM capabilities
4. Create inline functions for read/write and modify to
SATA, SATA Config and SATA Aux registers.
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
---
v2:
* Fixed indentation issues
* Moved the change to disable DIPM, HIPM, DevSlp, partial,
slumber and NCQ into a separate patch
drivers/ata/ahci_tegra.c | 478 ++++++++++++++++++++++++++++++++++-------------
1 file changed, 348 insertions(+), 130 deletions(-)
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index 3a62eb2..d12e2a9 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata/ahci_tegra.c
@@ -33,32 +33,74 @@
#define DRV_NAME "tegra-ahci"
+#define SATA_FPCI_BAR5_0 0x94
+#define FPCI_BAR5_START_MASK (0xFFFFFFF << 4)
+#define FPCI_BAR5_START (0x0040020 << 4)
+#define FPCI_BAR5_ACCESS_TYPE (0x1)
+
#define SATA_CONFIGURATION_0 0x180
-#define SATA_CONFIGURATION_EN_FPCI BIT(0)
+#define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
+#define SATA_CONFIGURATION_CLK_OVERRIDE BIT(31)
+
+#define SATA_INTR_MASK_0 0x188
+#define IP_INT_MASK BIT(16)
#define SCFG_OFFSET 0x1000
-#define T_SATA0_CFG_1 0x04
-#define T_SATA0_CFG_1_IO_SPACE BIT(0)
-#define T_SATA0_CFG_1_MEMORY_SPACE BIT(1)
-#define T_SATA0_CFG_1_BUS_MASTER BIT(2)
-#define T_SATA0_CFG_1_SERR BIT(8)
+#define T_SATA_CFG_1 0x4
+#define T_SATA_CFG_1_IO_SPACE BIT(0)
+#define T_SATA_CFG_1_MEMORY_SPACE BIT(1)
+#define T_SATA_CFG_1_BUS_MASTER BIT(2)
+#define T_SATA_CFG_1_SERR BIT(8)
+
+#define T_SATA_CFG_9 0x24
+#define T_SATA_CFG_9_BASE_ADDRESS 0x40020000
+
+#define T_SATA0_CFG_35 0x94
+#define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7FF << 2)
+#define T_SATA0_CFG_35_IDP_INDEX (0x2A << 2)
-#define T_SATA0_CFG_9 0x24
-#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13
+#define T_SATA0_AHCI_IDP1 0x98
+#define T_SATA0_AHCI_IDP1_DATA (0x400040)
-#define SATA_FPCI_BAR5 0x94
-#define SATA_FPCI_BAR5_START_SHIFT 4
+#define T_SATA0_CFG_PHY_1 0x12C
+#define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23)
+#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22)
-#define SATA_INTR_MASK 0x188
-#define SATA_INTR_MASK_IP_INT_MASK BIT(16)
+#define T_SATA0_NVOOB 0x114
+#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
+#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
+#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
+#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
+#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
+#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
+
+#define T_SATA_CFG_PHY_0 0x120
+#define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11)
+#define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24)
+
+#define FUSE_SATA_CALIB 0x124
+#define FUSE_SATA_CALIB_MASK 0x3
+
+#define T_SATA0_CFG2NVOOB_2 0x134
+#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff << 18)
+#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
+#define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13)
+#define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14)
+#define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26)
+#define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17)
+#define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30)
-#define T_SATA0_BKDOOR_CC 0x4a4
+#define T_SATA_BKDOOR_CC 0x4A4
+#define T_SATA_BKDOOR_CC_CLASS_CODE_MASK (0xFFFF << 16)
+#define T_SATA_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
+#define T_SATA_BKDOOR_CC_PROG_IF_MASK (0xFF << 8)
+#define T_SATA_BKDOOR_CC_PROG_IF (0x01 << 8)
-#define T_SATA0_CFG_SATA 0x54c
-#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
+#define T_SATA_CFG_SATA 0x54C
+#define T_SATA_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
#define T_SATA0_CFG_MISC 0x550
@@ -82,8 +124,27 @@
#define T_SATA0_CHX_PHY_CTRL11 0x6d0
#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
-#define FUSE_SATA_CALIB 0x124
-#define FUSE_SATA_CALIB_MASK 0x3
+/* Electrical settings for better link stability */
+#define T_SATA0_CHX_PHY_CTRL17_0 0x6e8
+#define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000
+#define T_SATA0_CHX_PHY_CTRL18_0 0x6ec
+#define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000
+#define T_SATA0_CHX_PHY_CTRL20_0 0x6f4
+#define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1
+#define T_SATA0_CHX_PHY_CTRL21_0 0x6f8
+#define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1
+
+/* AUX Registers */
+#define SATA_AUX_MISC_CNTL_1_0 0x8
+#define DEVSLP_OVERRIDE BIT(17)
+#define SDS_SUPPORT BIT(13)
+#define DESO_SUPPORT BIT(15)
+
+#define SATA_AUX_RX_STAT_INT_0 0xc
+#define SATA_DEVSLP BIT(7)
+
+#define SATA_AUX_SPARE_CFG0_0 0x18
+#define MDAT_TIMER_AFTER_PG_VALID BIT(14)
struct sata_pad_calibration {
u8 gen1_tx_amp;
@@ -99,15 +160,135 @@ static const struct sata_pad_calibration tegra124_pad_calibration[] = {
{0x14, 0x0e, 0x1a, 0x0e},
};
+struct tegra_ahci_ops {
+ int (*init)(struct ahci_host_priv *);
+};
+
+struct tegra_ahci_soc {
+ const char *const *supply_names;
+ unsigned int num_supplies;
+ struct tegra_ahci_ops ops;
+};
+
struct tegra_ahci_priv {
- struct platform_device *pdev;
- void __iomem *sata_regs;
- struct reset_control *sata_rst;
- struct reset_control *sata_oob_rst;
- struct reset_control *sata_cold_rst;
+ struct platform_device *pdev;
+ void __iomem *sata_regs;
+ void __iomem *sata_aux_regs;
+ struct reset_control *sata_rst;
+ struct reset_control *sata_oob_rst;
+ struct reset_control *sata_cold_rst;
/* Needs special handling, cannot use ahci_platform */
- struct clk *sata_clk;
- struct regulator_bulk_data supplies[5];
+ struct clk *sata_clk;
+ struct regulator_bulk_data *supplies;
+ struct tegra_ahci_soc *soc_data;
+};
+
+static const char *const tegra124_supply_names[] = {
+ "avdd", "hvdd", "vddio", "target-5v", "target-12v"
+};
+
+static inline void tegra_ahci_sata_update(struct tegra_ahci_priv *tegra,
+ u32 val, u32 mask, u32 offset)
+{
+ u32 uval;
+
+ uval = readl(tegra->sata_regs + offset);
+ uval = (uval & ~mask) | (val & mask);
+ writel(uval, tegra->sata_regs + offset);
+}
+
+static inline void tegra_ahci_scfg_writel(struct tegra_ahci_priv *tegra,
+ u32 val, u32 offset)
+{
+ writel(val, tegra->sata_regs + SCFG_OFFSET + offset);
+}
+
+static inline void tegra_ahci_scfg_update(struct tegra_ahci_priv *tegra,
+ u32 val, u32 mask, u32 offset)
+{
+ u32 uval;
+
+ uval = readl(tegra->sata_regs + SCFG_OFFSET + offset);
+ uval = (uval & ~mask) | (val & mask);
+ writel(uval, tegra->sata_regs + SCFG_OFFSET + offset);
+}
+
+static inline u32 tegra_ahci_aux_readl(struct tegra_ahci_priv *tegra,
+ u32 offset)
+{
+ return readl(tegra->sata_aux_regs + offset);
+}
+
+static inline void tegra_ahci_aux_update(struct tegra_ahci_priv *tegra, u32 val,
+ u32 mask, u32 offset)
+{
+ u32 uval;
+
+ uval = readl(tegra->sata_aux_regs + offset);
+ uval = (uval & ~mask) | (val & mask);
+ writel(uval, tegra->sata_aux_regs + offset);
+}
+
+static int tegra124_ahci_init(struct ahci_host_priv *hpriv)
+{
+ struct tegra_ahci_priv *tegra = hpriv->plat_data;
+ struct sata_pad_calibration calib;
+ int ret;
+ u32 val;
+ u32 mask;
+
+ /* Pad calibration */
+ ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
+ if (ret)
+ return ret;
+
+ calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
+
+ tegra_ahci_scfg_writel(tegra, BIT(0), T_SATA0_INDEX);
+
+ mask = T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK |
+ T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
+ val = (calib.gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT) |
+ (calib.gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT);
+ tegra_ahci_scfg_update(tegra, val, mask, T_SATA0_CHX_PHY_CTRL1_GEN1);
+
+ mask = T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK |
+ T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
+ val = (calib.gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT) |
+ (calib.gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT);
+ tegra_ahci_scfg_update(tegra, val, mask, T_SATA0_CHX_PHY_CTRL1_GEN2);
+
+ tegra_ahci_scfg_writel(tegra,
+ T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
+ T_SATA0_CHX_PHY_CTRL11);
+ tegra_ahci_scfg_writel(tegra,
+ T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
+ T_SATA0_CHX_PHY_CTRL2);
+
+ tegra_ahci_scfg_writel(tegra, 0, T_SATA0_INDEX);
+
+ return 0;
+}
+
+static const struct tegra_ahci_soc tegra124_ahci_soc_data = {
+ .supply_names = tegra124_supply_names,
+ .num_supplies = ARRAY_SIZE(tegra124_supply_names),
+ .ops = {
+ .init = tegra124_ahci_init,
+ },
+};
+
+static const char *const tegra210_supply_names[] = {
+ "dvdd-sata-pll",
+ "hvdd-sata",
+ "l0-hvddio-sata",
+ "l0-dvddio-sata",
+ "hvdd-pex-pll-e"
+};
+
+static const struct tegra_ahci_soc tegra210_ahci_soc_data = {
+ .supply_names = tegra210_supply_names,
+ .num_supplies = ARRAY_SIZE(tegra210_supply_names),
};
static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
@@ -115,7 +296,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
struct tegra_ahci_priv *tegra = hpriv->plat_data;
int ret;
- ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
+ ret = regulator_bulk_enable(tegra->soc_data->num_supplies,
tegra->supplies);
if (ret)
return ret;
@@ -144,8 +325,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
disable_regulators:
- regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
-
+ regulator_bulk_disable(tegra->soc_data->num_supplies, tegra->supplies);
return ret;
}
@@ -162,101 +342,124 @@ static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
clk_disable_unprepare(tegra->sata_clk);
tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
- regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
+ regulator_bulk_disable(tegra->soc_data->num_supplies, tegra->supplies);
}
static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
{
struct tegra_ahci_priv *tegra = hpriv->plat_data;
int ret;
- unsigned int val;
- struct sata_pad_calibration calib;
+ u32 val;
+ u32 mask;
ret = tegra_ahci_power_on(hpriv);
- if (ret) {
- dev_err(&tegra->pdev->dev,
- "failed to power on AHCI controller: %d\n", ret);
- return ret;
- }
-
- val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
- val |= SATA_CONFIGURATION_EN_FPCI;
- writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
-
- /* Pad calibration */
-
- ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
- if (ret) {
- dev_err(&tegra->pdev->dev,
- "failed to read calibration fuse: %d\n", ret);
+ if (ret)
return ret;
- }
-
- calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
-
- writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
-
- val = readl(tegra->sata_regs +
- SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
- val |= calib.gen1_tx_amp <<
- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
- val |= calib.gen1_tx_peak <<
- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
- writel(val, tegra->sata_regs + SCFG_OFFSET +
- T_SATA0_CHX_PHY_CTRL1_GEN1);
-
- val = readl(tegra->sata_regs +
- SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
- val |= calib.gen2_tx_amp <<
- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
- val |= calib.gen2_tx_peak <<
- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
- writel(val, tegra->sata_regs + SCFG_OFFSET +
- T_SATA0_CHX_PHY_CTRL1_GEN2);
-
- writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
- tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
- writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
- tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
-
- writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
-
- /* Program controller device ID */
- val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
- val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
- writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
-
- writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
-
- val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
- val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
- writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
-
- /* Enable IO & memory access, bus master mode */
-
- val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
- val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
- T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR;
- writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
-
- /* Program SATA MMIO */
-
- writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
- tegra->sata_regs + SATA_FPCI_BAR5);
-
- writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
- tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
-
- /* Unmask SATA interrupts */
-
- val = readl(tegra->sata_regs + SATA_INTR_MASK);
- val |= SATA_INTR_MASK_IP_INT_MASK;
- writel(val, tegra->sata_regs + SATA_INTR_MASK);
+ /*
+ * Program the following SATA IPFS registers
+ * to allow SW accesses to SATA's MMIO Register
+ */
+ mask = FPCI_BAR5_START_MASK | FPCI_BAR5_ACCESS_TYPE;
+ val = FPCI_BAR5_START | FPCI_BAR5_ACCESS_TYPE;
+ tegra_ahci_sata_update(tegra, val, mask, SATA_FPCI_BAR5_0);
+
+ /* Program the following SATA IPFS register to enable the SATA */
+ val = SATA_CONFIGURATION_0_EN_FPCI;
+ tegra_ahci_sata_update(tegra, val, val, SATA_CONFIGURATION_0);
+
+ /* Electrical settings for better link stability */
+ tegra_ahci_scfg_writel(tegra,
+ T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1,
+ T_SATA0_CHX_PHY_CTRL17_0);
+ tegra_ahci_scfg_writel(tegra,
+ T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2,
+ T_SATA0_CHX_PHY_CTRL18_0);
+ tegra_ahci_scfg_writel(tegra,
+ T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1,
+ T_SATA0_CHX_PHY_CTRL20_0);
+ tegra_ahci_scfg_writel(tegra,
+ T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2,
+ T_SATA0_CHX_PHY_CTRL21_0);
+
+ /* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */
+
+ mask = T_SATA_CFG_PHY_0_MASK_SQUELCH |
+ T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
+ val = T_SATA_CFG_PHY_0_MASK_SQUELCH;
+ val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
+ tegra_ahci_scfg_update(tegra, val, mask, T_SATA_CFG_PHY_0);
+
+ mask = (T_SATA0_NVOOB_COMMA_CNT_MASK |
+ T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
+ T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
+ val = (T_SATA0_NVOOB_COMMA_CNT |
+ T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
+ T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
+ tegra_ahci_scfg_update(tegra, val, mask, T_SATA0_NVOOB);
+
+ /*
+ * Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to 58.8ns
+ */
+ mask = T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
+ val = T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
+ tegra_ahci_scfg_update(tegra, val, mask, T_SATA0_CFG2NVOOB_2);
+
+ if (tegra->soc_data->ops.init)
+ tegra->soc_data->ops.init(hpriv);
+
+ /*
+ * Program the following SATA configuration registers
+ * to initialize SATA
+ */
+ val = (T_SATA_CFG_1_IO_SPACE | T_SATA_CFG_1_MEMORY_SPACE |
+ T_SATA_CFG_1_BUS_MASTER | T_SATA_CFG_1_SERR);
+ tegra_ahci_scfg_update(tegra, val, val, T_SATA_CFG_1);
+ tegra_ahci_scfg_writel(tegra, T_SATA_CFG_9_BASE_ADDRESS, T_SATA_CFG_9);
+
+ /* Program Class Code and Programming interface for SATA */
+ val = T_SATA_CFG_SATA_BACKDOOR_PROG_IF_EN;
+ tegra_ahci_scfg_update(tegra, val, val, T_SATA_CFG_SATA);
+
+ mask = T_SATA_BKDOOR_CC_CLASS_CODE_MASK | T_SATA_BKDOOR_CC_PROG_IF_MASK;
+ val = T_SATA_BKDOOR_CC_CLASS_CODE | T_SATA_BKDOOR_CC_PROG_IF;
+ tegra_ahci_scfg_update(tegra, val, mask, T_SATA_BKDOOR_CC);
+
+ tegra_ahci_scfg_update(tegra, 0, T_SATA_CFG_SATA_BACKDOOR_PROG_IF_EN,
+ T_SATA_CFG_SATA);
+
+ /* Enabling LPM capabilities through Backdoor Programming */
+ val = (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
+ T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
+ T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
+ T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM);
+ tegra_ahci_scfg_update(tegra, val, val, T_SATA0_AHCI_HBA_CAP_BKDR);
+
+ /* SATA Second Level Clock Gating configuration
+ * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane
+ * IDDQ Signals
+ */
+ mask = T_SATA0_CFG_35_IDP_INDEX_MASK;
+ val = T_SATA0_CFG_35_IDP_INDEX;
+ tegra_ahci_scfg_update(tegra, val, mask, T_SATA0_CFG_35);
+ tegra_ahci_scfg_writel(tegra, T_SATA0_AHCI_IDP1_DATA,
+ T_SATA0_AHCI_IDP1);
+ val = (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
+ T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN);
+ tegra_ahci_scfg_update(tegra, val, val, T_SATA0_CFG_PHY_1);
+
+ /*
+ * Indicate Sata only has the capability to enter DevSleep
+ * from slumber link.
+ */
+ tegra_ahci_aux_update(tegra, DESO_SUPPORT, DESO_SUPPORT,
+ SATA_AUX_MISC_CNTL_1_0);
+ /* Enabling IPFS Clock Gating */
+ tegra_ahci_sata_update(tegra, 0, SATA_CONFIGURATION_CLK_OVERRIDE,
+ SATA_CONFIGURATION_0);
+
+ tegra_ahci_sata_update(tegra, IP_INT_MASK, IP_INT_MASK,
+ SATA_INTR_MASK_0);
return 0;
}
@@ -274,19 +477,24 @@ static void tegra_ahci_host_stop(struct ata_host *host)
}
static struct ata_port_operations ahci_tegra_port_ops = {
- .inherits = &ahci_ops,
- .host_stop = tegra_ahci_host_stop,
+ .inherits = &ahci_ops,
+ .host_stop = tegra_ahci_host_stop,
};
static const struct ata_port_info ahci_tegra_port_info = {
- .flags = AHCI_FLAG_COMMON,
- .pio_mask = ATA_PIO4,
- .udma_mask = ATA_UDMA6,
- .port_ops = &ahci_tegra_port_ops,
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &ahci_tegra_port_ops,
};
static const struct of_device_id tegra_ahci_of_match[] = {
- { .compatible = "nvidia,tegra124-ahci" },
+ {
+ .compatible = "nvidia,tegra124-ahci",
+ .data = &tegra124_ahci_soc_data},
+ {
+ .compatible = "nvidia,tegra210-ahci",
+ .data = &tegra210_ahci_soc_data},
{}
};
MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
@@ -301,6 +509,7 @@ static int tegra_ahci_probe(struct platform_device *pdev)
struct tegra_ahci_priv *tegra;
struct resource *res;
int ret;
+ unsigned int i;
hpriv = ahci_platform_get_resources(pdev);
if (IS_ERR(hpriv))
@@ -311,13 +520,18 @@ static int tegra_ahci_probe(struct platform_device *pdev)
return -ENOMEM;
hpriv->plat_data = tegra;
-
tegra->pdev = pdev;
+ tegra->soc_data =
+ (struct tegra_ahci_soc *)of_device_get_match_data(&pdev->dev);
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(tegra->sata_regs))
return PTR_ERR(tegra->sata_regs);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(tegra->sata_aux_regs))
+ return PTR_ERR(tegra->sata_aux_regs);
tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
if (IS_ERR(tegra->sata_rst)) {
@@ -343,13 +557,17 @@ static int tegra_ahci_probe(struct platform_device *pdev)
return PTR_ERR(tegra->sata_clk);
}
- tegra->supplies[0].supply = "avdd";
- tegra->supplies[1].supply = "hvdd";
- tegra->supplies[2].supply = "vddio";
- tegra->supplies[3].supply = "target-5v";
- tegra->supplies[4].supply = "target-12v";
+ tegra->supplies = devm_kcalloc(&pdev->dev,
+ tegra->soc_data->num_supplies,
+ sizeof(*tegra->supplies), GFP_KERNEL);
+ if (!tegra->supplies)
+ return -ENOMEM;
+
+ for (i = 0; i < tegra->soc_data->num_supplies; i++)
+ tegra->supplies[i].supply = tegra->soc_data->supply_names[i];
- ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies),
+ ret = devm_regulator_bulk_get(&pdev->dev,
+ tegra->soc_data->num_supplies,
tegra->supplies);
if (ret) {
dev_err(&pdev->dev, "Failed to get regulators\n");
@@ -377,13 +595,13 @@ static struct platform_driver tegra_ahci_driver = {
.probe = tegra_ahci_probe,
.remove = ata_platform_remove_one,
.driver = {
- .name = DRV_NAME,
- .of_match_table = tegra_ahci_of_match,
- },
+ .name = DRV_NAME,
+ .of_match_table = tegra_ahci_of_match,
+ },
/* LP0 suspend support not implemented */
};
module_platform_driver(tegra_ahci_driver);
MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
-MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
+MODULE_DESCRIPTION("Tegra AHCI SATA driver");
MODULE_LICENSE("GPL v2");
--
2.1.4
^ permalink raw reply related
* 54299 linux-ide
From: robert.berry @ 2016-11-24 17:09 UTC (permalink / raw)
To: linux-ide
[-- Attachment #1: INFO_994466_linux-ide.zip --]
[-- Type: application/zip, Size: 2507 bytes --]
^ permalink raw reply
* Re: [RESEND PATCH] arm: assabet_defconfig: disable IDE subsystem
From: Arnd Bergmann @ 2016-11-25 22:22 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Bartlomiej Zolnierkiewicz, Russell King - ARM Linux,
Dmitry Eremin-Solenikov, Kevin Hilman, Nori, Sekhar, linux-kernel,
linux-ide, Olof Johansson
In-Reply-To: <1512445.DtnT51NQqg@amdc3058>
On Monday, October 31, 2016 7:24:46 PM CET Bartlomiej Zolnierkiewicz wrote:
> On Monday, October 31, 2016 07:14:13 PM Bartlomiej Zolnierkiewicz wrote:
> > On Monday, October 31, 2016 03:46:22 PM Russell King - ARM Linux wrote:
> > > On Wed, Oct 26, 2016 at 07:01:12PM +0200, Bartlomiej Zolnierkiewicz wrote:
> > > > > I'd be fine with just getting a pull request with all the patches that
> > > > > had no negative feedback and that were not already applied (if any).
> > > >
> > > > Here it is (sorry for taking so long).
> > >
> > > I've just been digging in the dmesg logs from when I was using the
> > > Assabet+Neponset as my firewall, and it was having to use the IDE
> > > ide-cs driver rather than the pata pcmcia driver.
> > >
> > > I don't recall whether the pata pcmcia driver was a problem or not,
> > > as the PCMCIA interface can't cope with _any_ 32-bit accesses. I
> > > think PATA tries to use the "highest" possible access size by
> > > default...
> >
> > It doesn't actually - it defaults to 16-bits for PIO data access and
> > you must explicitly enable 32-bits using ATA_PFLAG_PIO32 port flag
> > (pata_pcmcia doesn't set it so it should be okay). Also taskfile
> > registers are accessed using 8-bits access by default transport
> > functions (which are used by pata_pcmcia).
>
> Please also note that:
>
> - assebet_defconfig currently doesn't even enable ide-cs
> (CONFIG_BLK_DEV_IDECS) in the mainline kernel
>
> - neponset_defconfig doesn't even enable IDE (CONFIG_IDE)
> in the mainline kernel
>
> so there is no risk of breaking anything..
I noticed this older pull request in my todo folder, my interpretation
is that the concern was resolved and we simply missed it.
I've pulled it into next/defconfig for v4.10 now, with the above
in the merge commit text for reference.
Thanks,
Arnd
^ permalink raw reply
* (unknown),
From: obsexitos @ 2016-11-27 7:04 UTC (permalink / raw)
To: linux-ide
[-- Attachment #1: INFO_006036_linux-ide.zip --]
[-- Type: application/zip, Size: 1883 bytes --]
^ permalink raw reply
* (unknown),
From: beautyink @ 2016-11-27 14:25 UTC (permalink / raw)
To: linux-ide
[-- Attachment #1: MESSAGE_412161257221478_linux-ide.zip --]
[-- Type: application/zip, Size: 3511 bytes --]
^ permalink raw reply
* [PATCH] ata: disable port while unloading ATA controller driver
From: Vladimir Zapolskiy @ 2016-11-27 23:18 UTC (permalink / raw)
To: Tejun Heo; +Cc: Bartlomiej Zolnierkiewicz, linux-ide
While removing ATA controller driver ata_port_detach() sets
ATA_PFLAG_UNLOADING flag and charges the error handler, however actual
port disabling does not happen due to unset ATA_PFLAG_EH_PENDING flag.
To take care about clean port removal and ATA_PFLAG_EH_PENDING flag
setting it is sufficient to replace ata_port_schedule_eh() call with
ata_port_freeze().
The problem is reported by an assertion in ata_port_detach(),
if a controller driver is unloaded manually or on boot with
DEBUG_TEST_DRIVER_REMOVE option enabled:
# rmmod ahci_imx
WARNING: CPU: 2 PID: 379 at drivers/ata/libata-core.c:6484 ata_port_detach+0x11c/0x12c
Modules linked in: ahci_imx(-) i2c_imx
CPU: 2 PID: 379 Comm: rmmod Not tainted 4.9.0-rc6+ #66
Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
Backtrace:
[<>] (dump_backtrace) from [<>] (show_stack+0x18/0x1c)
[<>] (show_stack) from [<>] (dump_stack+0xb4/0xe8)
[<>] (dump_stack) from [<>] (__warn+0xd8/0x104)
[<>] (__warn) from [<>] (warn_slowpath_null+0x28/0x30)
[<>] (warn_slowpath_null) from [<>] (ata_port_detach+0x11c/0x12c)
[<>] (ata_port_detach) from [<>] (ata_platform_remove_one+0x2c/0x44)
[<>] (ata_platform_remove_one) from [<>] (platform_drv_remove+0x2c/0x44)
[<>] (platform_drv_remove) from [<>] (__device_release_driver+0x90/0x12c)
[<>] (__device_release_driver) from [<>] (driver_detach+0xc0/0xc4)
[<>] (driver_detach) from [<>] (bus_remove_driver+0x64/0xdc)
[<>] (bus_remove_driver) from [<>] (driver_unregister+0x30/0x50)
[<>] (driver_unregister) from [<>] (platform_driver_unregister+0x14/0x18)
[<>] (platform_driver_unregister) from [<>] (imx_ahci_driver_exit+0x14/0x1c [ahci_imx])
[<>] (imx_ahci_driver_exit [ahci_imx]) from [<>] (SyS_delete_module+0x140/0x1f4)
[<>] (SyS_delete_module) from [<>] (ret_fast_syscall+0x0/0x1c)
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
drivers/ata/libata-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 43842fd..6d64fe3 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -6505,7 +6505,7 @@ static void ata_port_detach(struct ata_port *ap)
/* tell EH we're leaving & flush EH */
spin_lock_irqsave(ap->lock, flags);
ap->pflags |= ATA_PFLAG_UNLOADING;
- ata_port_schedule_eh(ap);
+ ata_port_freeze(ap);
spin_unlock_irqrestore(ap->lock, flags);
/* wait till EH commits suicide */
--
2.10.2
^ permalink raw reply related
* Re: [PATCH] ata: disable port while unloading ATA controller driver
From: Vladimir Zapolskiy @ 2016-11-27 23:30 UTC (permalink / raw)
To: Tejun Heo, Bartlomiej Zolnierkiewicz; +Cc: linux-ide
In-Reply-To: <20161127231856.11466-1-vz@mleia.com>
On 11/28/2016 01:18 AM, Vladimir Zapolskiy wrote:
> While removing ATA controller driver ata_port_detach() sets
> ATA_PFLAG_UNLOADING flag and charges the error handler, however actual
> port disabling does not happen due to unset ATA_PFLAG_EH_PENDING flag.
>
> To take care about clean port removal and ATA_PFLAG_EH_PENDING flag
> setting it is sufficient to replace ata_port_schedule_eh() call with
> ata_port_freeze().
>
> The problem is reported by an assertion in ata_port_detach(),
> if a controller driver is unloaded manually or on boot with
> DEBUG_TEST_DRIVER_REMOVE option enabled:
>
> # rmmod ahci_imx
> WARNING: CPU: 2 PID: 379 at drivers/ata/libata-core.c:6484 ata_port_detach+0x11c/0x12c
> Modules linked in: ahci_imx(-) i2c_imx
> CPU: 2 PID: 379 Comm: rmmod Not tainted 4.9.0-rc6+ #66
> Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
> Backtrace:
> [<>] (dump_backtrace) from [<>] (show_stack+0x18/0x1c)
> [<>] (show_stack) from [<>] (dump_stack+0xb4/0xe8)
> [<>] (dump_stack) from [<>] (__warn+0xd8/0x104)
> [<>] (__warn) from [<>] (warn_slowpath_null+0x28/0x30)
> [<>] (warn_slowpath_null) from [<>] (ata_port_detach+0x11c/0x12c)
> [<>] (ata_port_detach) from [<>] (ata_platform_remove_one+0x2c/0x44)
> [<>] (ata_platform_remove_one) from [<>] (platform_drv_remove+0x2c/0x44)
> [<>] (platform_drv_remove) from [<>] (__device_release_driver+0x90/0x12c)
> [<>] (__device_release_driver) from [<>] (driver_detach+0xc0/0xc4)
> [<>] (driver_detach) from [<>] (bus_remove_driver+0x64/0xdc)
> [<>] (bus_remove_driver) from [<>] (driver_unregister+0x30/0x50)
> [<>] (driver_unregister) from [<>] (platform_driver_unregister+0x14/0x18)
> [<>] (platform_driver_unregister) from [<>] (imx_ahci_driver_exit+0x14/0x1c [ahci_imx])
> [<>] (imx_ahci_driver_exit [ahci_imx]) from [<>] (SyS_delete_module+0x140/0x1f4)
> [<>] (SyS_delete_module) from [<>] (ret_fast_syscall+0x0/0x1c)
>
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> ---
Tejun, Bartlomiej,
you may consider this change as RFC, because I'm not an expert in ATA
subsystem, for example I hesitate to claim that ata_port_freeze() is
actually needed here, in my test case (iMX6Q SabreAuto without
a connected SATA drive) a weaker ata_port_abort() also works well.
I suppose that the change is in the kernel sources for a long time,
so you may consider to send the fix to the maintainers of stable
branches, feel free to ask me to find a commit for Fixes tag.
--
With best wishes,
Vladimir
^ permalink raw reply
* Re: [v2,1/3] ata: ahci_tegra: add support for tegra210
From: Mikko Perttunen @ 2016-11-28 12:32 UTC (permalink / raw)
To: PREETHAM RAMACHANDRA, preetham260-Re5JQEeQqe8AvxtiuMwx3w
Cc: tj-DgEjT+Ai2ygdnm+yROfE0A, swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
ldewangan-DDmLM1+adcrQT0dZR+AlfA,
linux-ide-u79uwXL29TY76Z2rM5mHXA,
vbyravarasu-DDmLM1+adcrQT0dZR+AlfA,
pkunapuli-DDmLM1+adcrQT0dZR+AlfA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479973418-21351-2-git-send-email-pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
+Cc linux-tegra
Hi Preetham,
I'll do a review pass. Please also Cc the next version to
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org so that more Tegra developers have visibility.
On 24.11.2016 09:43, PREETHAM RAMACHANDRA wrote:
> From: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Add AHCI support for tegra210
> 1. Moved tegra124 specifics to tegra124_ahci_init.
> 2. Separated out the regulators needed for tegra124 and tegra210.
> 3. Set the LPM capabilities
> 4. Create inline functions for read/write and modify to
> SATA, SATA Config and SATA Aux registers.
>
> Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> v2:
> * Fixed indentation issues
> * Moved the change to disable DIPM, HIPM, DevSlp, partial,
> slumber and NCQ into a separate patch
>
> drivers/ata/ahci_tegra.c | 478 ++++++++++++++++++++++++++++++++++-------------
> 1 file changed, 348 insertions(+), 130 deletions(-)
>
> diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
> index 3a62eb2..d12e2a9 100644
> --- a/drivers/ata/ahci_tegra.c
> +++ b/drivers/ata/ahci_tegra.c
> @@ -33,32 +33,74 @@
>
> #define DRV_NAME "tegra-ahci"
>
> +#define SATA_FPCI_BAR5_0 0x94
> +#define FPCI_BAR5_START_MASK (0xFFFFFFF << 4)
> +#define FPCI_BAR5_START (0x0040020 << 4)
> +#define FPCI_BAR5_ACCESS_TYPE (0x1)
Please use the existing convention in this file, that is, fields are
prefixed with the register name. Also, please use small letters for hex
digits as used in the file elsewhere.
> +
> #define SATA_CONFIGURATION_0 0x180
> -#define SATA_CONFIGURATION_EN_FPCI BIT(0)
> +#define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
> +#define SATA_CONFIGURATION_CLK_OVERRIDE BIT(31)
> +
> +#define SATA_INTR_MASK_0 0x188
> +#define IP_INT_MASK BIT(16)
>
> #define SCFG_OFFSET 0x1000
>
> -#define T_SATA0_CFG_1 0x04
> -#define T_SATA0_CFG_1_IO_SPACE BIT(0)
> -#define T_SATA0_CFG_1_MEMORY_SPACE BIT(1)
> -#define T_SATA0_CFG_1_BUS_MASTER BIT(2)
> -#define T_SATA0_CFG_1_SERR BIT(8)
> +#define T_SATA_CFG_1 0x4
> +#define T_SATA_CFG_1_IO_SPACE BIT(0)
> +#define T_SATA_CFG_1_MEMORY_SPACE BIT(1)
> +#define T_SATA_CFG_1_BUS_MASTER BIT(2)
> +#define T_SATA_CFG_1_SERR BIT(8)
Try not to rename and move fields unnecessarily. It makes it very
difficult to see where things have actually changed and makes the patch
unnecessarily long.
> +
> +#define T_SATA_CFG_9 0x24
> +#define T_SATA_CFG_9_BASE_ADDRESS 0x40020000
> +
> +#define T_SATA0_CFG_35 0x94
> +#define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7FF << 2)
> +#define T_SATA0_CFG_35_IDP_INDEX (0x2A << 2)
>
> -#define T_SATA0_CFG_9 0x24
> -#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13
> +#define T_SATA0_AHCI_IDP1 0x98
> +#define T_SATA0_AHCI_IDP1_DATA (0x400040)
>
> -#define SATA_FPCI_BAR5 0x94
> -#define SATA_FPCI_BAR5_START_SHIFT 4
> +#define T_SATA0_CFG_PHY_1 0x12C
> +#define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23)
> +#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22)
>
> -#define SATA_INTR_MASK 0x188
> -#define SATA_INTR_MASK_IP_INT_MASK BIT(16)
> +#define T_SATA0_NVOOB 0x114
> +#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
> +#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
> +#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
> +#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
> +#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
> +#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
> +
> +#define T_SATA_CFG_PHY_0 0x120
> +#define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11)
> +#define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24)
> +
> +#define FUSE_SATA_CALIB 0x124
> +#define FUSE_SATA_CALIB_MASK 0x3
> +
> +#define T_SATA0_CFG2NVOOB_2 0x134
> +#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff << 18)
> +#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
>
> #define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
> +#define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13)
> +#define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14)
> +#define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26)
> +#define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17)
> +#define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30)
>
> -#define T_SATA0_BKDOOR_CC 0x4a4
> +#define T_SATA_BKDOOR_CC 0x4A4
> +#define T_SATA_BKDOOR_CC_CLASS_CODE_MASK (0xFFFF << 16)
> +#define T_SATA_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
> +#define T_SATA_BKDOOR_CC_PROG_IF_MASK (0xFF << 8)
> +#define T_SATA_BKDOOR_CC_PROG_IF (0x01 << 8)
>
> -#define T_SATA0_CFG_SATA 0x54c
> -#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
> +#define T_SATA_CFG_SATA 0x54C
> +#define T_SATA_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
>
> #define T_SATA0_CFG_MISC 0x550
>
> @@ -82,8 +124,27 @@
> #define T_SATA0_CHX_PHY_CTRL11 0x6d0
> #define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
>
> -#define FUSE_SATA_CALIB 0x124
> -#define FUSE_SATA_CALIB_MASK 0x3
> +/* Electrical settings for better link stability */
> +#define T_SATA0_CHX_PHY_CTRL17_0 0x6e8
> +#define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000
> +#define T_SATA0_CHX_PHY_CTRL18_0 0x6ec
> +#define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000
> +#define T_SATA0_CHX_PHY_CTRL20_0 0x6f4
> +#define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1
> +#define T_SATA0_CHX_PHY_CTRL21_0 0x6f8
> +#define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1
> +
> +/* AUX Registers */
> +#define SATA_AUX_MISC_CNTL_1_0 0x8
> +#define DEVSLP_OVERRIDE BIT(17)
> +#define SDS_SUPPORT BIT(13)
> +#define DESO_SUPPORT BIT(15)
> +
> +#define SATA_AUX_RX_STAT_INT_0 0xc
> +#define SATA_DEVSLP BIT(7)
> +
> +#define SATA_AUX_SPARE_CFG0_0 0x18
> +#define MDAT_TIMER_AFTER_PG_VALID BIT(14)
>
> struct sata_pad_calibration {
> u8 gen1_tx_amp;
> @@ -99,15 +160,135 @@ static const struct sata_pad_calibration tegra124_pad_calibration[] = {
> {0x14, 0x0e, 0x1a, 0x0e},
> };
>
> +struct tegra_ahci_ops {
> + int (*init)(struct ahci_host_priv *);
> +};
> +
> +struct tegra_ahci_soc {
> + const char *const *supply_names;
> + unsigned int num_supplies;
> + struct tegra_ahci_ops ops;
> +};
> +
> struct tegra_ahci_priv {
> - struct platform_device *pdev;
> - void __iomem *sata_regs;
> - struct reset_control *sata_rst;
> - struct reset_control *sata_oob_rst;
> - struct reset_control *sata_cold_rst;
> + struct platform_device *pdev;
> + void __iomem *sata_regs;
> + void __iomem *sata_aux_regs;
> + struct reset_control *sata_rst;
> + struct reset_control *sata_oob_rst;
> + struct reset_control *sata_cold_rst;
> /* Needs special handling, cannot use ahci_platform */
> - struct clk *sata_clk;
> - struct regulator_bulk_data supplies[5];
> + struct clk *sata_clk;
> + struct regulator_bulk_data *supplies;
> + struct tegra_ahci_soc *soc_data;
> +};
I don't particularly care whether the field names are aligned or not,
but I remember the ata maintainers wanting them to be. Anyway, changing
the style makes the patch larger and the actual functionality changes
harder to review.
> +
> +static const char *const tegra124_supply_names[] = {
> + "avdd", "hvdd", "vddio", "target-5v", "target-12v"
> +};
> +
> +static inline void tegra_ahci_sata_update(struct tegra_ahci_priv *tegra,
> + u32 val, u32 mask, u32 offset)
> +{
> + u32 uval;
> +
> + uval = readl(tegra->sata_regs + offset);
> + uval = (uval & ~mask) | (val & mask);
> + writel(uval, tegra->sata_regs + offset);
> +}
I'm not very fond of these _update functions. I think it is clearer to
just write it out at the callsite, especially since this is used only
four times.
> +
> +static inline void tegra_ahci_scfg_writel(struct tegra_ahci_priv *tegra,
> + u32 val, u32 offset)
> +{
> + writel(val, tegra->sata_regs + SCFG_OFFSET + offset);
> +}
> +
> +static inline void tegra_ahci_scfg_update(struct tegra_ahci_priv *tegra,
> + u32 val, u32 mask, u32 offset)
> +{
> + u32 uval;
> +
> + uval = readl(tegra->sata_regs + SCFG_OFFSET + offset);
> + uval = (uval & ~mask) | (val & mask);
> + writel(uval, tegra->sata_regs + SCFG_OFFSET + offset);
> +}
> +
> +static inline u32 tegra_ahci_aux_readl(struct tegra_ahci_priv *tegra,
> + u32 offset)
> +{
> + return readl(tegra->sata_aux_regs + offset);
> +}
This is never called.
> +
> +static inline void tegra_ahci_aux_update(struct tegra_ahci_priv *tegra, u32 val,
> + u32 mask, u32 offset)
> +{
> + u32 uval;
> +
> + uval = readl(tegra->sata_aux_regs + offset);
> + uval = (uval & ~mask) | (val & mask);
> + writel(uval, tegra->sata_aux_regs + offset);
> +}
This is only called once.
> +
> +static int tegra124_ahci_init(struct ahci_host_priv *hpriv)
> +{
> + struct tegra_ahci_priv *tegra = hpriv->plat_data;
> + struct sata_pad_calibration calib;
> + int ret;
> + u32 val;
> + u32 mask;
> +
> + /* Pad calibration */
> + ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
> + if (ret)
> + return ret;
> +
> + calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
> +
> + tegra_ahci_scfg_writel(tegra, BIT(0), T_SATA0_INDEX);
> +
> + mask = T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK |
> + T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
> + val = (calib.gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT) |
> + (calib.gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT);
> + tegra_ahci_scfg_update(tegra, val, mask, T_SATA0_CHX_PHY_CTRL1_GEN1);
> +
> + mask = T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK |
> + T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
> + val = (calib.gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT) |
> + (calib.gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT);
> + tegra_ahci_scfg_update(tegra, val, mask, T_SATA0_CHX_PHY_CTRL1_GEN2);
> +
> + tegra_ahci_scfg_writel(tegra,
> + T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
> + T_SATA0_CHX_PHY_CTRL11);
> + tegra_ahci_scfg_writel(tegra,
> + T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
> + T_SATA0_CHX_PHY_CTRL2);
> +
> + tegra_ahci_scfg_writel(tegra, 0, T_SATA0_INDEX);
> +
> + return 0;
> +}
> +
> +static const struct tegra_ahci_soc tegra124_ahci_soc_data = {
> + .supply_names = tegra124_supply_names,
> + .num_supplies = ARRAY_SIZE(tegra124_supply_names),
> + .ops = {
> + .init = tegra124_ahci_init,
> + },
> +};
> +
> +static const char *const tegra210_supply_names[] = {
> + "dvdd-sata-pll",
> + "hvdd-sata",
> + "l0-hvddio-sata",
> + "l0-dvddio-sata",
> + "hvdd-pex-pll-e"
> +};
Perhaps the "-sata-" should be removed from these - I believe the supply
name here should refer to the usage of the supplied power within the IP
block. The IP block here is SATA so it is clear that it is used for
something SATA related. If someone is better informed, please comment.
It also looks like this doesn't include the 5V and 12V supplies which
had to be enabled on the Jetson TK1 to enable power output through the
Molex connector - do you know if the Jetson TX1 no longer needs similar
to enable the SATA power connector?
> +
> +static const struct tegra_ahci_soc tegra210_ahci_soc_data = {
> + .supply_names = tegra210_supply_names,
> + .num_supplies = ARRAY_SIZE(tegra210_supply_names),
> };
>
> static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
> @@ -115,7 +296,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
> struct tegra_ahci_priv *tegra = hpriv->plat_data;
> int ret;
>
> - ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
> + ret = regulator_bulk_enable(tegra->soc_data->num_supplies,
> tegra->supplies);
> if (ret)
> return ret;
> @@ -144,8 +325,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
> tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
>
> disable_regulators:
> - regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
> -
> + regulator_bulk_disable(tegra->soc_data->num_supplies, tegra->supplies);
> return ret;
> }
>
> @@ -162,101 +342,124 @@ static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
> clk_disable_unprepare(tegra->sata_clk);
> tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
>
> - regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
> + regulator_bulk_disable(tegra->soc_data->num_supplies, tegra->supplies);
> }
>
> static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
> {
> struct tegra_ahci_priv *tegra = hpriv->plat_data;
> int ret;
> - unsigned int val;
> - struct sata_pad_calibration calib;
> + u32 val;
> + u32 mask;
>
> ret = tegra_ahci_power_on(hpriv);
> - if (ret) {
> - dev_err(&tegra->pdev->dev,
> - "failed to power on AHCI controller: %d\n", ret);
> - return ret;
> - }
> -
> - val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
> - val |= SATA_CONFIGURATION_EN_FPCI;
> - writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
> -
> - /* Pad calibration */
> -
> - ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
> - if (ret) {
> - dev_err(&tegra->pdev->dev,
> - "failed to read calibration fuse: %d\n", ret);
> + if (ret)
> return ret;
> - }
> -
> - calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
> -
> - writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
> -
> - val = readl(tegra->sata_regs +
> - SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
> - val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
> - val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
> - val |= calib.gen1_tx_amp <<
> - T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
> - val |= calib.gen1_tx_peak <<
> - T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
> - writel(val, tegra->sata_regs + SCFG_OFFSET +
> - T_SATA0_CHX_PHY_CTRL1_GEN1);
> -
> - val = readl(tegra->sata_regs +
> - SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
> - val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
> - val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
> - val |= calib.gen2_tx_amp <<
> - T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
> - val |= calib.gen2_tx_peak <<
> - T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
> - writel(val, tegra->sata_regs + SCFG_OFFSET +
> - T_SATA0_CHX_PHY_CTRL1_GEN2);
> -
> - writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
> - tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
> - writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
> - tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
> -
> - writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
> -
> - /* Program controller device ID */
>
> - val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
> - val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
> - writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
> -
> - writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
> -
> - val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
> - val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
> - writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
> -
> - /* Enable IO & memory access, bus master mode */
> -
> - val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
> - val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
> - T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR;
> - writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
> -
> - /* Program SATA MMIO */
> -
> - writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
> - tegra->sata_regs + SATA_FPCI_BAR5);
> -
> - writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
> - tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
> -
> - /* Unmask SATA interrupts */
> -
> - val = readl(tegra->sata_regs + SATA_INTR_MASK);
> - val |= SATA_INTR_MASK_IP_INT_MASK;
> - writel(val, tegra->sata_regs + SATA_INTR_MASK);
> + /*
> + * Program the following SATA IPFS registers
> + * to allow SW accesses to SATA's MMIO Register
> + */
> + mask = FPCI_BAR5_START_MASK | FPCI_BAR5_ACCESS_TYPE;
> + val = FPCI_BAR5_START | FPCI_BAR5_ACCESS_TYPE;
> + tegra_ahci_sata_update(tegra, val, mask, SATA_FPCI_BAR5_0);
> +
> + /* Program the following SATA IPFS register to enable the SATA */
> + val = SATA_CONFIGURATION_0_EN_FPCI;
> + tegra_ahci_sata_update(tegra, val, val, SATA_CONFIGURATION_0);
> +
> + /* Electrical settings for better link stability */
> + tegra_ahci_scfg_writel(tegra,
> + T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1,
> + T_SATA0_CHX_PHY_CTRL17_0);
> + tegra_ahci_scfg_writel(tegra,
> + T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2,
> + T_SATA0_CHX_PHY_CTRL18_0);
> + tegra_ahci_scfg_writel(tegra,
> + T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1,
> + T_SATA0_CHX_PHY_CTRL20_0);
> + tegra_ahci_scfg_writel(tegra,
> + T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2,
> + T_SATA0_CHX_PHY_CTRL21_0);
> +
> + /* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */
> +
> + mask = T_SATA_CFG_PHY_0_MASK_SQUELCH |
> + T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
> + val = T_SATA_CFG_PHY_0_MASK_SQUELCH;
> + val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
> + tegra_ahci_scfg_update(tegra, val, mask, T_SATA_CFG_PHY_0);
> +
> + mask = (T_SATA0_NVOOB_COMMA_CNT_MASK |
> + T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
> + T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
> + val = (T_SATA0_NVOOB_COMMA_CNT |
> + T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
> + T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
> + tegra_ahci_scfg_update(tegra, val, mask, T_SATA0_NVOOB);
> +
> + /*
> + * Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to 58.8ns
> + */
> + mask = T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
> + val = T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
> + tegra_ahci_scfg_update(tegra, val, mask, T_SATA0_CFG2NVOOB_2);
> +
> + if (tegra->soc_data->ops.init)
> + tegra->soc_data->ops.init(hpriv);
> +
> + /*
> + * Program the following SATA configuration registers
> + * to initialize SATA
> + */
> + val = (T_SATA_CFG_1_IO_SPACE | T_SATA_CFG_1_MEMORY_SPACE |
> + T_SATA_CFG_1_BUS_MASTER | T_SATA_CFG_1_SERR);
> + tegra_ahci_scfg_update(tegra, val, val, T_SATA_CFG_1);
> + tegra_ahci_scfg_writel(tegra, T_SATA_CFG_9_BASE_ADDRESS, T_SATA_CFG_9);
> +
> + /* Program Class Code and Programming interface for SATA */
> + val = T_SATA_CFG_SATA_BACKDOOR_PROG_IF_EN;
> + tegra_ahci_scfg_update(tegra, val, val, T_SATA_CFG_SATA);
> +
> + mask = T_SATA_BKDOOR_CC_CLASS_CODE_MASK | T_SATA_BKDOOR_CC_PROG_IF_MASK;
> + val = T_SATA_BKDOOR_CC_CLASS_CODE | T_SATA_BKDOOR_CC_PROG_IF;
> + tegra_ahci_scfg_update(tegra, val, mask, T_SATA_BKDOOR_CC);
> +
> + tegra_ahci_scfg_update(tegra, 0, T_SATA_CFG_SATA_BACKDOOR_PROG_IF_EN,
> + T_SATA_CFG_SATA);
> +
> + /* Enabling LPM capabilities through Backdoor Programming */
> + val = (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
> + T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
> + T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
> + T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM);
> + tegra_ahci_scfg_update(tegra, val, val, T_SATA0_AHCI_HBA_CAP_BKDR);
> +
> + /* SATA Second Level Clock Gating configuration
> + * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane
> + * IDDQ Signals
> + */
> + mask = T_SATA0_CFG_35_IDP_INDEX_MASK;
> + val = T_SATA0_CFG_35_IDP_INDEX;
> + tegra_ahci_scfg_update(tegra, val, mask, T_SATA0_CFG_35);
> + tegra_ahci_scfg_writel(tegra, T_SATA0_AHCI_IDP1_DATA,
> + T_SATA0_AHCI_IDP1);
> + val = (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
> + T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN);
> + tegra_ahci_scfg_update(tegra, val, val, T_SATA0_CFG_PHY_1);
> +
> + /*
> + * Indicate Sata only has the capability to enter DevSleep
> + * from slumber link.
> + */
> + tegra_ahci_aux_update(tegra, DESO_SUPPORT, DESO_SUPPORT,
> + SATA_AUX_MISC_CNTL_1_0);
> + /* Enabling IPFS Clock Gating */
> + tegra_ahci_sata_update(tegra, 0, SATA_CONFIGURATION_CLK_OVERRIDE,
> + SATA_CONFIGURATION_0);
> +
> + tegra_ahci_sata_update(tegra, IP_INT_MASK, IP_INT_MASK,
> + SATA_INTR_MASK_0);
>
> return 0;
> }
> @@ -274,19 +477,24 @@ static void tegra_ahci_host_stop(struct ata_host *host)
> }
>
> static struct ata_port_operations ahci_tegra_port_ops = {
> - .inherits = &ahci_ops,
> - .host_stop = tegra_ahci_host_stop,
> + .inherits = &ahci_ops,
> + .host_stop = tegra_ahci_host_stop,
> };
>
> static const struct ata_port_info ahci_tegra_port_info = {
> - .flags = AHCI_FLAG_COMMON,
> - .pio_mask = ATA_PIO4,
> - .udma_mask = ATA_UDMA6,
> - .port_ops = &ahci_tegra_port_ops,
> + .flags = AHCI_FLAG_COMMON,
> + .pio_mask = ATA_PIO4,
> + .udma_mask = ATA_UDMA6,
> + .port_ops = &ahci_tegra_port_ops,
> };
Please keep the original style as to keep the patch as small as possible.
>
> static const struct of_device_id tegra_ahci_of_match[] = {
> - { .compatible = "nvidia,tegra124-ahci" },
> + {
> + .compatible = "nvidia,tegra124-ahci",
> + .data = &tegra124_ahci_soc_data},
> + {
> + .compatible = "nvidia,tegra210-ahci",
> + .data = &tegra210_ahci_soc_data},
Please write these like
{
.compatible = "nvidia,tegra124-ahci",
.data = &tegra124_ahci_soc_data,
},
> {}
> };
> MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
> @@ -301,6 +509,7 @@ static int tegra_ahci_probe(struct platform_device *pdev)
> struct tegra_ahci_priv *tegra;
> struct resource *res;
> int ret;
> + unsigned int i;
>
> hpriv = ahci_platform_get_resources(pdev);
> if (IS_ERR(hpriv))
> @@ -311,13 +520,18 @@ static int tegra_ahci_probe(struct platform_device *pdev)
> return -ENOMEM;
>
> hpriv->plat_data = tegra;
> -
> tegra->pdev = pdev;
> + tegra->soc_data =
> + (struct tegra_ahci_soc *)of_device_get_match_data(&pdev->dev);
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(tegra->sata_regs))
> return PTR_ERR(tegra->sata_regs);
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> + tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(tegra->sata_aux_regs))
> + return PTR_ERR(tegra->sata_aux_regs);
Please add this register range also to the device tree binding
documentation. Also, please provide a patch to enable the SATA
controller on a Tegra210 board - preferably the Jetson TX1 (or internal
variant) so that it is easy to test.
>
> tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
> if (IS_ERR(tegra->sata_rst)) {
> @@ -343,13 +557,17 @@ static int tegra_ahci_probe(struct platform_device *pdev)
> return PTR_ERR(tegra->sata_clk);
> }
>
> - tegra->supplies[0].supply = "avdd";
> - tegra->supplies[1].supply = "hvdd";
> - tegra->supplies[2].supply = "vddio";
> - tegra->supplies[3].supply = "target-5v";
> - tegra->supplies[4].supply = "target-12v";
> + tegra->supplies = devm_kcalloc(&pdev->dev,
> + tegra->soc_data->num_supplies,
> + sizeof(*tegra->supplies), GFP_KERNEL);
> + if (!tegra->supplies)
> + return -ENOMEM;
> +
> + for (i = 0; i < tegra->soc_data->num_supplies; i++)
> + tegra->supplies[i].supply = tegra->soc_data->supply_names[i];
>
> - ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies),
> + ret = devm_regulator_bulk_get(&pdev->dev,
> + tegra->soc_data->num_supplies,
> tegra->supplies);
> if (ret) {
> dev_err(&pdev->dev, "Failed to get regulators\n");
> @@ -377,13 +595,13 @@ static struct platform_driver tegra_ahci_driver = {
> .probe = tegra_ahci_probe,
> .remove = ata_platform_remove_one,
> .driver = {
> - .name = DRV_NAME,
> - .of_match_table = tegra_ahci_of_match,
> - },
> + .name = DRV_NAME,
> + .of_match_table = tegra_ahci_of_match,
> + },
Please keep the style unchanged here as well.
> /* LP0 suspend support not implemented */
> };
> module_platform_driver(tegra_ahci_driver);
>
> MODULE_AUTHOR("Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>");
> -MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
> +MODULE_DESCRIPTION("Tegra AHCI SATA driver");
Awesome!
> MODULE_LICENSE("GPL v2");
>
>
Thanks,
Mikko
^ permalink raw reply
* Re: [v2,2/3] ata: ahci_tegra: Add support to disable features
From: Mikko Perttunen @ 2016-11-28 12:38 UTC (permalink / raw)
To: PREETHAM RAMACHANDRA, tj-DgEjT+Ai2ygdnm+yROfE0A,
swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
preetham260-Re5JQEeQqe8AvxtiuMwx3w
Cc: ldewangan-DDmLM1+adcrQT0dZR+AlfA,
linux-ide-u79uwXL29TY76Z2rM5mHXA,
vbyravarasu-DDmLM1+adcrQT0dZR+AlfA,
pkunapuli-DDmLM1+adcrQT0dZR+AlfA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479973418-21351-3-git-send-email-pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 24.11.2016 09:43, PREETHAM RAMACHANDRA wrote:
> From: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Add support to disable DIPM, HIPM, DevSlp, partial, slumber and NCQ
> features from DT. By default these features are enabled.
>
Why are these features disabled? Are they broken on all Tegra210 chips,
broken on specific boards or do they require some support from the
driver that is not there?
Most likely we should hardcode the disabled features into the driver
instead of reading them from the device tree.
> Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> v2:
> * This change was created by seperating
> "ata: ahci_tegra: add support for tegra210" from v1
>
> drivers/ata/ahci_tegra.c | 107 ++++++++++++++++++++++++++++++++++++-----------
> 1 file changed, 82 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
> index d12e2a9..443c3e8 100644
> --- a/drivers/ata/ahci_tegra.c
> +++ b/drivers/ata/ahci_tegra.c
> @@ -329,7 +329,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
> return ret;
> }
>
> -static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
> +static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
> {
> struct tegra_ahci_priv *tegra = hpriv->plat_data;
>
> @@ -345,6 +345,85 @@ static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
> regulator_bulk_disable(tegra->soc_data->num_supplies, tegra->supplies);
> }
>
> +static void tegra_ahci_host_stop(struct ata_host *host)
> +{
> + struct ahci_host_priv *hpriv = host->private_data;
> +
> + tegra_ahci_controller_deinit(hpriv);
> +}
> +
> +static struct ata_port_operations ahci_tegra_port_ops = {
> + .inherits = &ahci_ops,
> + .host_stop = tegra_ahci_host_stop,
> +};
> +
> +static struct ata_port_info ahci_tegra_port_info = {
> + .flags = AHCI_FLAG_COMMON,
> + .pio_mask = ATA_PIO4,
> + .udma_mask = ATA_UDMA6,
> + .port_ops = &ahci_tegra_port_ops,
> +};
> +
> +static void tegra_ahci_disable_devslp(struct tegra_ahci_priv *tegra)
> +{
> + tegra_ahci_aux_update(tegra, 0, SDS_SUPPORT, SATA_AUX_MISC_CNTL_1_0);
> +}
> +
> +static void tegra_ahci_disable_hipm(struct tegra_ahci_priv *tegra)
> +{
> + tegra_ahci_scfg_update(tegra, 0, T_SATA0_AHCI_HBA_CAP_BKDR_SALP,
> + T_SATA0_AHCI_HBA_CAP_BKDR);
> +}
> +
> +static void tegra_ahci_disable_partial(struct tegra_ahci_priv *tegra)
> +{
> + tegra_ahci_scfg_update(tegra, 0,
> + T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP,
> + T_SATA0_AHCI_HBA_CAP_BKDR);
> +}
> +
> +static void tegra_ahci_disable_slumber(struct tegra_ahci_priv *tegra)
> +{
> + tegra_ahci_scfg_update(tegra, 0,
> + T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP,
> + T_SATA0_AHCI_HBA_CAP_BKDR);
> +}
> +
> +static void tegra_ahci_disable_ncq(struct tegra_ahci_priv *tegra)
> +{
> + tegra_ahci_scfg_update(tegra, 0, T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ,
> + T_SATA0_AHCI_HBA_CAP_BKDR);
> +}
These probably don't need their own functions.
> +
> +static void tegra_ahci_disable_features(struct ahci_host_priv *hpriv)
> +{
> + struct tegra_ahci_priv *tegra = hpriv->plat_data;
> + struct platform_device *pdev = tegra->pdev;
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct property *prop;
> + const char *feature;
> +
> + if (of_property_count_strings(np, "nvidia,disable-features") <= 0)
> + return;
> +
> + of_property_for_each_string(np, "nvidia,disable-features", prop,
> + feature) {
> + if (!strcmp(feature, "devslp"))
> + tegra_ahci_disable_devslp(tegra);
> + else if (!strcmp(feature, "hipm"))
> + tegra_ahci_disable_hipm(tegra);
> + else if (!strcmp(feature, "ncq"))
> + tegra_ahci_disable_ncq(tegra);
> + else if (!strcmp(feature, "dipm"))
> + ahci_tegra_port_info.flags |= ATA_FLAG_NO_DIPM;
> + else if (!strcmp(feature, "partial"))
> + tegra_ahci_disable_partial(tegra);
> + else if (!strcmp(feature, "slumber"))
> + tegra_ahci_disable_slumber(tegra);
> + }
> +}
> +
> static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
> {
> struct tegra_ahci_priv *tegra = hpriv->plat_data;
> @@ -458,36 +537,14 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
> tegra_ahci_sata_update(tegra, 0, SATA_CONFIGURATION_CLK_OVERRIDE,
> SATA_CONFIGURATION_0);
>
> + tegra_ahci_disable_features(hpriv);
> +
> tegra_ahci_sata_update(tegra, IP_INT_MASK, IP_INT_MASK,
> SATA_INTR_MASK_0);
>
> return 0;
> }
>
> -static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
> -{
> - tegra_ahci_power_off(hpriv);
> -}
> -
> -static void tegra_ahci_host_stop(struct ata_host *host)
> -{
> - struct ahci_host_priv *hpriv = host->private_data;
> -
> - tegra_ahci_controller_deinit(hpriv);
> -}
> -
> -static struct ata_port_operations ahci_tegra_port_ops = {
> - .inherits = &ahci_ops,
> - .host_stop = tegra_ahci_host_stop,
> -};
> -
> -static const struct ata_port_info ahci_tegra_port_info = {
> - .flags = AHCI_FLAG_COMMON,
> - .pio_mask = ATA_PIO4,
> - .udma_mask = ATA_UDMA6,
> - .port_ops = &ahci_tegra_port_ops,
> -};
> -
> static const struct of_device_id tegra_ahci_of_match[] = {
> {
> .compatible = "nvidia,tegra124-ahci",
>
>
Thanks,
Mikko.
^ permalink raw reply
* Re: [v2,3/3] dt-bindings: ata: ahci_tegra: Add tegra210 AHCI
From: Mikko Perttunen @ 2016-11-28 13:05 UTC (permalink / raw)
To: PREETHAM RAMACHANDRA, tj-DgEjT+Ai2ygdnm+yROfE0A,
swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
preetham260-Re5JQEeQqe8AvxtiuMwx3w
Cc: ldewangan-DDmLM1+adcrQT0dZR+AlfA,
linux-ide-u79uwXL29TY76Z2rM5mHXA,
vbyravarasu-DDmLM1+adcrQT0dZR+AlfA,
pkunapuli-DDmLM1+adcrQT0dZR+AlfA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479973418-21351-4-git-send-email-pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 24.11.2016 09:43, PREETHAM RAMACHANDRA wrote:
> From: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> .../bindings/ata/nvidia,tegra124-ahci.txt | 48 ++++++++++++++++------
> 1 file changed, 36 insertions(+), 12 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> index 66c83c3..446214f 100644
> --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
> @@ -1,9 +1,9 @@
> -Tegra124 SoC SATA AHCI controller
> +Tegra SoC SATA AHCI controller
>
> Required properties :
> -- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise,
> - must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
> - is tegra132.
> +- compatible : Must be one of:
> + - Tegra124 : "nvidia,tegra124-ahci"
> + - Tegra210 : "nvidia,tegra210-ahci"
> - reg : Should contain 2 entries:
> - AHCI register set (SATA BAR5)
> - SATA register set
I think you added a new set in the first patch, AUX; you should add it
here as well.
> @@ -13,8 +13,6 @@ Required properties :
> - clock-names : Must include the following entries:
> - sata
> - sata-oob
> - - cml1
> - - pll_e
> - resets : Must contain an entry for each entry in reset-names.
> See ../reset/reset.txt for details.
> - reset-names : Must include the following entries:
> @@ -24,9 +22,35 @@ Required properties :
> - phys : Must contain an entry for each entry in phy-names.
> See ../phy/phy-bindings.txt for details.
> - phy-names : Must include the following entries:
> - - sata-phy : XUSB PADCTL SATA PHY
> -- hvdd-supply : Defines the SATA HVDD regulator
> -- vddio-supply : Defines the SATA VDDIO regulator
> -- avdd-supply : Defines the SATA AVDD regulator
> -- target-5v-supply : Defines the SATA 5V power regulator
> -- target-12v-supply : Defines the SATA 12V power regulator
> + - For T124:
> + - sata-phy : XUSB PADCTL SATA PHY
> + - For T210:
> + - sata-0
> +- For T124:
> + - hvdd-supply : Defines the SATA HVDD regulator
> + - vddio-supply : Defines the SATA VDDIO regulator
> + - avdd-supply : Defines the SATA AVDD regulator
> + - target-5v-supply : Defines the SATA 5V power regulator
> +- For T210:
> + - l0-hvddio-sata-supply : Defines the SATA HVDDIO regulator
> + - l0-dvddio-sata-supply : Defines the SATA DVDDIO regulator
> + - hvdd-pex-pll-e-supply : Defines the PEX PLL_E regulator
> + - dvdd-sata-pll-supply : Defines the SATA PLL regulator
> + - hvdd-sata-supply : Defines the SATA HVDD regulator
> +- nvidia,disable-features : Must include the following entries:
> + - devslp
> + - dipm
> +
> +Optional properties:
> +- clock-names :
> + - cml1 :
> + cml1 clock is required by phy so it is optional to define
> + here as phy driver will be enabling this clock.
The current phy driver does not seem to be enabling this clock. For
PCIE, the PCIE driver itself enables cml0. It might be true that the phy
driver should be enabling this. Thierry?
> + - pll_e :
> + pll_e is the parent of cml1 clock so it is optional to define
> + here as phy driver will be enabling this clock.
> +- nvidia,disable-features :
> + - hipm
> + - ncq
> + - partial
> + - slumber
>
>
Thanks,
Mikko.
^ permalink raw reply
* Re: [v2,3/3] dt-bindings: ata: ahci_tegra: Add tegra210 AHCI
From: Jon Hunter @ 2016-11-28 13:52 UTC (permalink / raw)
To: Mikko Perttunen, PREETHAM RAMACHANDRA, tj-DgEjT+Ai2ygdnm+yROfE0A,
swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
preetham260-Re5JQEeQqe8AvxtiuMwx3w
Cc: ldewangan-DDmLM1+adcrQT0dZR+AlfA,
linux-ide-u79uwXL29TY76Z2rM5mHXA,
vbyravarasu-DDmLM1+adcrQT0dZR+AlfA,
pkunapuli-DDmLM1+adcrQT0dZR+AlfA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <bdc5d888-0d9f-fed2-8a74-c42ae7e6b810-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 28/11/16 13:05, Mikko Perttunen wrote:
> On 24.11.2016 09:43, PREETHAM RAMACHANDRA wrote:
>> From: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
I did not receive the original (please CC linux-tegra as well if you did
not originally), but there should be some description here.
>> Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> .../bindings/ata/nvidia,tegra124-ahci.txt | 48
>> ++++++++++++++++------
>> 1 file changed, 36 insertions(+), 12 deletions(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> index 66c83c3..446214f 100644
>> --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> @@ -1,9 +1,9 @@
>> -Tegra124 SoC SATA AHCI controller
>> +Tegra SoC SATA AHCI controller
>>
>> Required properties :
>> -- compatible : For Tegra124, must contain "nvidia,tegra124-ahci".
>> Otherwise,
>> - must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where
>> <chip>
>> - is tegra132.
>> +- compatible : Must be one of:
>> + - Tegra124 : "nvidia,tegra124-ahci"
>> + - Tegra210 : "nvidia,tegra210-ahci"
>> - reg : Should contain 2 entries:
>> - AHCI register set (SATA BAR5)
>> - SATA register set
>
> I think you added a new set in the first patch, AUX; you should add it
> here as well.
>
>> @@ -13,8 +13,6 @@ Required properties :
>> - clock-names : Must include the following entries:
>> - sata
>> - sata-oob
>> - - cml1
>> - - pll_e
>> - resets : Must contain an entry for each entry in reset-names.
>> See ../reset/reset.txt for details.
>> - reset-names : Must include the following entries:
>> @@ -24,9 +22,35 @@ Required properties :
>> - phys : Must contain an entry for each entry in phy-names.
>> See ../phy/phy-bindings.txt for details.
>> - phy-names : Must include the following entries:
>> - - sata-phy : XUSB PADCTL SATA PHY
>> -- hvdd-supply : Defines the SATA HVDD regulator
>> -- vddio-supply : Defines the SATA VDDIO regulator
>> -- avdd-supply : Defines the SATA AVDD regulator
>> -- target-5v-supply : Defines the SATA 5V power regulator
>> -- target-12v-supply : Defines the SATA 12V power regulator
>> + - For T124:
>> + - sata-phy : XUSB PADCTL SATA PHY
>> + - For T210:
>> + - sata-0
>> +- For T124:
>> + - hvdd-supply : Defines the SATA HVDD regulator
>> + - vddio-supply : Defines the SATA VDDIO regulator
>> + - avdd-supply : Defines the SATA AVDD regulator
>> + - target-5v-supply : Defines the SATA 5V power regulator
>> +- For T210:
>> + - l0-hvddio-sata-supply : Defines the SATA HVDDIO regulator
>> + - l0-dvddio-sata-supply : Defines the SATA DVDDIO regulator
>> + - hvdd-pex-pll-e-supply : Defines the PEX PLL_E regulator
>> + - dvdd-sata-pll-supply : Defines the SATA PLL regulator
>> + - hvdd-sata-supply : Defines the SATA HVDD regulator
>> +- nvidia,disable-features : Must include the following entries:
>> + - devslp
>> + - dipm
My understanding is that the AHCI controller requires the SATA powergate
to be enabled. Now we have support for powergates via the genpd
framework we should add the 'power-domains' property for this device.
Do you know if there is any sequencing requirement with regard to
powering on the above rails and the powergate? If not we should check as
we should ensure that we have the proper sequencing.
Cheers
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH] ata: disable port while unloading ATA controller driver
From: Tejun Heo @ 2016-11-28 18:34 UTC (permalink / raw)
To: Vladimir Zapolskiy; +Cc: Bartlomiej Zolnierkiewicz, linux-ide
In-Reply-To: <20161127231856.11466-1-vz@mleia.com>
Hello, Vladimir.
On Mon, Nov 28, 2016 at 01:18:56AM +0200, Vladimir Zapolskiy wrote:
> While removing ATA controller driver ata_port_detach() sets
> ATA_PFLAG_UNLOADING flag and charges the error handler, however actual
> port disabling does not happen due to unset ATA_PFLAG_EH_PENDING flag.
>
> To take care about clean port removal and ATA_PFLAG_EH_PENDING flag
> setting it is sufficient to replace ata_port_schedule_eh() call with
> ata_port_freeze().
Hmm... this explanation doesn't really make sense to me.
ATA_PFLAG_EH_PENDING is set by at_eh_set_pending() which is the same
for both ata_port_schedule_eh() and ata_port_freeze(). There gotta me
something else going on here. Any chance you can track down why EH
isn't running?
Thanks.
--
tejun
^ permalink raw reply
* [GIT PULL] libata fixes for v4.9-rc7
From: Tejun Heo @ 2016-11-28 21:06 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linux-ide, linux-kernel
Hello, Linus.
The recent changes in ahci MSI handling need one more fix. Hopefully,
this restores parity with before. The other two are minor fixes with
both low impact and risk.
Thanks.
The following changes since commit 0ce57f8af1782fd12d3a81872a4ab97244989802:
ahci: fix the single MSI-X case in ahci_init_one (2016-10-25 11:43:07 -0400)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git for-4.9-fixes
for you to fetch changes up to 6929ef385e09c0065b87fda3e7b872a5070ac783:
ahci: always fall back to single-MSI mode (2016-11-21 11:06:57 -0500)
----------------------------------------------------------------
Christoph Hellwig (1):
ahci: always fall back to single-MSI mode
Hannes Reinecke (1):
libata-scsi: Fixup ata_gen_passthru_sense()
Wei Yongjun (1):
mvsas: fix error return code in mvs_task_prep()
drivers/ata/ahci.c | 7 -------
drivers/ata/libata-scsi.c | 2 +-
drivers/scsi/mvsas/mv_sas.c | 4 +++-
3 files changed, 4 insertions(+), 9 deletions(-)
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