* [PATCH v2 4/4] ARM: omap2plus_defconfig: enable ahci-dm816 module
From: Bartosz Golaszewski @ 2017-03-14 11:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Neil Armstrong, Michael Turquette,
Kevin Hilman, Patrick Titiano, Tony Lindgren, Paul Walmsley,
Sergei Shtylyov
Cc: linux-ide, devicetree, linux-kernel, linux-arm-kernel, linux-omap,
Bartosz Golaszewski
In-Reply-To: <1489490055-2318-1-git-send-email-bgolaszewski@baylibre.com>
This is now supported on the dm8168-evm board, so enable it in
the defconfig for omap2+.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
arch/arm/configs/omap2plus_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index f2462a6..3944aa9 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -141,6 +141,7 @@ CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_ATA=y
CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_DM816=m
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
--
2.9.3
^ permalink raw reply related
* [PATCH v2 3/4] ARM: dts: dm8168-evm: add SATA node
From: Bartosz Golaszewski @ 2017-03-14 11:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Neil Armstrong, Michael Turquette,
Kevin Hilman, Patrick Titiano, Tony Lindgren, Paul Walmsley,
Sergei Shtylyov
Cc: linux-ide-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-omap-u79uwXL29TY76Z2rM5mHXA, Bartosz Golaszewski
In-Reply-To: <1489490055-2318-1-git-send-email-bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Add the SATA controller node to the dm8168-evm device tree.
Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
arch/arm/boot/dts/dm8168-evm.dts | 4 ++++
arch/arm/boot/dts/dm816x.dtsi | 7 +++++++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index c6fabfc..1865976 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -179,3 +179,7 @@
pinctrl-0 = <&usb1_pins>;
mentor,multipoint = <0>;
};
+
+&sata {
+ clocks = <&sysclk5_ck>, <&sata_refclk>;
+};
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 276211e..59cbf95 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -293,6 +293,13 @@
phy-handle = <&phy1>;
};
+ sata: sata@4a140000 {
+ compatible = "ti,dm816-ahci";
+ reg = <0x4a140000 0x10000>;
+ interrupts = <16>;
+ ti,hwmods = "sata";
+ };
+
mcspi1: spi@48030000 {
compatible = "ti,omap4-mcspi";
reg = <0x48030000 0x1000>;
--
2.9.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v2 1/4] ARM: OMAP2+: dm81xx: Add clkdm and hwmod for SATA
From: Bartosz Golaszewski @ 2017-03-14 11:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Neil Armstrong, Michael Turquette,
Kevin Hilman, Patrick Titiano, Tony Lindgren, Paul Walmsley,
Sergei Shtylyov
Cc: linux-ide, devicetree, linux-kernel, linux-arm-kernel, linux-omap,
Bartosz Golaszewski
In-Reply-To: <1489490055-2318-1-git-send-email-bgolaszewski@baylibre.com>
From: Kevin Hilman <khilman@baylibre.com>
Add the SATA clockdomain (part of CM_DEFAULT) and a hwmod for the SATA
block on dm81xx.
Tested on DM8168 EVM.
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
[Bartosz: removed an unused define]
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
arch/arm/mach-omap2/clockdomains81xx_data.c | 10 +++++++++
arch/arm/mach-omap2/cm81xx.h | 1 +
arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 34 +++++++++++++++++++++++++++++
3 files changed, 45 insertions(+)
diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c
index 3b5fb05..65fbd13 100644
--- a/arch/arm/mach-omap2/clockdomains81xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
@@ -91,6 +91,14 @@ static struct clockdomain default_l3_slow_81xx_clkdm = {
.flags = CLKDM_CAN_SWSUP,
};
+static struct clockdomain default_sata_81xx_clkdm = {
+ .name = "default_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_MOD,
+ .clkdm_offs = TI816X_CM_DEFAULT_SATA_CLKDM,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
/* 816x only */
static struct clockdomain alwon_mpu_816x_clkdm = {
@@ -173,6 +181,7 @@ static struct clockdomain *clockdomains_ti814x[] __initdata = {
&mmu_81xx_clkdm,
&mmu_cfg_81xx_clkdm,
&default_l3_slow_81xx_clkdm,
+ &default_sata_81xx_clkdm,
NULL,
};
@@ -200,6 +209,7 @@ static struct clockdomain *clockdomains_ti816x[] __initdata = {
&default_ducati_816x_clkdm,
&default_pci_816x_clkdm,
&default_l3_slow_81xx_clkdm,
+ &default_sata_81xx_clkdm,
NULL,
};
diff --git a/arch/arm/mach-omap2/cm81xx.h b/arch/arm/mach-omap2/cm81xx.h
index 3a0ccf0..5d73a10 100644
--- a/arch/arm/mach-omap2/cm81xx.h
+++ b/arch/arm/mach-omap2/cm81xx.h
@@ -57,5 +57,6 @@
#define TI816X_CM_DEFAULT_PCI_CLKDM 0x0010
#define TI816X_CM_DEFAULT_L3_SLOW_CLKDM 0x0014
#define TI816X_CM_DEFAULT_DUCATI_CLKDM 0x0018
+#define TI816X_CM_DEFAULT_SATA_CLKDM 0x0060
#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index b82b77c..310afe4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -106,6 +106,7 @@
*/
#define DM81XX_CM_DEFAULT_OFFSET 0x500
#define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET)
+#define DM81XX_CM_DEFAULT_SATA_CLKCTRL (0x560 - DM81XX_CM_DEFAULT_OFFSET)
/* L3 Interconnect entries clocked at 125, 250 and 500MHz */
static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
@@ -973,6 +974,38 @@ static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
.user = OCP_USER_MPU,
};
+static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = {
+ .sysc_offs = 0x1100,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = SIDLE_FORCE,
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dm81xx_sata_hwmod_class = {
+ .name = "sata",
+ .sysc = &dm81xx_sata_sysc,
+};
+
+static struct omap_hwmod dm81xx_sata_hwmod = {
+ .name = "sata",
+ .clkdm_name = "default_sata_clkdm",
+ .flags = HWMOD_NO_IDLEST,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .class = &dm81xx_sata_hwmod_class,
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = {
+ .master = &dm81xx_l4_hs_hwmod,
+ .slave = &dm81xx_sata_hwmod,
+ .clk = "sysclk5_ck",
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x110,
@@ -1474,6 +1507,7 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
&dm81xx_l4_hs__emac0,
&dm81xx_emac0__mdio,
&dm816x_l4_hs__emac1,
+ &dm81xx_l4_hs__sata,
&dm81xx_alwon_l3_fast__tpcc,
&dm81xx_alwon_l3_fast__tptc0,
&dm81xx_alwon_l3_fast__tptc1,
--
2.9.3
^ permalink raw reply related
* [PATCH v2 0/4] ARM: dm8168-evm: add SATA support
From: Bartosz Golaszewski @ 2017-03-14 11:14 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Neil Armstrong, Michael Turquette,
Kevin Hilman, Patrick Titiano, Tony Lindgren, Paul Walmsley,
Sergei Shtylyov
Cc: linux-ide, devicetree, linux-kernel, linux-arm-kernel, linux-omap,
Bartosz Golaszewski
This series implements support for the on-board SATA controller
on the dm8168-evm board.
The first patch adds the clock domain and hwmod entries for the
SATA module.
The second patch models the external reference clock used by SATA.
The third adds the SATA node to the SoC's device tree.
The fourth enables the SATA driver by default in omap2plus_defconfig.
Tested together with the series implementing the driver for
ahci-dm816 on a DM8168-EVM board.
v1 -> v2:
PATCH 1/4:
- removed the unused define from cm81xx.h
PATCH 3/4:
- fixed the size of the mapped register region
Bartosz Golaszewski (3):
ARM: dts: dm8168-evm: add the external reference clock for SATA
ARM: dts: dm8168-evm: add SATA node
ARM: omap2plus_defconfig: enable ahci-dm816 module
Kevin Hilman (1):
ARM: OMAP2+: dm81xx: Add clkdm and hwmod for SATA
arch/arm/boot/dts/dm8168-evm.dts | 10 +++++++++
arch/arm/boot/dts/dm816x.dtsi | 7 ++++++
arch/arm/configs/omap2plus_defconfig | 1 +
arch/arm/mach-omap2/clockdomains81xx_data.c | 10 +++++++++
arch/arm/mach-omap2/cm81xx.h | 1 +
arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 34 +++++++++++++++++++++++++++++
6 files changed, 63 insertions(+)
--
2.9.3
^ permalink raw reply
* [PATCH v2 2/2] ata: ahci: add support for DaVinci DM816 SATA controller
From: Bartosz Golaszewski @ 2017-03-14 11:04 UTC (permalink / raw)
To: Tejun Heo, Rob Herring, Mark Rutland, Neil Armstrong,
Michael Turquette, Kevin Hilman, Patrick Titiano, Tony Lindgren,
Sergei Shtylyov
Cc: linux-ide, devicetree, linux-kernel, Bartosz Golaszewski
In-Reply-To: <1489489491-14195-1-git-send-email-bgolaszewski@baylibre.com>
This SATA controller is quite similar to the one present on the DA850
SoC, but the PHY configuration is different and it supports two HBA
ports.
The IP suffers from the same PMP issue the DA850 does - if we enable
PMP but don't use it - softreset fails. Appropriate workaround was
implemented in this driver as well.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
drivers/ata/Kconfig | 9 +++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_dm816.c | 200 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 210 insertions(+)
create mode 100644 drivers/ata/ahci_dm816.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 70b57d2..7f59a7a 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -118,6 +118,15 @@ config AHCI_DA850
If unsure, say N.
+config AHCI_DM816
+ tristate "DaVinci DM816 AHCI SATA support"
+ depends on ARCH_OMAP2PLUS
+ help
+ This option enables support for the DaVinci DM816 SoC's
+ onboard AHCI SATA controller.
+
+ If unsure, say N.
+
config AHCI_ST
tristate "ST AHCI SATA support"
depends on ARCH_STI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 89a0a19..3052c0a 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
obj-$(CONFIG_AHCI_BRCM) += ahci_brcm.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_DM816) += ahci_dm816.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_OCTEON) += ahci_octeon.o
diff --git a/drivers/ata/ahci_dm816.c b/drivers/ata/ahci_dm816.c
new file mode 100644
index 0000000..fbd827c
--- /dev/null
+++ b/drivers/ata/ahci_dm816.c
@@ -0,0 +1,200 @@
+/*
+ * DaVinci DM816 AHCI SATA platform driver
+ *
+ * Copyright (C) 2017 BayLibre SAS
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/pm.h>
+#include <linux/platform_device.h>
+#include <linux/libata.h>
+#include <linux/ahci_platform.h>
+
+#include "ahci.h"
+
+#define AHCI_DM816_DRV_NAME "ahci-dm816"
+
+#define AHCI_DM816_PHY_ENPLL(x) ((x) << 0)
+#define AHCI_DM816_PHY_MPY(x) ((x) << 1)
+#define AHCI_DM816_PHY_LOS(x) ((x) << 12)
+#define AHCI_DM816_PHY_RXCDR(x) ((x) << 13)
+#define AHCI_DM816_PHY_RXEQ(x) ((x) << 16)
+#define AHCI_DM816_PHY_TXSWING(x) ((x) << 23)
+
+#define AHCI_DM816_P0PHYCR_REG 0x178
+#define AHCI_DM816_P1PHYCR_REG 0x1f8
+
+#define AHCI_DM816_PLL_OUT 1500000000LU
+
+static const unsigned long pll_mpy_table[] = {
+ 400, 500, 600, 800, 825, 1000, 1200,
+ 1250, 1500, 1600, 1650, 2000, 2200, 2500
+};
+
+static int ahci_dm816_get_mpy_bits(unsigned long refclk_rate)
+{
+ unsigned long pll_multiplier;
+ int i;
+
+ /*
+ * We need to determine the value of the multiplier (MPY) bits.
+ * In order to include the 8.25 multiplier we need to first divide
+ * the refclk rate by 100.
+ */
+ pll_multiplier = AHCI_DM816_PLL_OUT / (refclk_rate / 100);
+
+ for (i = 0; i < ARRAY_SIZE(pll_mpy_table); i++) {
+ if (pll_mpy_table[i] == pll_multiplier)
+ return i;
+ }
+
+ /*
+ * We should have divided evenly - if not, return an invalid
+ * value.
+ */
+ return -1;
+}
+
+static int ahci_dm816_phy_init(struct ahci_host_priv *hpriv, struct device *dev)
+{
+ unsigned long refclk_rate;
+ int mpy;
+ u32 val;
+
+ /*
+ * We should have been supplied two clocks: the functional and
+ * keep-alive clock and the external reference clock. We need the
+ * rate of the latter to calculate the correct value of MPY bits.
+ */
+ if (!hpriv->clks[1]) {
+ dev_err(dev, "reference clock not supplied\n");
+ return -EINVAL;
+ }
+
+ refclk_rate = clk_get_rate(hpriv->clks[1]);
+ if ((refclk_rate % 100) != 0) {
+ dev_err(dev, "reference clock rate must be divisible by 100\n");
+ return -EINVAL;
+ }
+
+ mpy = ahci_dm816_get_mpy_bits(refclk_rate);
+ if (mpy < 0) {
+ dev_err(dev, "can't calculate the MPY bits value\n");
+ return -EINVAL;
+ }
+
+ /* Enable the PHY and configure the first HBA port. */
+ val = AHCI_DM816_PHY_MPY(mpy) | AHCI_DM816_PHY_LOS(1) |
+ AHCI_DM816_PHY_RXCDR(4) | AHCI_DM816_PHY_RXEQ(1) |
+ AHCI_DM816_PHY_TXSWING(3) | AHCI_DM816_PHY_ENPLL(1);
+ writel(val, hpriv->mmio + AHCI_DM816_P0PHYCR_REG);
+
+ /* Configure the second HBA port. */
+ val = AHCI_DM816_PHY_LOS(1) | AHCI_DM816_PHY_RXCDR(4) |
+ AHCI_DM816_PHY_RXEQ(1) | AHCI_DM816_PHY_TXSWING(3);
+ writel(val, hpriv->mmio + AHCI_DM816_P1PHYCR_REG);
+
+ return 0;
+}
+
+static int ahci_dm816_softreset(struct ata_link *link,
+ unsigned int *class, unsigned long deadline)
+{
+ int pmp, ret;
+
+ pmp = sata_srst_pmp(link);
+
+ /*
+ * There's an issue with the SATA controller on DM816 SoC: if we
+ * enable Port Multiplier support, but the drive is connected directly
+ * to the board, it can't be detected. As a workaround: if PMP is
+ * enabled, we first call ahci_do_softreset() and pass it the result of
+ * sata_srst_pmp(). If this call fails, we retry with pmp = 0.
+ */
+ ret = ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
+ if (pmp && ret == -EBUSY)
+ return ahci_do_softreset(link, class, 0,
+ deadline, ahci_check_ready);
+
+ return ret;
+}
+
+static struct ata_port_operations ahci_dm816_port_ops = {
+ .inherits = &ahci_platform_ops,
+ .softreset = ahci_dm816_softreset,
+};
+
+static const struct ata_port_info ahci_dm816_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &ahci_dm816_port_ops,
+};
+
+static struct scsi_host_template ahci_dm816_platform_sht = {
+ AHCI_SHT(AHCI_DM816_DRV_NAME),
+};
+
+static int ahci_dm816_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ahci_host_priv *hpriv;
+ int rc;
+
+ hpriv = ahci_platform_get_resources(pdev);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
+
+ rc = ahci_platform_enable_resources(hpriv);
+ if (rc)
+ return rc;
+
+ rc = ahci_dm816_phy_init(hpriv, dev);
+ if (rc)
+ goto disable_resources;
+
+ rc = ahci_platform_init_host(pdev, hpriv,
+ &ahci_dm816_port_info,
+ &ahci_dm816_platform_sht);
+ if (rc)
+ goto disable_resources;
+
+ return 0;
+
+disable_resources:
+ ahci_platform_disable_resources(hpriv);
+
+ return rc;
+}
+
+static SIMPLE_DEV_PM_OPS(ahci_dm816_pm_ops,
+ ahci_platform_suspend,
+ ahci_platform_resume);
+
+static const struct of_device_id ahci_dm816_of_match[] = {
+ { .compatible = "ti,dm816-ahci", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, ahci_dm816_of_match);
+
+static struct platform_driver ahci_dm816_driver = {
+ .probe = ahci_dm816_probe,
+ .remove = ata_platform_remove_one,
+ .driver = {
+ .name = AHCI_DM816_DRV_NAME,
+ .of_match_table = ahci_dm816_of_match,
+ .pm = &ahci_dm816_pm_ops,
+ },
+};
+module_platform_driver(ahci_dm816_driver);
+
+MODULE_DESCRIPTION("DaVinci DM816 AHCI SATA platform driver");
+MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
+MODULE_LICENSE("GPL");
--
2.9.3
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: ata: add DT bindings for ahci-dm816 SATA controller
From: Bartosz Golaszewski @ 2017-03-14 11:04 UTC (permalink / raw)
To: Tejun Heo, Rob Herring, Mark Rutland, Neil Armstrong,
Michael Turquette, Kevin Hilman, Patrick Titiano, Tony Lindgren,
Sergei Shtylyov
Cc: linux-ide-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bartosz Golaszewski
In-Reply-To: <1489489491-14195-1-git-send-email-bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Add DT bindings for the onboard SATA controller present on the DM816x
SoCs.
Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
.../devicetree/bindings/ata/ahci-dm816.txt | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/ahci-dm816.txt
diff --git a/Documentation/devicetree/bindings/ata/ahci-dm816.txt b/Documentation/devicetree/bindings/ata/ahci-dm816.txt
new file mode 100644
index 0000000..f8c535f
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/ahci-dm816.txt
@@ -0,0 +1,21 @@
+Device tree binding for the TI DM816 AHCI SATA Controller
+---------------------------------------------------------
+
+Required properties:
+ - compatible: must be "ti,dm816-ahci"
+ - reg: physical base address and size of the register region used by
+ the controller (as defined by the AHCI 1.1 standard)
+ - interrupts: interrupt specifier (refer to the interrupt binding)
+ - clocks: list of phandle and clock specifier pairs (or only
+ phandles for clock providers with '0' defined for
+ #clock-cells); two clocks must be specified: the functional
+ clock and an external reference clock
+
+Example:
+
+ sata: sata@4a140000 {
+ compatible = "ti,dm816-ahci";
+ reg = <0x4a140000 0x10000>;
+ interrupts = <16>;
+ clocks = <&sysclk5_ck>, <&sata_refclk>;
+ };
--
2.9.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH v2 0/2] ata: ahci-dm816: new driver
From: Bartosz Golaszewski @ 2017-03-14 11:04 UTC (permalink / raw)
To: Tejun Heo, Rob Herring, Mark Rutland, Neil Armstrong,
Michael Turquette, Kevin Hilman, Patrick Titiano, Tony Lindgren,
Sergei Shtylyov
Cc: linux-ide-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bartosz Golaszewski
Add support for the on-board SATA controller present on TI DM816 SoCs.
This IP suffers from the same issue DA850 does, that is: if we enable
PMP, but connect the drive directly to the board, the disk cannot be
detected. A workaround similar to the one implemented in ahci-da850 is
included in this driver as well.
Tested on DM8168-EVM.
v1 -> v2:
PATCH 1/2
- fixed the size of the mapped register region in the example
- rephrased the clocks property description
Bartosz Golaszewski (2):
dt-bindings: ata: add DT bindings for ahci-dm816 SATA controller
ata: ahci: add support for DaVinci DM816 SATA controller
.../devicetree/bindings/ata/ahci-dm816.txt | 21 +++
drivers/ata/Kconfig | 9 +
drivers/ata/Makefile | 1 +
drivers/ata/ahci_dm816.c | 200 +++++++++++++++++++++
4 files changed, 231 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/ahci-dm816.txt
create mode 100644 drivers/ata/ahci_dm816.c
--
2.9.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: ata: add DT bindings for ahci-dm816 SATA controller
From: Bartosz Golaszewski @ 2017-03-14 10:43 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Tejun Heo, Rob Herring, Mark Rutland, Neil Armstrong,
Michael Turquette, Kevin Hilman, Patrick Titiano,
linux-ide-u79uwXL29TY76Z2rM5mHXA, linux-devicetree, LKML
In-Reply-To: <61ee23f2-734b-f793-0054-364ce553ae5e-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
2017-03-13 18:27 GMT+01:00 Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>:
> On 03/13/2017 08:08 PM, Bartosz Golaszewski wrote:
>
>>>> Add DT bindings for the onboard SATA controller present on the DM816x
>>>> SoCs.
>>>>
>>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
>>>> ---
>>>> Documentation/devicetree/bindings/ata/ahci-dm816.txt | 20
>>>> ++++++++++++++++++++
>>>> 1 file changed, 20 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/ata/ahci-dm816.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/ata/ahci-dm816.txt
>>>> b/Documentation/devicetree/bindings/ata/ahci-dm816.txt
>>>> new file mode 100644
>>>> index 0000000..b87ed5a
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/ata/ahci-dm816.txt
>>>> @@ -0,0 +1,20 @@
>>>> +Device tree binding for the TI DM816 AHCI SATA Controller
>>>> +---------------------------------------------------------
>>>> +
>>>> +Required properties:
>>>> + - compatible: must be "ti,dm816-ahci"
>>>> + - reg: physical base address and size of the register region used by
>>>> + the controller (as defined by the AHCI 1.1 standard)
>>>> + - interrupts: interrupt specifier (refer to the interrupt binding)
>>>> + - clocks: clock specifiers (refer to the clock binding); two clocks
>>>
>>>
>>>
>>> There should be a phandle preceding the clock specifier, all new such
>>> props are different to the old "interrupts" (which had phandle in a
>>> separate
>>> "interrupt-parent" prop).
>
>
>> I'm afraid I don't understand - could you point me to an example?
>
>
> Have you read Documentation/devicetree/bindings/clock/clock-bindings.txt,
> on clock consumers?
Yes I have. It says:
66 clocks: List of phandle and clock specifier pairs, one pair
67 for each clock input to the device. Note: if the
68 clock provider specifies '0' for #clock-cells, then
69 only the phandle portion of the pair will appear.
> In fact, your own example below doesn't have clock specifiers, only
> phandles.
>
Since the SATA reference clock specifies 0 for #clock-cells I'll omit
the clock specifier. On the other hand: I'll rephrase the clocks
property description in the bindings for clarity.
Thanks,
Bartosz
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: ata: add DT bindings for ahci-dm816 SATA controller
From: Neil Armstrong @ 2017-03-14 9:06 UTC (permalink / raw)
To: Sergei Shtylyov, Bartosz Golaszewski
Cc: Tejun Heo, Rob Herring, Mark Rutland, Michael Turquette,
Kevin Hilman, Patrick Titiano, linux-ide, linux-devicetree, LKML
In-Reply-To: <61ee23f2-734b-f793-0054-364ce553ae5e@cogentembedded.com>
On 03/13/2017 06:27 PM, Sergei Shtylyov wrote:
> On 03/13/2017 08:08 PM, Bartosz Golaszewski wrote:
>
>>>> Add DT bindings for the onboard SATA controller present on the DM816x
>>>> SoCs.
>>>>
>>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>>>> ---
>>>> Documentation/devicetree/bindings/ata/ahci-dm816.txt | 20
>>>> ++++++++++++++++++++
>>>> 1 file changed, 20 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/ata/ahci-dm816.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/ata/ahci-dm816.txt
>>>> b/Documentation/devicetree/bindings/ata/ahci-dm816.txt
>>>> new file mode 100644
>>>> index 0000000..b87ed5a
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/ata/ahci-dm816.txt
>>>> @@ -0,0 +1,20 @@
>>>> +Device tree binding for the TI DM816 AHCI SATA Controller
>>>> +---------------------------------------------------------
>>>> +
>>>> +Required properties:
>>>> + - compatible: must be "ti,dm816-ahci"
>>>> + - reg: physical base address and size of the register region used by
>>>> + the controller (as defined by the AHCI 1.1 standard)
>>>> + - interrupts: interrupt specifier (refer to the interrupt binding)
>>>> + - clocks: clock specifiers (refer to the clock binding); two clocks
>>>
>>>
>>> There should be a phandle preceding the clock specifier, all new such
>>> props are different to the old "interrupts" (which had phandle in a separate
>>> "interrupt-parent" prop).
>
>> I'm afraid I don't understand - could you point me to an example?
>
> Have you read Documentation/devicetree/bindings/clock/clock-bindings.txt, on clock consumers?
> In fact, your own example below doesn't have clock specifiers, only phandles.
Hi Sergei,
I think it's perfectly clear since he mentions the "clock bindings", so it's clear the clocks
property must conform to the bindings described in the clock/clock-bindings.txt file.
The term "specifier" is alone not very clear, but it used as is in plenty of other
bindings files about this clocks property (i.e imx-sata.txt, ahci-fsl-qoriq.txt, ahci-ceva.txt).
And it's perfectly allowed to only have a single phandle without any arguments, as described
in the clock bindings actually.
Thanks,
Neil
>
>>>> + must be specified: the functional clock and an external
>>>> + reference clock
>>>> +
>>>> +Example:
>>>> +
>>>> + sata: sata@4a140000 {
>>>> + compatible = "ti,dm816-ahci";
>>>> + reg = <0x4a140000 0xffff>;
> [...]
>>>> + interrupts = <16>;
>>>> + clocks = <&sysclk5_ck>, <&sata_refclk>;
>>>> + };
>>>>
>
>> Thanks,
>> Bartosz Golaszewski
>
> MBR, Sergei
>
^ permalink raw reply
* Re: [PATCH 3/4] ARM: dts: dm8168-evm: add SATA node
From: Sergei Shtylyov @ 2017-03-14 9:00 UTC (permalink / raw)
To: Bartosz Golaszewski, Rob Herring, Mark Rutland, Neil Armstrong,
Michael Turquette, Kevin Hilman, Patrick Titiano, Tony Lindgren,
Paul Walmsley
Cc: linux-ide, devicetree, linux-kernel, linux-arm-kernel, linux-omap
In-Reply-To: <1489423399-3824-4-git-send-email-bgolaszewski@baylibre.com>
On 3/13/2017 7:43 PM, Bartosz Golaszewski wrote:
> Add the SATA controller node to the dm8168-evm device tree.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
[...]
> diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
> index 276211e..6131081 100644
> --- a/arch/arm/boot/dts/dm816x.dtsi
> +++ b/arch/arm/boot/dts/dm816x.dtsi
> @@ -293,6 +293,13 @@
> phy-handle = <&phy1>;
> };
>
> + sata: sata@4a140000 {
> + compatible = "ti,dm816-ahci";
> + reg = <0x4a140000 0xffff>;
Again, 0x10000 for the size.
[...]
MBR, Sergei
^ permalink raw reply
* Re: [PATCH 2/2] ata: ahci: add support for DaVinci DM816 SATA controller
From: Neil Armstrong @ 2017-03-14 9:00 UTC (permalink / raw)
To: Sergei Shtylyov, Bartosz Golaszewski, Tejun Heo, Rob Herring,
Mark Rutland, Michael Turquette, Kevin Hilman, Patrick Titiano
Cc: linux-ide, devicetree, linux-kernel
In-Reply-To: <db5d21c2-b0e2-c9ec-1f15-460973fd23e3@cogentembedded.com>
On 03/14/2017 09:57 AM, Sergei Shtylyov wrote:
> Hello!
>
> On 3/13/2017 7:36 PM, Bartosz Golaszewski wrote:
>
>> This SATA controller is quite similar to the one present on the DA850
>> SoC, but the PHY configuration is different and it supports two HBA
>> ports.
>>
>> The IP suffers from the same PMP issue the DA850 does - if we enable
>> PMP but don't use it - softreset fails. Appropriate workaround was
>> implemented in this driver as well.
>>
>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>> ---
>> drivers/ata/Kconfig | 9 +++
>> drivers/ata/Makefile | 1 +
>> drivers/ata/ahci_dm816.c | 200 +++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 210 insertions(+)
>> create mode 100644 drivers/ata/ahci_dm816.c
>>
>> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
>> index 70b57d2..7f59a7a 100644
>> --- a/drivers/ata/Kconfig
>> +++ b/drivers/ata/Kconfig
>> @@ -118,6 +118,15 @@ config AHCI_DA850
>>
>> If unsure, say N.
>>
>> +config AHCI_DM816
>> + tristate "DaVinci DM816 AHCI SATA support"
>
> Is it really DaVinci?
>
>> + depends on ARCH_OMAP2PLUS
>
> Especially if it depends on OMAP...
Hi Sergei,
Yes it's a DaVinci family SoC, but shares a lot of IPs with the OMAP family.
Neil
>
> [...]
>
> MBR, Sergei
>
^ permalink raw reply
* Re: [PATCH 2/2] ata: ahci: add support for DaVinci DM816 SATA controller
From: Sergei Shtylyov @ 2017-03-14 8:57 UTC (permalink / raw)
To: Bartosz Golaszewski, Tejun Heo, Rob Herring, Mark Rutland,
Neil Armstrong, Michael Turquette, Kevin Hilman, Patrick Titiano
Cc: linux-ide, devicetree, linux-kernel
In-Reply-To: <1489422982-3461-3-git-send-email-bgolaszewski@baylibre.com>
Hello!
On 3/13/2017 7:36 PM, Bartosz Golaszewski wrote:
> This SATA controller is quite similar to the one present on the DA850
> SoC, but the PHY configuration is different and it supports two HBA
> ports.
>
> The IP suffers from the same PMP issue the DA850 does - if we enable
> PMP but don't use it - softreset fails. Appropriate workaround was
> implemented in this driver as well.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> drivers/ata/Kconfig | 9 +++
> drivers/ata/Makefile | 1 +
> drivers/ata/ahci_dm816.c | 200 +++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 210 insertions(+)
> create mode 100644 drivers/ata/ahci_dm816.c
>
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index 70b57d2..7f59a7a 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -118,6 +118,15 @@ config AHCI_DA850
>
> If unsure, say N.
>
> +config AHCI_DM816
> + tristate "DaVinci DM816 AHCI SATA support"
Is it really DaVinci?
> + depends on ARCH_OMAP2PLUS
Especially if it depends on OMAP...
[...]
MBR, Sergei
^ permalink raw reply
* Re: [PATCH 1/4] ARM: OMAP2+: dm81xx: Add clkdm and hwmod for SATA
From: Kevin Hilman @ 2017-03-13 21:34 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Rob Herring, Mark Rutland, Neil Armstrong, Michael Turquette,
Patrick Titiano, Tony Lindgren, Paul Walmsley,
linux-ide-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-omap-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1489423399-3824-2-git-send-email-bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> writes:
> From: Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
>
> Add the SATA clockdomain (part of CM_DEFAULT) and a hwmod for the SATA
> block on dm81xx.
>
> Tested on DM8168 EVM.
>
> Signed-off-by: Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> ---
> arch/arm/mach-omap2/clockdomains81xx_data.c | 10 +++++++++
> arch/arm/mach-omap2/cm81xx.h | 2 ++
> arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 34 +++++++++++++++++++++++++++++
> 3 files changed, 46 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c
> index 3b5fb05..65fbd13 100644
> --- a/arch/arm/mach-omap2/clockdomains81xx_data.c
> +++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
> @@ -91,6 +91,14 @@ static struct clockdomain default_l3_slow_81xx_clkdm = {
> .flags = CLKDM_CAN_SWSUP,
> };
>
> +static struct clockdomain default_sata_81xx_clkdm = {
> + .name = "default_clkdm",
> + .pwrdm = { .name = "default_pwrdm" },
> + .cm_inst = TI81XX_CM_DEFAULT_MOD,
> + .clkdm_offs = TI816X_CM_DEFAULT_SATA_CLKDM,
> + .flags = CLKDM_CAN_SWSUP,
> +};
> +
> /* 816x only */
>
> static struct clockdomain alwon_mpu_816x_clkdm = {
> @@ -173,6 +181,7 @@ static struct clockdomain *clockdomains_ti814x[] __initdata = {
> &mmu_81xx_clkdm,
> &mmu_cfg_81xx_clkdm,
> &default_l3_slow_81xx_clkdm,
> + &default_sata_81xx_clkdm,
> NULL,
> };
>
> @@ -200,6 +209,7 @@ static struct clockdomain *clockdomains_ti816x[] __initdata = {
> &default_ducati_816x_clkdm,
> &default_pci_816x_clkdm,
> &default_l3_slow_81xx_clkdm,
> + &default_sata_81xx_clkdm,
> NULL,
> };
>
> diff --git a/arch/arm/mach-omap2/cm81xx.h b/arch/arm/mach-omap2/cm81xx.h
> index 3a0ccf0..44ca275 100644
> --- a/arch/arm/mach-omap2/cm81xx.h
> +++ b/arch/arm/mach-omap2/cm81xx.h
> @@ -35,6 +35,7 @@
> #define TI81XX_CM_MMU_CLKDM 0x000C
> #define TI81XX_CM_MMUCFG_CLKDM 0x0010
> #define TI81XX_CM_ALWON_MPU_CLKDM 0x001C
> +#define TI81XX_CM_ALWON_SYSCLK5_CLKDM 0x0024
oops, this is a stray addition (by me) but is no not needed.
> #define TI81XX_CM_ALWON_L3_FAST_CLKDM 0x0030
>
Kevin
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 2/4] ARM: dts: dm8168-evm: add the external reference clock for SATA
From: Tony Lindgren @ 2017-03-13 21:34 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Rob Herring, Mark Rutland, Neil Armstrong, Michael Turquette,
Kevin Hilman, Patrick Titiano, Paul Walmsley, linux-ide,
devicetree, linux-kernel, linux-arm-kernel, linux-omap
In-Reply-To: <1489423399-3824-3-git-send-email-bgolaszewski@baylibre.com>
* Bartosz Golaszewski <bgolaszewski@baylibre.com> [170313 09:45]:
> This board has an external oscillator supplying the reference clock
> signal for SATA. Its rate is fixed at 100Mhz. Add a corresponding
> device tree node.
Is this the 100MHz clock from PCIe? Just like on dm814x-evm as noted
in the workaround thread below:
http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/181083/671141
Regards,
Tony
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> arch/arm/boot/dts/dm8168-evm.dts | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
> index 0bf55fa..f13e214 100644
> --- a/arch/arm/boot/dts/dm8168-evm.dts
> +++ b/arch/arm/boot/dts/dm8168-evm.dts
> @@ -25,6 +25,12 @@
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> };
> +
> + sata_refclk: fixedclock0 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <100000000>;
> + };
> };
>
> &dm816x_pinmux {
> --
> 2.9.3
>
^ permalink raw reply
* Re: [PATCH 3/4] ARM: dts: dm8168-evm: add SATA node
From: Tony Lindgren @ 2017-03-13 21:15 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Rob Herring, Mark Rutland, Neil Armstrong, Michael Turquette,
Kevin Hilman, Patrick Titiano, Paul Walmsley, linux-ide,
devicetree, linux-kernel, linux-arm-kernel, linux-omap
In-Reply-To: <1489423399-3824-4-git-send-email-bgolaszewski@baylibre.com>
* Bartosz Golaszewski <bgolaszewski@baylibre.com> [170313 09:45]:
> Add the SATA controller node to the dm8168-evm device tree.
> --- a/arch/arm/boot/dts/dm816x.dtsi
> +++ b/arch/arm/boot/dts/dm816x.dtsi
> @@ -293,6 +293,13 @@
> phy-handle = <&phy1>;
> };
>
> + sata: sata@4a140000 {
> + compatible = "ti,dm816-ahci";
> + reg = <0x4a140000 0xffff>;
> + interrupts = <16>;
> + ti,hwmods = "sata";
> + };
The size should be 0x10000 instead of 0xffff, right?
Tony
^ permalink raw reply
* 33421 linux-ide
From: mitch_128 @ 2017-03-13 18:33 UTC (permalink / raw)
To: linux-ide
[-- Attachment #1: 63220200.zip --]
[-- Type: application/zip, Size: 5377 bytes --]
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: ata: add DT bindings for ahci-dm816 SATA controller
From: Sergei Shtylyov @ 2017-03-13 17:27 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Tejun Heo, Rob Herring, Mark Rutland, Neil Armstrong,
Michael Turquette, Kevin Hilman, Patrick Titiano, linux-ide,
linux-devicetree, LKML
In-Reply-To: <CAMpxmJUO65yZDSKhL2k1V1fYRFn3psfCtwokbsZAm61UzcdjSg@mail.gmail.com>
On 03/13/2017 08:08 PM, Bartosz Golaszewski wrote:
>>> Add DT bindings for the onboard SATA controller present on the DM816x
>>> SoCs.
>>>
>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>>> ---
>>> Documentation/devicetree/bindings/ata/ahci-dm816.txt | 20
>>> ++++++++++++++++++++
>>> 1 file changed, 20 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/ata/ahci-dm816.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/ata/ahci-dm816.txt
>>> b/Documentation/devicetree/bindings/ata/ahci-dm816.txt
>>> new file mode 100644
>>> index 0000000..b87ed5a
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/ata/ahci-dm816.txt
>>> @@ -0,0 +1,20 @@
>>> +Device tree binding for the TI DM816 AHCI SATA Controller
>>> +---------------------------------------------------------
>>> +
>>> +Required properties:
>>> + - compatible: must be "ti,dm816-ahci"
>>> + - reg: physical base address and size of the register region used by
>>> + the controller (as defined by the AHCI 1.1 standard)
>>> + - interrupts: interrupt specifier (refer to the interrupt binding)
>>> + - clocks: clock specifiers (refer to the clock binding); two clocks
>>
>>
>> There should be a phandle preceding the clock specifier, all new such
>> props are different to the old "interrupts" (which had phandle in a separate
>> "interrupt-parent" prop).
> I'm afraid I don't understand - could you point me to an example?
Have you read Documentation/devicetree/bindings/clock/clock-bindings.txt,
on clock consumers?
In fact, your own example below doesn't have clock specifiers, only phandles.
>>> + must be specified: the functional clock and an external
>>> + reference clock
>>> +
>>> +Example:
>>> +
>>> + sata: sata@4a140000 {
>>> + compatible = "ti,dm816-ahci";
>>> + reg = <0x4a140000 0xffff>;
[...]
>>> + interrupts = <16>;
>>> + clocks = <&sysclk5_ck>, <&sata_refclk>;
>>> + };
>>>
> Thanks,
> Bartosz Golaszewski
MBR, Sergei
^ permalink raw reply
* Re: [PATCH] libata: make ata_sg_clean static over again
From: Tejun Heo @ 2017-03-13 17:08 UTC (permalink / raw)
To: Jason Yan; +Cc: linux-ide, martin.petersen, linux-scsi, miaoxie
In-Reply-To: <1489111540-22046-1-git-send-email-yanaijie@huawei.com>
On Fri, Mar 10, 2017 at 10:05:40AM +0800, Jason Yan wrote:
> Fixes the following sparse warning:
>
> drivers/ata/libata-core.c:4913:6: warning: symbol 'ata_sg_clean' was not
> declared. Should it be static?
>
> Signed-off-by: Jason Yan <yanaijie@huawei.com>
Applied to libata/for-4.12.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: ata: add DT bindings for ahci-dm816 SATA controller
From: Bartosz Golaszewski @ 2017-03-13 17:08 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Tejun Heo, Rob Herring, Mark Rutland, Neil Armstrong,
Michael Turquette, Kevin Hilman, Patrick Titiano,
linux-ide-u79uwXL29TY76Z2rM5mHXA, linux-devicetree, LKML
In-Reply-To: <2d0ede95-86d6-4d52-6cf5-91de35a29145-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
2017-03-13 17:53 GMT+01:00 Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>:
> Hello!
>
> On 03/13/2017 07:36 PM, Bartosz Golaszewski wrote:
>
>> Add DT bindings for the onboard SATA controller present on the DM816x
>> SoCs.
>>
>> Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
>> ---
>> Documentation/devicetree/bindings/ata/ahci-dm816.txt | 20
>> ++++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/ata/ahci-dm816.txt
>>
>> diff --git a/Documentation/devicetree/bindings/ata/ahci-dm816.txt
>> b/Documentation/devicetree/bindings/ata/ahci-dm816.txt
>> new file mode 100644
>> index 0000000..b87ed5a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/ata/ahci-dm816.txt
>> @@ -0,0 +1,20 @@
>> +Device tree binding for the TI DM816 AHCI SATA Controller
>> +---------------------------------------------------------
>> +
>> +Required properties:
>> + - compatible: must be "ti,dm816-ahci"
>> + - reg: physical base address and size of the register region used by
>> + the controller (as defined by the AHCI 1.1 standard)
>> + - interrupts: interrupt specifier (refer to the interrupt binding)
>> + - clocks: clock specifiers (refer to the clock binding); two clocks
>
>
> There should be a phandle preceding the clock specifier, all new such
> props are different to the old "interrupts" (which had phandle in a separate
> "interrupt-parent" prop).
>
I'm afraid I don't understand - could you point me to an example?
>> + must be specified: the functional clock and an external
>> + reference clock
>> +
>> +Example:
>> +
>> + sata: sata@4a140000 {
>> + compatible = "ti,dm816-ahci";
>> + reg = <0x4a140000 0xffff>;
>
>
> I think you meant 0x10000 ISO 0xffff -- this is a size, not limit.
>
Right, thanks.
>> + interrupts = <16>;
>> + clocks = <&sysclk5_ck>, <&sata_refclk>;
>> + };
>>
>
> MBR, Sergei
>
Thanks,
Bartosz Golaszewski
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH] libata: use setup_deferrable_timer
From: Tejun Heo @ 2017-03-13 17:07 UTC (permalink / raw)
To: Geliang Tang; +Cc: linux-ide, linux-kernel
In-Reply-To: <7eff953a3a1eaa33e39692b18d59e6baecb189cc.1489060962.git.geliangtang@gmail.com>
On Sat, Mar 11, 2017 at 08:47:01AM +0800, Geliang Tang wrote:
> Use setup_deferrable_timer() instead of init_timer_deferrable() to
> simplify the code.
>
> Signed-off-by: Geliang Tang <geliangtang@gmail.com>
Applied to libata/for-4.12.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: ata: add DT bindings for ahci-dm816 SATA controller
From: Sergei Shtylyov @ 2017-03-13 16:53 UTC (permalink / raw)
To: Bartosz Golaszewski, Tejun Heo, Rob Herring, Mark Rutland,
Neil Armstrong, Michael Turquette, Kevin Hilman, Patrick Titiano
Cc: linux-ide-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1489422982-3461-2-git-send-email-bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Hello!
On 03/13/2017 07:36 PM, Bartosz Golaszewski wrote:
> Add DT bindings for the onboard SATA controller present on the DM816x
> SoCs.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> ---
> Documentation/devicetree/bindings/ata/ahci-dm816.txt | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ata/ahci-dm816.txt
>
> diff --git a/Documentation/devicetree/bindings/ata/ahci-dm816.txt b/Documentation/devicetree/bindings/ata/ahci-dm816.txt
> new file mode 100644
> index 0000000..b87ed5a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/ahci-dm816.txt
> @@ -0,0 +1,20 @@
> +Device tree binding for the TI DM816 AHCI SATA Controller
> +---------------------------------------------------------
> +
> +Required properties:
> + - compatible: must be "ti,dm816-ahci"
> + - reg: physical base address and size of the register region used by
> + the controller (as defined by the AHCI 1.1 standard)
> + - interrupts: interrupt specifier (refer to the interrupt binding)
> + - clocks: clock specifiers (refer to the clock binding); two clocks
There should be a phandle preceding the clock specifier, all new such
props are different to the old "interrupts" (which had phandle in a separate
"interrupt-parent" prop).
> + must be specified: the functional clock and an external
> + reference clock
> +
> +Example:
> +
> + sata: sata@4a140000 {
> + compatible = "ti,dm816-ahci";
> + reg = <0x4a140000 0xffff>;
I think you meant 0x10000 ISO 0xffff -- this is a size, not limit.
> + interrupts = <16>;
> + clocks = <&sysclk5_ck>, <&sata_refclk>;
> + };
>
MBR, Sergei
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 4/4] ARM: omap2plus_defconfig: enable ahci-dm816 module
From: Bartosz Golaszewski @ 2017-03-13 16:43 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Neil Armstrong, Michael Turquette,
Kevin Hilman, Patrick Titiano, Tony Lindgren, Paul Walmsley
Cc: devicetree, Bartosz Golaszewski, linux-kernel, linux-ide,
linux-omap, linux-arm-kernel
In-Reply-To: <1489423399-3824-1-git-send-email-bgolaszewski@baylibre.com>
This is now supported on the dm8168-evm board, so enable it in
the defconfig for omap2+.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
arch/arm/configs/omap2plus_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index f2462a6..3944aa9 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -141,6 +141,7 @@ CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_ATA=y
CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_DM816=m
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
--
2.9.3
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: dm8168-evm: add SATA node
From: Bartosz Golaszewski @ 2017-03-13 16:43 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Neil Armstrong, Michael Turquette,
Kevin Hilman, Patrick Titiano, Tony Lindgren, Paul Walmsley
Cc: devicetree, Bartosz Golaszewski, linux-kernel, linux-ide,
linux-omap, linux-arm-kernel
In-Reply-To: <1489423399-3824-1-git-send-email-bgolaszewski@baylibre.com>
Add the SATA controller node to the dm8168-evm device tree.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
arch/arm/boot/dts/dm8168-evm.dts | 4 ++++
arch/arm/boot/dts/dm816x.dtsi | 7 +++++++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index f13e214..547856e 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -179,3 +179,7 @@
pinctrl-0 = <&usb1_pins>;
mentor,multipoint = <0>;
};
+
+&sata {
+ clocks = <&sysclk5_ck>, <&sata_refclk>;
+};
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 276211e..6131081 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -293,6 +293,13 @@
phy-handle = <&phy1>;
};
+ sata: sata@4a140000 {
+ compatible = "ti,dm816-ahci";
+ reg = <0x4a140000 0xffff>;
+ interrupts = <16>;
+ ti,hwmods = "sata";
+ };
+
mcspi1: spi@48030000 {
compatible = "ti,omap4-mcspi";
reg = <0x48030000 0x1000>;
--
2.9.3
^ permalink raw reply related
* [PATCH 2/4] ARM: dts: dm8168-evm: add the external reference clock for SATA
From: Bartosz Golaszewski @ 2017-03-13 16:43 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Neil Armstrong, Michael Turquette,
Kevin Hilman, Patrick Titiano, Tony Lindgren, Paul Walmsley
Cc: linux-ide-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-omap-u79uwXL29TY76Z2rM5mHXA, Bartosz Golaszewski
In-Reply-To: <1489423399-3824-1-git-send-email-bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
This board has an external oscillator supplying the reference clock
signal for SATA. Its rate is fixed at 100Mhz. Add a corresponding
device tree node.
Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
arch/arm/boot/dts/dm8168-evm.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index 0bf55fa..f13e214 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -25,6 +25,12 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ sata_refclk: fixedclock0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
};
&dm816x_pinmux {
--
2.9.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 1/4] ARM: OMAP2+: dm81xx: Add clkdm and hwmod for SATA
From: Bartosz Golaszewski @ 2017-03-13 16:43 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Neil Armstrong, Michael Turquette,
Kevin Hilman, Patrick Titiano, Tony Lindgren, Paul Walmsley
Cc: devicetree, Bartosz Golaszewski, linux-kernel, linux-ide,
linux-omap, linux-arm-kernel
In-Reply-To: <1489423399-3824-1-git-send-email-bgolaszewski@baylibre.com>
From: Kevin Hilman <khilman@baylibre.com>
Add the SATA clockdomain (part of CM_DEFAULT) and a hwmod for the SATA
block on dm81xx.
Tested on DM8168 EVM.
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
arch/arm/mach-omap2/clockdomains81xx_data.c | 10 +++++++++
arch/arm/mach-omap2/cm81xx.h | 2 ++
arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 34 +++++++++++++++++++++++++++++
3 files changed, 46 insertions(+)
diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c
index 3b5fb05..65fbd13 100644
--- a/arch/arm/mach-omap2/clockdomains81xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
@@ -91,6 +91,14 @@ static struct clockdomain default_l3_slow_81xx_clkdm = {
.flags = CLKDM_CAN_SWSUP,
};
+static struct clockdomain default_sata_81xx_clkdm = {
+ .name = "default_clkdm",
+ .pwrdm = { .name = "default_pwrdm" },
+ .cm_inst = TI81XX_CM_DEFAULT_MOD,
+ .clkdm_offs = TI816X_CM_DEFAULT_SATA_CLKDM,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
/* 816x only */
static struct clockdomain alwon_mpu_816x_clkdm = {
@@ -173,6 +181,7 @@ static struct clockdomain *clockdomains_ti814x[] __initdata = {
&mmu_81xx_clkdm,
&mmu_cfg_81xx_clkdm,
&default_l3_slow_81xx_clkdm,
+ &default_sata_81xx_clkdm,
NULL,
};
@@ -200,6 +209,7 @@ static struct clockdomain *clockdomains_ti816x[] __initdata = {
&default_ducati_816x_clkdm,
&default_pci_816x_clkdm,
&default_l3_slow_81xx_clkdm,
+ &default_sata_81xx_clkdm,
NULL,
};
diff --git a/arch/arm/mach-omap2/cm81xx.h b/arch/arm/mach-omap2/cm81xx.h
index 3a0ccf0..44ca275 100644
--- a/arch/arm/mach-omap2/cm81xx.h
+++ b/arch/arm/mach-omap2/cm81xx.h
@@ -35,6 +35,7 @@
#define TI81XX_CM_MMU_CLKDM 0x000C
#define TI81XX_CM_MMUCFG_CLKDM 0x0010
#define TI81XX_CM_ALWON_MPU_CLKDM 0x001C
+#define TI81XX_CM_ALWON_SYSCLK5_CLKDM 0x0024
#define TI81XX_CM_ALWON_L3_FAST_CLKDM 0x0030
/* ACTIVE */
@@ -57,5 +58,6 @@
#define TI816X_CM_DEFAULT_PCI_CLKDM 0x0010
#define TI816X_CM_DEFAULT_L3_SLOW_CLKDM 0x0014
#define TI816X_CM_DEFAULT_DUCATI_CLKDM 0x0018
+#define TI816X_CM_DEFAULT_SATA_CLKDM 0x0060
#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index b82b77c..310afe4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -106,6 +106,7 @@
*/
#define DM81XX_CM_DEFAULT_OFFSET 0x500
#define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET)
+#define DM81XX_CM_DEFAULT_SATA_CLKCTRL (0x560 - DM81XX_CM_DEFAULT_OFFSET)
/* L3 Interconnect entries clocked at 125, 250 and 500MHz */
static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
@@ -973,6 +974,38 @@ static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
.user = OCP_USER_MPU,
};
+static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = {
+ .sysc_offs = 0x1100,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = SIDLE_FORCE,
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dm81xx_sata_hwmod_class = {
+ .name = "sata",
+ .sysc = &dm81xx_sata_sysc,
+};
+
+static struct omap_hwmod dm81xx_sata_hwmod = {
+ .name = "sata",
+ .clkdm_name = "default_sata_clkdm",
+ .flags = HWMOD_NO_IDLEST,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .class = &dm81xx_sata_hwmod_class,
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = {
+ .master = &dm81xx_l4_hs_hwmod,
+ .slave = &dm81xx_sata_hwmod,
+ .clk = "sysclk5_ck",
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x110,
@@ -1474,6 +1507,7 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
&dm81xx_l4_hs__emac0,
&dm81xx_emac0__mdio,
&dm816x_l4_hs__emac1,
+ &dm81xx_l4_hs__sata,
&dm81xx_alwon_l3_fast__tpcc,
&dm81xx_alwon_l3_fast__tptc0,
&dm81xx_alwon_l3_fast__tptc1,
--
2.9.3
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox