* Re: [PATCH v1] ata: sata_rcar: Handle return value of clk_prepare_enable
From: Sergei Shtylyov @ 2017-05-10 9:02 UTC (permalink / raw)
To: Arvind Yadav, tj; +Cc: linux-ide, linux-kernel
In-Reply-To: <1494325828-2725-1-git-send-email-arvind.yadav.cs@gmail.com>
Hello.
On 5/9/2017 1:30 PM, Arvind Yadav wrote:
> Here, Clock enable can failed. So adding an error check for
Maybe "here enabling the clock can fail"?
> clk_prepare_enable.
>
> Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Other than that:
Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
MBR, Sergei
^ permalink raw reply
* Re: [PATCH 1/4] ata: Add DT bindings for Faraday Technology FTIDE010
From: Bartlomiej Zolnierkiewicz @ 2017-05-10 13:59 UTC (permalink / raw)
To: Linus Walleij
Cc: Tejun Heo, linux-ide, Janos Laube, Paulius Zaleckas,
openwrt-devel, linux-arm-kernel@lists.infradead.org,
Hans Ulli Kroll, Florian Fainelli, devicetree@vger.kernel.org,
John Feng-Hsin Chiang, Greentime Hu
In-Reply-To: <CACRpkdbmOsrxKX8=a7bvcF+c=Q2tfwYQVt0=cz+_jhDyadwa2A@mail.gmail.com>
On Monday, May 08, 2017 10:26:49 PM Linus Walleij wrote:
> On Mon, May 8, 2017 at 12:47 PM, Bartlomiej Zolnierkiewicz
> <b.zolnierkie@samsung.com> wrote:
>
> > Also for all current drivers we just put timing values (or a logic
> > to calculate them from the standard ATA timings) into the driver
> > itself and not device tree (as they are based on values are dictated
> > by ATA standard and should not change for a given controller type).
>
> I had it like that at first (and I can of course switch it back). But I
> came to think this is better.
>
> I was looking at these values from the point that it depends a bit
> on the silicon where it is synthesized. So the vendor tree has
> things like this:
>
> #ifndef SL2312_FPGA_IDE
> static unsigned char PIO_TIMING[5] = { 0xaa, 0xa3, 0xa1, 0x33, 0x31 };
> static unsigned char TIMING_MDMA_50M[3] = { 0x66, 0x22, 0x21 };
> static unsigned char TIMING_MDMA_66M[3] = { 0x88, 0x32, 0x31 };
> static unsigned char TIMING_UDMA_50M[6] = { 0x33, 0x31, 0x21, 0x21,
> 0x11, 0x91 };
> static unsigned char TIMING_UDMA_66M[7] = { 0x44, 0x42, 0x31, 0x21,
> 0x11, 0x91, 0x91};
> #else
> static unsigned char PIO_TIMING[5] = { 0x88, 0x82, 0x81, 0x32, 0x21 };
> static unsigned char TIMING_MDMA_50M[3] = { 0x33, 0x11, 0x11 };
> static unsigned char TIMING_MDMA_66M[3] = { 0x33, 0x11, 0x11 };
> static unsigned char TIMING_UDMA_50M[6] = { 0x22, 0x11, 0x11, 0x11 };
> static unsigned char TIMING_UDMA_66M[7] = { 0x22, 0x11, 0x11, 0x11 };
> #endif
>
> (From D-Link DIR-685 source release from Storlink/Cortina board support.)
>
> So depending on whether they use an FPGA or an ASIC the values are
> different, no matter what frequency (50 or 66 MHz) is used. So it is not
> derived from frequency.
>
> So I think it makes most sense to have it in the device tree as we don't
> know what designs are out there.
I still would prefer to keep timing values private to the driver and just
select the controller type (FPGA/ASIC) using the device tree.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
^ permalink raw reply
* Re: [PATCH 1/4] ata: Add DT bindings for Faraday Technology FTIDE010
From: Linus Walleij @ 2017-05-10 15:48 UTC (permalink / raw)
To: Bartlomiej Zolnierkiewicz
Cc: Tejun Heo, linux-ide-u79uwXL29TY76Z2rM5mHXA, Janos Laube,
Paulius Zaleckas, openwrt-devel-p3rKhJxN3npAfugRpC6u6w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Hans Ulli Kroll, Florian Fainelli,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
John Feng-Hsin Chiang, Greentime Hu
In-Reply-To: <6650456.qCJGCGKGLl@amdc3058>
On Wed, May 10, 2017 at 3:59 PM, Bartlomiej Zolnierkiewicz
<b.zolnierkie-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
> On Monday, May 08, 2017 10:26:49 PM Linus Walleij wrote:
>> On Mon, May 8, 2017 at 12:47 PM, Bartlomiej Zolnierkiewicz
>> <b.zolnierkie-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
>> So depending on whether they use an FPGA or an ASIC the values are
>> different, no matter what frequency (50 or 66 MHz) is used. So it is not
>> derived from frequency.
>>
>> So I think it makes most sense to have it in the device tree as we don't
>> know what designs are out there.
>
> I still would prefer to keep timing values private to the driver and just
> select the controller type (FPGA/ASIC) using the device tree.
OK I'll revert to static timings in the driver, no problem.
Yours,
Linus Walleij
--
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^ permalink raw reply
* [PATCH] ata: avoid gcc-7 warning in ata_timing_quantize
From: Arnd Bergmann @ 2017-05-11 12:51 UTC (permalink / raw)
To: Tejun Heo; +Cc: Arnd Bergmann, Adam Manzanares, linux-ide, linux-kernel
gcc-7 warns about the result of a constant multiplication used as
a boolean:
drivers/ata/libata-core.c: In function 'ata_timing_quantize':
drivers/ata/libata-core.c:3164:30: warning: '*' in boolean context, suggest '&&' instead [-Wint-in-bool-context]
This slightly rearranges the macro to simplify the code and avoid
the warning at the same time.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/ata/libata-core.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 2d83b8c75965..3fc4c35425f6 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -3157,19 +3157,19 @@ static const struct ata_timing ata_timing[] = {
};
#define ENOUGH(v, unit) (((v)-1)/(unit)+1)
-#define EZ(v, unit) ((v)?ENOUGH(v, unit):0)
+#define EZ(v, unit) ((v)?ENOUGH((v * 1000), unit):0)
static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
{
- q->setup = EZ(t->setup * 1000, T);
- q->act8b = EZ(t->act8b * 1000, T);
- q->rec8b = EZ(t->rec8b * 1000, T);
- q->cyc8b = EZ(t->cyc8b * 1000, T);
- q->active = EZ(t->active * 1000, T);
- q->recover = EZ(t->recover * 1000, T);
- q->dmack_hold = EZ(t->dmack_hold * 1000, T);
- q->cycle = EZ(t->cycle * 1000, T);
- q->udma = EZ(t->udma * 1000, UT);
+ q->setup = EZ(t->setup, T);
+ q->act8b = EZ(t->act8b, T);
+ q->rec8b = EZ(t->rec8b, T);
+ q->cyc8b = EZ(t->cyc8b, T);
+ q->active = EZ(t->active, T);
+ q->recover = EZ(t->recover, T);
+ q->dmack_hold = EZ(t->dmack_hold, T);
+ q->cycle = EZ(t->cycle, T);
+ q->udma = EZ(t->udma, UT);
}
void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
--
2.9.0
^ permalink raw reply related
* [PATCH] ide: avoid warning for timings calculation
From: Arnd Bergmann @ 2017-05-11 12:52 UTC (permalink / raw)
To: David S. Miller; +Cc: Arnd Bergmann, linux-ide, linux-kernel
gcc-7 warns about the result of a constant multiplication used as
a boolean:
drivers/ide/ide-timings.c: In function 'ide_timing_quantize':
drivers/ide/ide-timings.c:112:24: error: '*' in boolean context, suggest '&&' instead [-Werror=int-in-bool-context]
q->setup = EZ(t->setup * 1000, T);
This slightly rearranges the macro to simplify the code and avoid
the warning at the same time.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/ide/ide-timings.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/ide/ide-timings.c b/drivers/ide/ide-timings.c
index 0e05f75934c9..9da64c1de85c 100644
--- a/drivers/ide/ide-timings.c
+++ b/drivers/ide/ide-timings.c
@@ -104,19 +104,19 @@ u16 ide_pio_cycle_time(ide_drive_t *drive, u8 pio)
EXPORT_SYMBOL_GPL(ide_pio_cycle_time);
#define ENOUGH(v, unit) (((v) - 1) / (unit) + 1)
-#define EZ(v, unit) ((v) ? ENOUGH(v, unit) : 0)
+#define EZ(v, unit) ((v) ? ENOUGH(v * 1000, unit) : 0)
static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q,
int T, int UT)
{
- q->setup = EZ(t->setup * 1000, T);
- q->act8b = EZ(t->act8b * 1000, T);
- q->rec8b = EZ(t->rec8b * 1000, T);
- q->cyc8b = EZ(t->cyc8b * 1000, T);
- q->active = EZ(t->active * 1000, T);
- q->recover = EZ(t->recover * 1000, T);
- q->cycle = EZ(t->cycle * 1000, T);
- q->udma = EZ(t->udma * 1000, UT);
+ q->setup = EZ(t->setup, T);
+ q->act8b = EZ(t->act8b, T);
+ q->rec8b = EZ(t->rec8b, T);
+ q->cyc8b = EZ(t->cyc8b, T);
+ q->active = EZ(t->active, T);
+ q->recover = EZ(t->recover, T);
+ q->cycle = EZ(t->cycle, T);
+ q->udma = EZ(t->udma, UT);
}
void ide_timing_merge(struct ide_timing *a, struct ide_timing *b,
--
2.9.0
^ permalink raw reply related
* Re: [PATCH] ata: avoid gcc-7 warning in ata_timing_quantize
From: Tejun Heo @ 2017-05-11 14:50 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: Adam Manzanares, linux-ide, linux-kernel
In-Reply-To: <20170511125145.265782-1-arnd@arndb.de>
Hello, Arnd.
On Thu, May 11, 2017 at 02:51:25PM +0200, Arnd Bergmann wrote:
> gcc-7 warns about the result of a constant multiplication used as
> a boolean:
>
> drivers/ata/libata-core.c: In function 'ata_timing_quantize':
> drivers/ata/libata-core.c:3164:30: warning: '*' in boolean context, suggest '&&' instead [-Wint-in-bool-context]
>
> This slightly rearranges the macro to simplify the code and avoid
> the warning at the same time.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Heh, that's an interesting new warning. Appied to
libata/for-4.12-fixes.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 0/3] SATA: Fine-tuning for two function implementations
From: Bartlomiej Zolnierkiewicz @ 2017-05-11 15:01 UTC (permalink / raw)
To: Tejun Heo
Cc: SF Markus Elfring, linux-ide, Hans de Goede, LKML,
kernel-janitors
In-Reply-To: <20170428215334.GH22354@htj.duckdns.org>
Hi,
On Friday, April 28, 2017 05:53:34 PM Tejun Heo wrote:
> Hello,
>
> On Tue, Apr 18, 2017 at 10:00:37PM +0200, SF Markus Elfring wrote:
> > From: Markus Elfring <elfring@users.sourceforge.net>
> > Date: Tue, 18 Apr 2017 21:54:32 +0200
> >
> > A few update suggestions were taken into account
> > from static source code analysis.
>
> Hmmm, allocs -> callocs. Are these actually beneficial? If so, why?
> Because one multiplication is rolled into the call?
Each conversion (i.e. I tried the one from patch #1) seems to add
an extra 24 bytes to the resulting code size (using gcc 4.8.4 for
ARM32 cross-compilation) so I don't see much point in the automatic
conversions. Only instances containing size calculations with
real possibility for integer overflows should be converted and
the patchset under discussion contains no such instances.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
^ permalink raw reply
* [PATCH V3 0/3] ADD AHCI support for tegra210
From: Preetham Chandru Ramchandra @ 2017-05-12 9:34 UTC (permalink / raw)
To: thierry.reding, tj
Cc: tegra, linux-ide, ldewangan, preetham260, vbyravarasu, pkunapuli,
Preetham Chandru R
From: Preetham Chandru R <pchandru@nvidia.com>
1. ADD AHCI support for tegra210
2. Extend the tegra AHCI controller device tree binding with tegra210
---
Preetham Chandru R (3):
ata: ahci_tegra: Add AHCI support for tegra210
dt-bindings: tegra: Add tegra210 AHCI
arm64: tegra: Enable SATA on Tegra210
.../bindings/ata/nvidia,tegra124-ahci.txt | 45 ++-
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 6 +
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 16 +
drivers/ata/ahci_tegra.c | 377 ++++++++++++++++-----
4 files changed, 346 insertions(+), 98 deletions(-)
--
2.1.4
^ permalink raw reply
* [PATCH V3 1/3] ata: ahci_tegra: Add AHCI support for tegra210
From: Preetham Chandru Ramchandra @ 2017-05-12 9:34 UTC (permalink / raw)
To: thierry.reding, tj
Cc: tegra, linux-ide, ldewangan, preetham260, vbyravarasu, pkunapuli,
Preetham Chandru R
In-Reply-To: <1494581650-11115-1-git-send-email-pchandru@nvidia.com>
From: Preetham Chandru R <pchandru@nvidia.com>
1. Move tegra124 specifics to tegra124_ahci_init.
2. Separate the regulators needed for tegra124 and tegra210.
3. Disable DIPM and Devslp for t210 and t124 as there are known issues
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
---
v3:
* Remove inline functions for read/write and modify to
SATA, SATA Config and SATA Aux registers.
* Add code to disable DIPM and DevSlp for t210 and t124
v2:
* Fix indentation issues
* Move the change to disable DIPM, HIPM, DevSlp, partial,
slumber and NCQ into a separate patch
---
drivers/ata/ahci_tegra.c | 377 ++++++++++++++++++++++++++++++++++++-----------
1 file changed, 293 insertions(+), 84 deletions(-)
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index 3a62eb2..cd581a6 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata/ahci_tegra.c
@@ -34,7 +34,8 @@
#define DRV_NAME "tegra-ahci"
#define SATA_CONFIGURATION_0 0x180
-#define SATA_CONFIGURATION_EN_FPCI BIT(0)
+#define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
+#define SATA_CONFIGURATION_0_CLK_OVERRIDE BIT(31)
#define SCFG_OFFSET 0x1000
@@ -45,17 +46,55 @@
#define T_SATA0_CFG_1_SERR BIT(8)
#define T_SATA0_CFG_9 0x24
-#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13
+#define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000
#define SATA_FPCI_BAR5 0x94
-#define SATA_FPCI_BAR5_START_SHIFT 4
+#define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4)
+#define SATA_FPCI_BAR5_START (0x0040020 << 4)
+#define SATA_FPCI_BAR5_ACCESS_TYPE (0x1)
#define SATA_INTR_MASK 0x188
#define SATA_INTR_MASK_IP_INT_MASK BIT(16)
+#define T_SATA0_CFG_35 0x94
+#define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2)
+#define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2)
+
+#define T_SATA0_AHCI_IDP1 0x98
+#define T_SATA0_AHCI_IDP1_DATA (0x400040)
+
+#define T_SATA0_CFG_PHY_1 0x12c
+#define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23)
+#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22)
+
+#define T_SATA0_NVOOB 0x114
+#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
+#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
+#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
+#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
+#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
+#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
+
+#define T_SATA_CFG_PHY_0 0x120
+#define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11)
+#define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24)
+
+#define T_SATA0_CFG2NVOOB_2 0x134
+#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff << 18)
+#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
+
#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
+#define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13)
+#define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14)
+#define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26)
+#define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17)
+#define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30)
#define T_SATA0_BKDOOR_CC 0x4a4
+#define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16)
+#define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
+#define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8)
+#define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8)
#define T_SATA0_CFG_SATA 0x54c
#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
@@ -82,9 +121,35 @@
#define T_SATA0_CHX_PHY_CTRL11 0x6d0
#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
+#define T_SATA0_CHX_PHY_CTRL17_0 0x6e8
+#define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000
+#define T_SATA0_CHX_PHY_CTRL18_0 0x6ec
+#define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000
+#define T_SATA0_CHX_PHY_CTRL20_0 0x6f4
+#define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1
+#define T_SATA0_CHX_PHY_CTRL21_0 0x6f8
+#define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1
+
+/* AUX Registers */
+#define SATA_AUX_MISC_CNTL_1_0 0x8
+#define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE BIT(17)
+#define SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT BIT(13)
+#define SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT BIT(15)
+
+#define SATA_AUX_RX_STAT_INT_0 0xc
+#define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP BIT(7)
+
+#define SATA_AUX_SPARE_CFG0_0 0x18
+#define SATA_AUX_SPARE_CFG0_0_MDAT_TIMER_AFTER_PG_VALID BIT(14)
+
#define FUSE_SATA_CALIB 0x124
#define FUSE_SATA_CALIB_MASK 0x3
+enum {
+ NO_DEVSLP = (1 << 0),
+ NO_DIPM = (1 << 1),
+};
+
struct sata_pad_calibration {
u8 gen1_tx_amp;
u8 gen1_tx_peak;
@@ -99,15 +164,89 @@ static const struct sata_pad_calibration tegra124_pad_calibration[] = {
{0x14, 0x0e, 0x1a, 0x0e},
};
+struct tegra_ahci_ops {
+ int (*init)(struct ahci_host_priv *);
+};
+
+struct tegra_ahci_soc {
+ const char *const *supply_names;
+ u32 num_supplies;
+ u32 quirks;
+ struct tegra_ahci_ops ops;
+};
+
struct tegra_ahci_priv {
struct platform_device *pdev;
void __iomem *sata_regs;
+ void __iomem *sata_aux_regs;
struct reset_control *sata_rst;
struct reset_control *sata_oob_rst;
struct reset_control *sata_cold_rst;
/* Needs special handling, cannot use ahci_platform */
struct clk *sata_clk;
- struct regulator_bulk_data supplies[5];
+ struct regulator_bulk_data *supplies;
+ struct tegra_ahci_soc *soc_data;
+};
+
+static const char *const tegra124_supply_names[] = {
+ "avdd", "hvdd", "vddio", "target-5v", "target-12v"
+};
+
+static int tegra124_ahci_init(struct ahci_host_priv *hpriv)
+{
+ struct tegra_ahci_priv *tegra = hpriv->plat_data;
+ struct sata_pad_calibration calib;
+ int ret;
+ u32 val;
+
+ /* Pad calibration */
+ ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
+ if (ret)
+ return ret;
+
+ calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
+
+ writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
+
+ val = readl(tegra->sata_regs +
+ SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
+ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
+ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
+ val |= calib.gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
+ val |= calib.gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
+ writel(val, tegra->sata_regs + SCFG_OFFSET +
+ T_SATA0_CHX_PHY_CTRL1_GEN1);
+
+ val = readl(tegra->sata_regs +
+ SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
+ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
+ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
+ val |= calib.gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
+ val |= calib.gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
+ writel(val, tegra->sata_regs + SCFG_OFFSET +
+ T_SATA0_CHX_PHY_CTRL1_GEN2);
+
+ writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
+ tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
+ writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
+ tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
+
+ writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
+
+ return 0;
+}
+
+static const struct tegra_ahci_soc tegra124_ahci_soc_data = {
+ .supply_names = tegra124_supply_names,
+ .num_supplies = ARRAY_SIZE(tegra124_supply_names),
+ .quirks = NO_DIPM | NO_DEVSLP,
+ .ops = {
+ .init = tegra124_ahci_init,
+ },
+};
+
+static const struct tegra_ahci_soc tegra210_ahci_soc_data = {
+ .quirks = NO_DIPM | NO_DEVSLP,
};
static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
@@ -115,7 +254,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
struct tegra_ahci_priv *tegra = hpriv->plat_data;
int ret;
- ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
+ ret = regulator_bulk_enable(tegra->soc_data->num_supplies,
tegra->supplies);
if (ret)
return ret;
@@ -144,8 +283,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
disable_regulators:
- regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
-
+ regulator_bulk_disable(tegra->soc_data->num_supplies, tegra->supplies);
return ret;
}
@@ -162,97 +300,137 @@ static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
clk_disable_unprepare(tegra->sata_clk);
tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
- regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
+ regulator_bulk_disable(tegra->soc_data->num_supplies, tegra->supplies);
}
static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
{
struct tegra_ahci_priv *tegra = hpriv->plat_data;
int ret;
- unsigned int val;
- struct sata_pad_calibration calib;
+ u32 val;
ret = tegra_ahci_power_on(hpriv);
- if (ret) {
- dev_err(&tegra->pdev->dev,
- "failed to power on AHCI controller: %d\n", ret);
+ if (ret)
return ret;
- }
+ /*
+ * Program the following SATA IPFS registers
+ * to allow SW accesses to SATA's MMIO Register
+ */
+ val = readl(tegra->sata_regs + SATA_FPCI_BAR5);
+ val &= ~(SATA_FPCI_BAR5_START_MASK | SATA_FPCI_BAR5_ACCESS_TYPE);
+ val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE;
+ writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
+
+ /* Program the following SATA IPFS register to enable the SATA */
val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
- val |= SATA_CONFIGURATION_EN_FPCI;
+ val |= SATA_CONFIGURATION_0_EN_FPCI;
writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
- /* Pad calibration */
-
- ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
- if (ret) {
- dev_err(&tegra->pdev->dev,
- "failed to read calibration fuse: %d\n", ret);
- return ret;
- }
-
- calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
-
- writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
-
- val = readl(tegra->sata_regs +
- SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
- val |= calib.gen1_tx_amp <<
- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
- val |= calib.gen1_tx_peak <<
- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
- writel(val, tegra->sata_regs + SCFG_OFFSET +
- T_SATA0_CHX_PHY_CTRL1_GEN1);
-
- val = readl(tegra->sata_regs +
- SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
- val |= calib.gen2_tx_amp <<
- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
- val |= calib.gen2_tx_peak <<
- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
- writel(val, tegra->sata_regs + SCFG_OFFSET +
- T_SATA0_CHX_PHY_CTRL1_GEN2);
-
- writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
- tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
- writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
- tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
-
- writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
-
- /* Program controller device ID */
+ /* Electrical settings for better link stability */
+ val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1;
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0);
+ val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2;
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0);
+ val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1;
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0);
+ val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2;
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0);
+
+ /* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */
+
+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
+ val |= T_SATA_CFG_PHY_0_MASK_SQUELCH;
+ val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
+
+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
+ val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK |
+ T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
+ T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
+ val |= (T_SATA0_NVOOB_COMMA_CNT |
+ T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
+ T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
+
+ /*
+ * Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to 58.8ns
+ */
+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
+ val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
+ val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
+
+ if (tegra->soc_data->ops.init)
+ tegra->soc_data->ops.init(hpriv);
+
+ /*
+ * Program the following SATA configuration registers
+ * to initialize SATA
+ */
+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
+ val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
+ T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR);
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
+ val = T_SATA0_CFG_9_BASE_ADDRESS;
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
+ /* Program Class Code and Programming interface for SATA */
val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
- writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
+ val &=
+ ~(T_SATA0_BKDOOR_CC_CLASS_CODE_MASK |
+ T_SATA0_BKDOOR_CC_PROG_IF_MASK);
+ val |= T_SATA0_BKDOOR_CC_CLASS_CODE | T_SATA0_BKDOOR_CC_PROG_IF;
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
- /* Enable IO & memory access, bus master mode */
-
- val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
- val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
- T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR;
- writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
-
- /* Program SATA MMIO */
-
- writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
- tegra->sata_regs + SATA_FPCI_BAR5);
-
- writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
- tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
+ /* Enabling LPM capabilities through Backdoor Programming */
+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
+ val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
+ T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
+ T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
+ T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM);
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
+
+ /* SATA Second Level Clock Gating configuration
+ * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane
+ * IDDQ Signals
+ */
+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
+ val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
+ val |= T_SATA0_CFG_35_IDP_INDEX;
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
+
+ val = T_SATA0_AHCI_IDP1_DATA;
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
+
+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
+ val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
+ T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN);
+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
+
+ /*
+ * Indicate Sata only has the capability to enter DevSleep
+ * from slumber link.
+ */
+
+ val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
+ val |= SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT;
+ writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
+
+ /* Enabling IPFS Clock Gating */
+ val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
+ val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
+ writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
- /* Unmask SATA interrupts */
+ tegra_ahci_handle_quirks(hpriv);
val = readl(tegra->sata_regs + SATA_INTR_MASK);
val |= SATA_INTR_MASK_IP_INT_MASK;
@@ -278,7 +456,7 @@ static struct ata_port_operations ahci_tegra_port_ops = {
.host_stop = tegra_ahci_host_stop,
};
-static const struct ata_port_info ahci_tegra_port_info = {
+static struct ata_port_info ahci_tegra_port_info = {
.flags = AHCI_FLAG_COMMON,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
@@ -286,7 +464,14 @@ static const struct ata_port_info ahci_tegra_port_info = {
};
static const struct of_device_id tegra_ahci_of_match[] = {
- { .compatible = "nvidia,tegra124-ahci" },
+ {
+ .compatible = "nvidia,tegra124-ahci",
+ .data = &tegra124_ahci_soc_data
+ },
+ {
+ .compatible = "nvidia,tegra210-ahci",
+ .data = &tegra210_ahci_soc_data
+ },
{}
};
MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
@@ -295,12 +480,27 @@ static struct scsi_host_template ahci_platform_sht = {
AHCI_SHT(DRV_NAME),
};
+static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv)
+{
+ struct tegra_ahci_priv *tegra = hpriv->plat_data;
+ u32 val;
+
+ if (tegra->soc_data->quirks & NO_DEVSLP) {
+ val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
+ val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
+ writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
+ } else if (tegra->soc_data->quirks & NO_DIPM) {
+ ahci_tegra_port_info.flags |= ATA_FLAG_NO_DIPM;
+ }
+}
+
static int tegra_ahci_probe(struct platform_device *pdev)
{
struct ahci_host_priv *hpriv;
struct tegra_ahci_priv *tegra;
struct resource *res;
int ret;
+ unsigned int i;
hpriv = ahci_platform_get_resources(pdev);
if (IS_ERR(hpriv))
@@ -311,13 +511,18 @@ static int tegra_ahci_probe(struct platform_device *pdev)
return -ENOMEM;
hpriv->plat_data = tegra;
-
tegra->pdev = pdev;
+ tegra->soc_data =
+ (struct tegra_ahci_soc *)of_device_get_match_data(&pdev->dev);
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(tegra->sata_regs))
return PTR_ERR(tegra->sata_regs);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(tegra->sata_aux_regs))
+ return PTR_ERR(tegra->sata_aux_regs);
tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
if (IS_ERR(tegra->sata_rst)) {
@@ -343,13 +548,17 @@ static int tegra_ahci_probe(struct platform_device *pdev)
return PTR_ERR(tegra->sata_clk);
}
- tegra->supplies[0].supply = "avdd";
- tegra->supplies[1].supply = "hvdd";
- tegra->supplies[2].supply = "vddio";
- tegra->supplies[3].supply = "target-5v";
- tegra->supplies[4].supply = "target-12v";
+ tegra->supplies = devm_kcalloc(&pdev->dev,
+ tegra->soc_data->num_supplies,
+ sizeof(*tegra->supplies), GFP_KERNEL);
+ if (!tegra->supplies)
+ return -ENOMEM;
+
+ for (i = 0; i < tegra->soc_data->num_supplies; i++)
+ tegra->supplies[i].supply = tegra->soc_data->supply_names[i];
- ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies),
+ ret = devm_regulator_bulk_get(&pdev->dev,
+ tegra->soc_data->num_supplies,
tegra->supplies);
if (ret) {
dev_err(&pdev->dev, "Failed to get regulators\n");
@@ -385,5 +594,5 @@ static struct platform_driver tegra_ahci_driver = {
module_platform_driver(tegra_ahci_driver);
MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
-MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
+MODULE_DESCRIPTION("Tegra AHCI SATA driver");
MODULE_LICENSE("GPL v2");
--
2.1.4
^ permalink raw reply related
* [PATCH V3 2/3] dt-bindings: tegra: Add tegra210 AHCI
From: Preetham Chandru Ramchandra @ 2017-05-12 9:34 UTC (permalink / raw)
To: thierry.reding, tj
Cc: tegra, linux-ide, ldewangan, preetham260, vbyravarasu, pkunapuli,
Preetham Chandru R
In-Reply-To: <1494581650-11115-1-git-send-email-pchandru@nvidia.com>
From: Preetham Chandru R <pchandru@nvidia.com>
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
---
v3:
* Add AUX register.
v2:
* change cml1, pll_e and phy regulators as optional
for T210.
---
.../bindings/ata/nvidia,tegra124-ahci.txt | 45 +++++++++++++++-------
1 file changed, 31 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
index 66c83c3..dc62dba 100644
--- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
+++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
@@ -1,32 +1,49 @@
-Tegra124 SoC SATA AHCI controller
+Tegra SoC SATA AHCI controller
Required properties :
-- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise,
- must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
- is tegra132.
-- reg : Should contain 2 entries:
+- compatible : Must be one of:
+ - Tegra124 : "nvidia,tegra124-ahci"
+ - Tegra210 : "nvidia,tegra210-ahci"
+- reg : Should contain 3 entries:
- AHCI register set (SATA BAR5)
- SATA register set
+ - AUX register set
- interrupts : Defines the interrupt used by SATA
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
- sata
- sata-oob
- - cml1
- - pll_e
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
- sata
- sata-oob
- - sata-cold
+ - For T124: sata-cold
- phys : Must contain an entry for each entry in phy-names.
See ../phy/phy-bindings.txt for details.
- phy-names : Must include the following entries:
- - sata-phy : XUSB PADCTL SATA PHY
-- hvdd-supply : Defines the SATA HVDD regulator
-- vddio-supply : Defines the SATA VDDIO regulator
-- avdd-supply : Defines the SATA AVDD regulator
-- target-5v-supply : Defines the SATA 5V power regulator
-- target-12v-supply : Defines the SATA 12V power regulator
+ - For T124:
+ - sata-phy : XUSB PADCTL SATA PHY
+ - For T210:
+ - sata-0
+- For T124:
+ - hvdd-supply : Defines the SATA HVDD regulator
+ - vddio-supply : Defines the SATA VDDIO regulator
+ - avdd-supply : Defines the SATA AVDD regulator
+ - target-5v-supply : Defines the SATA 5V power regulator
+
+Optional properties:
+- clock-names :
+ - cml1 :
+ cml1 clock is required by phy so it is optional to define
+ here as phy driver will be enabling this clock.
+ - pll_e :
+ pll_e is the parent of cml1 clock so it is optional to define
+ here as phy driver will be enabling this clock.
+- For T210:
+ - l0-hvddio-sata-supply : Defines the SATA HVDDIO regulator
+ - l0-dvddio-sata-supply : Defines the SATA DVDDIO regulator
+ - hvdd-pex-pll-e-supply : Defines the PEX PLL_E regulator
+ - dvdd-sata-pll-supply : Defines the SATA PLL regulator
+ - hvdd-sata-supply : Defines the SATA HVDD regulator
--
2.1.4
^ permalink raw reply related
* [PATCH V3 3/3] arm64: tegra: Enable SATA on Tegra210
From: Preetham Chandru Ramchandra @ 2017-05-12 9:34 UTC (permalink / raw)
To: thierry.reding, tj
Cc: tegra, linux-ide, ldewangan, preetham260, vbyravarasu, pkunapuli,
Preetham Chandru R
In-Reply-To: <1494581650-11115-1-git-send-email-pchandru@nvidia.com>
From: Preetham Chandru R <pchandru@nvidia.com>
Enable the SATA unit on Tegra210 systems.
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 6 ++++++
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 16 ++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index e5fc67b..58c28b9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -1324,6 +1324,12 @@
status = "okay";
};
+ sata@70020000 {
+ status = "okay";
+ phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
+ phy-names = "sata-0";
+ };
+
padctl@7009f000 {
status = "okay";
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 8f26c4d..20c9160 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -795,6 +795,22 @@
#iommu-cells = <1>;
};
+ sata@70020000 {
+ compatible = "nvidia,tegra210-ahci";
+ reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
+ <0x0 0x70020000 0x0 0x7000>, /* SATA */
+ <0x0 0x70001100 0x0 0x1000>; /* SATA AUX*/
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_SATA>,
+ <&tegra_car TEGRA210_CLK_SATA_OOB>;
+ clock-names = "sata", "sata-oob";
+ resets = <&tegra_car 124>,
+ <&tegra_car 123>,
+ <&tegra_car 129>;
+ reset-names = "sata", "sata-oob", "sata-cold";
+ status = "disabled";
+ };
+
hda@70030000 {
compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
reg = <0x0 0x70030000 0x0 0x10000>;
--
2.1.4
^ permalink raw reply related
* RE: [PATCH V3 0/3] ADD AHCI support for tegra210
From: Preetham Chandru @ 2017-05-12 9:45 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Laxman Dewangan,
preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
Venu Byravarasu, Pavan Kunapuli,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1494581650-11115-1-git-send-email-pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
+CC linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>-----Original Message-----
>From: Preetham Chandru
>Sent: Friday, May 12, 2017 3:04 PM
>To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
>Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Laxman Dewangan
><ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; Venu Byravarasu
><vbyravarasu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Pavan Kunapuli <pkunapuli-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Preetham
>Chandru <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>Subject: [PATCH V3 0/3] ADD AHCI support for tegra210
>
>From: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
>1. ADD AHCI support for tegra210
>2. Extend the tegra AHCI controller device tree binding with tegra210
>---
>Preetham Chandru R (3):
> ata: ahci_tegra: Add AHCI support for tegra210
> dt-bindings: tegra: Add tegra210 AHCI
> arm64: tegra: Enable SATA on Tegra210
>
> .../bindings/ata/nvidia,tegra124-ahci.txt | 45 ++-
> arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 6 +
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 16 +
> drivers/ata/ahci_tegra.c | 377 ++++++++++++++++-----
> 4 files changed, 346 insertions(+), 98 deletions(-)
>
>--
>2.1.4
^ permalink raw reply
* RE: [PATCH V3 1/3] ata: ahci_tegra: Add AHCI support for tegra210
From: Preetham Chandru @ 2017-05-12 9:45 UTC (permalink / raw)
To: thierry.reding@gmail.com, tj@kernel.org
Cc: tegra@vger.kernel.org, linux-ide@vger.kernel.org, Laxman Dewangan,
preetham260@gmail.com, Venu Byravarasu, Pavan Kunapuli
In-Reply-To: <1494581650-11115-2-git-send-email-pchandru@nvidia.com>
+CC linux-tegra@vger.kernel.org
>-----Original Message-----
>From: Preetham Chandru
>Sent: Friday, May 12, 2017 3:04 PM
>To: thierry.reding@gmail.com; tj@kernel.org
>Cc: tegra@vger.kernel.org; linux-ide@vger.kernel.org; Laxman Dewangan
><ldewangan@nvidia.com>; preetham260@gmail.com; Venu Byravarasu
><vbyravarasu@nvidia.com>; Pavan Kunapuli <pkunapuli@nvidia.com>; Preetham
>Chandru <pchandru@nvidia.com>
>Subject: [PATCH V3 1/3] ata: ahci_tegra: Add AHCI support for tegra210
>
>From: Preetham Chandru R <pchandru@nvidia.com>
>
>1. Move tegra124 specifics to tegra124_ahci_init.
>2. Separate the regulators needed for tegra124 and tegra210.
>3. Disable DIPM and Devslp for t210 and t124 as there are known issues
>
>Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
>---
>v3:
>* Remove inline functions for read/write and modify to
> SATA, SATA Config and SATA Aux registers.
>* Add code to disable DIPM and DevSlp for t210 and t124
>v2:
>* Fix indentation issues
>* Move the change to disable DIPM, HIPM, DevSlp, partial,
> slumber and NCQ into a separate patch
>---
> drivers/ata/ahci_tegra.c | 377 ++++++++++++++++++++++++++++++++++++-------
>----
> 1 file changed, 293 insertions(+), 84 deletions(-)
>
>diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c index
>3a62eb2..cd581a6 100644
>--- a/drivers/ata/ahci_tegra.c
>+++ b/drivers/ata/ahci_tegra.c
>@@ -34,7 +34,8 @@
> #define DRV_NAME "tegra-ahci"
>
> #define SATA_CONFIGURATION_0 0x180
>-#define SATA_CONFIGURATION_EN_FPCI BIT(0)
>+#define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
>+#define SATA_CONFIGURATION_0_CLK_OVERRIDE BIT(31)
>
> #define SCFG_OFFSET 0x1000
>
>@@ -45,17 +46,55 @@
> #define T_SATA0_CFG_1_SERR BIT(8)
>
> #define T_SATA0_CFG_9 0x24
>-#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13
>+#define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000
>
> #define SATA_FPCI_BAR5 0x94
>-#define SATA_FPCI_BAR5_START_SHIFT 4
>+#define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4)
>+#define SATA_FPCI_BAR5_START (0x0040020 <<
>4)
>+#define SATA_FPCI_BAR5_ACCESS_TYPE (0x1)
>
> #define SATA_INTR_MASK 0x188
> #define SATA_INTR_MASK_IP_INT_MASK BIT(16)
>
>+#define T_SATA0_CFG_35 0x94
>+#define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2)
>+#define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2)
>+
>+#define T_SATA0_AHCI_IDP1 0x98
>+#define T_SATA0_AHCI_IDP1_DATA (0x400040)
>+
>+#define T_SATA0_CFG_PHY_1 0x12c
>+#define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23)
>+#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22)
>+
>+#define T_SATA0_NVOOB 0x114
>+#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
>+#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
>+#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
>+#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
>+#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
>+#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
>+
>+#define T_SATA_CFG_PHY_0 0x120
>+#define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11)
>+#define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24)
>+
>+#define T_SATA0_CFG2NVOOB_2 0x134
>+#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff
><< 18)
>+#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
>+
> #define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
>+#define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13)
>+#define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14)
>+#define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26)
>+#define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17)
>+#define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30)
>
> #define T_SATA0_BKDOOR_CC 0x4a4
>+#define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16)
>+#define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
>+#define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8)
>+#define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8)
>
> #define T_SATA0_CFG_SATA 0x54c
> #define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
>@@ -82,9 +121,35 @@
> #define T_SATA0_CHX_PHY_CTRL11 0x6d0
> #define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
>
>+#define T_SATA0_CHX_PHY_CTRL17_0 0x6e8
>+#define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000
>+#define T_SATA0_CHX_PHY_CTRL18_0 0x6ec
>+#define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000
>+#define T_SATA0_CHX_PHY_CTRL20_0 0x6f4
>+#define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1
>+#define T_SATA0_CHX_PHY_CTRL21_0 0x6f8
>+#define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1
>+
>+/* AUX Registers */
>+#define SATA_AUX_MISC_CNTL_1_0 0x8
>+#define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE BIT(17)
>+#define SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT BIT(13)
>+#define SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT BIT(15)
>+
>+#define SATA_AUX_RX_STAT_INT_0 0xc
>+#define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP BIT(7)
>+
>+#define SATA_AUX_SPARE_CFG0_0 0x18
>+#define SATA_AUX_SPARE_CFG0_0_MDAT_TIMER_AFTER_PG_VALID BIT(14)
>+
> #define FUSE_SATA_CALIB 0x124
> #define FUSE_SATA_CALIB_MASK 0x3
>
>+enum {
>+ NO_DEVSLP = (1 << 0),
>+ NO_DIPM = (1 << 1),
>+};
>+
> struct sata_pad_calibration {
> u8 gen1_tx_amp;
> u8 gen1_tx_peak;
>@@ -99,15 +164,89 @@ static const struct sata_pad_calibration
>tegra124_pad_calibration[] = {
> {0x14, 0x0e, 0x1a, 0x0e},
> };
>
>+struct tegra_ahci_ops {
>+ int (*init)(struct ahci_host_priv *);
>+};
>+
>+struct tegra_ahci_soc {
>+ const char *const *supply_names;
>+ u32 num_supplies;
>+ u32 quirks;
>+ struct tegra_ahci_ops ops;
>+};
>+
> struct tegra_ahci_priv {
> struct platform_device *pdev;
> void __iomem *sata_regs;
>+ void __iomem *sata_aux_regs;
> struct reset_control *sata_rst;
> struct reset_control *sata_oob_rst;
> struct reset_control *sata_cold_rst;
> /* Needs special handling, cannot use ahci_platform */
> struct clk *sata_clk;
>- struct regulator_bulk_data supplies[5];
>+ struct regulator_bulk_data *supplies;
>+ struct tegra_ahci_soc *soc_data;
>+};
>+
>+static const char *const tegra124_supply_names[] = {
>+ "avdd", "hvdd", "vddio", "target-5v", "target-12v"
>+};
>+
>+static int tegra124_ahci_init(struct ahci_host_priv *hpriv) {
>+ struct tegra_ahci_priv *tegra = hpriv->plat_data;
>+ struct sata_pad_calibration calib;
>+ int ret;
>+ u32 val;
>+
>+ /* Pad calibration */
>+ ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
>+ if (ret)
>+ return ret;
>+
>+ calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
>+
>+ writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
>+
>+ val = readl(tegra->sata_regs +
>+ SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
>+ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
>+ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
>+ val |= calib.gen1_tx_amp <<
>T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
>+ val |= calib.gen1_tx_peak <<
>T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>+ T_SATA0_CHX_PHY_CTRL1_GEN1);
>+
>+ val = readl(tegra->sata_regs +
>+ SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
>+ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
>+ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
>+ val |= calib.gen2_tx_amp <<
>T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
>+ val |= calib.gen2_tx_peak <<
>T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>+ T_SATA0_CHX_PHY_CTRL1_GEN2);
>+
>+ writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
>+ tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
>+ writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
>+ tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
>+
>+ writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
>+
>+ return 0;
>+}
>+
>+static const struct tegra_ahci_soc tegra124_ahci_soc_data = {
>+ .supply_names = tegra124_supply_names,
>+ .num_supplies = ARRAY_SIZE(tegra124_supply_names),
>+ .quirks = NO_DIPM | NO_DEVSLP,
>+ .ops = {
>+ .init = tegra124_ahci_init,
>+ },
>+};
>+
>+static const struct tegra_ahci_soc tegra210_ahci_soc_data = {
>+ .quirks = NO_DIPM | NO_DEVSLP,
> };
>
> static int tegra_ahci_power_on(struct ahci_host_priv *hpriv) @@ -115,7 +254,7
>@@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
> struct tegra_ahci_priv *tegra = hpriv->plat_data;
> int ret;
>
>- ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
>+ ret = regulator_bulk_enable(tegra->soc_data->num_supplies,
> tegra->supplies);
> if (ret)
> return ret;
>@@ -144,8 +283,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv
>*hpriv)
> tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
>
> disable_regulators:
>- regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
>-
>+ regulator_bulk_disable(tegra->soc_data->num_supplies,
>+tegra->supplies);
> return ret;
> }
>
>@@ -162,97 +300,137 @@ static void tegra_ahci_power_off(struct
>ahci_host_priv *hpriv)
> clk_disable_unprepare(tegra->sata_clk);
> tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
>
>- regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
>+ regulator_bulk_disable(tegra->soc_data->num_supplies,
>+tegra->supplies);
> }
>
> static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv) {
> struct tegra_ahci_priv *tegra = hpriv->plat_data;
> int ret;
>- unsigned int val;
>- struct sata_pad_calibration calib;
>+ u32 val;
>
> ret = tegra_ahci_power_on(hpriv);
>- if (ret) {
>- dev_err(&tegra->pdev->dev,
>- "failed to power on AHCI controller: %d\n", ret);
>+ if (ret)
> return ret;
>- }
>
>+ /*
>+ * Program the following SATA IPFS registers
>+ * to allow SW accesses to SATA's MMIO Register
>+ */
>+ val = readl(tegra->sata_regs + SATA_FPCI_BAR5);
>+ val &= ~(SATA_FPCI_BAR5_START_MASK |
>SATA_FPCI_BAR5_ACCESS_TYPE);
>+ val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE;
>+ writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
>+
>+ /* Program the following SATA IPFS register to enable the SATA */
> val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
>- val |= SATA_CONFIGURATION_EN_FPCI;
>+ val |= SATA_CONFIGURATION_0_EN_FPCI;
> writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
>
>- /* Pad calibration */
>-
>- ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
>- if (ret) {
>- dev_err(&tegra->pdev->dev,
>- "failed to read calibration fuse: %d\n", ret);
>- return ret;
>- }
>-
>- calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
>-
>- writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
>-
>- val = readl(tegra->sata_regs +
>- SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
>- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
>- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
>- val |= calib.gen1_tx_amp <<
>- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
>- val |= calib.gen1_tx_peak <<
>- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
>- writel(val, tegra->sata_regs + SCFG_OFFSET +
>- T_SATA0_CHX_PHY_CTRL1_GEN1);
>-
>- val = readl(tegra->sata_regs +
>- SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
>- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
>- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
>- val |= calib.gen2_tx_amp <<
>- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
>- val |= calib.gen2_tx_peak <<
>- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
>- writel(val, tegra->sata_regs + SCFG_OFFSET +
>- T_SATA0_CHX_PHY_CTRL1_GEN2);
>-
>- writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
>- tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
>- writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
>- tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
>-
>- writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
>-
>- /* Program controller device ID */
>+ /* Electrical settings for better link stability */
>+ val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>T_SATA0_CHX_PHY_CTRL17_0);
>+ val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>T_SATA0_CHX_PHY_CTRL18_0);
>+ val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>T_SATA0_CHX_PHY_CTRL20_0);
>+ val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>+T_SATA0_CHX_PHY_CTRL21_0);
>+
>+ /* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */
>+
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
>+ val |= T_SATA_CFG_PHY_0_MASK_SQUELCH;
>+ val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
>+
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
>+ val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK |
>+ T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
>+ T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
>+ val |= (T_SATA0_NVOOB_COMMA_CNT |
>+ T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
>+ T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
>+
>+ /*
>+ * Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to
>58.8ns
>+ */
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
>+ val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
>+ val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
>+
>+ if (tegra->soc_data->ops.init)
>+ tegra->soc_data->ops.init(hpriv);
>+
>+ /*
>+ * Program the following SATA configuration registers
>+ * to initialize SATA
>+ */
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
>+ val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
>+ T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR);
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
>+ val = T_SATA0_CFG_9_BASE_ADDRESS;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
>
>+ /* Program Class Code and Programming interface for SATA */
> val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
> val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
> writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
>
>- writel(0x01060100, tegra->sata_regs + SCFG_OFFSET +
>T_SATA0_BKDOOR_CC);
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
>+ val &=
>+ ~(T_SATA0_BKDOOR_CC_CLASS_CODE_MASK |
>+ T_SATA0_BKDOOR_CC_PROG_IF_MASK);
>+ val |= T_SATA0_BKDOOR_CC_CLASS_CODE |
>T_SATA0_BKDOOR_CC_PROG_IF;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
>
> val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
> val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
> writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
>
>- /* Enable IO & memory access, bus master mode */
>-
>- val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
>- val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
>- T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR;
>- writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
>-
>- /* Program SATA MMIO */
>-
>- writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
>- tegra->sata_regs + SATA_FPCI_BAR5);
>-
>- writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
>- tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
>+ /* Enabling LPM capabilities through Backdoor Programming */
>+ val = readl(tegra->sata_regs + SCFG_OFFSET +
>T_SATA0_AHCI_HBA_CAP_BKDR);
>+ val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
>+ T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
>+ T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
>+ T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM);
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>+T_SATA0_AHCI_HBA_CAP_BKDR);
>+
>+ /* SATA Second Level Clock Gating configuration
>+ * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane
>+ * IDDQ Signals
>+ */
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
>+ val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
>+ val |= T_SATA0_CFG_35_IDP_INDEX;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
>+
>+ val = T_SATA0_AHCI_IDP1_DATA;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
>+
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
>+ val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
>+ T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN);
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
>+
>+ /*
>+ * Indicate Sata only has the capability to enter DevSleep
>+ * from slumber link.
>+ */
>+
>+ val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
>+ val |= SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT;
>+ writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
>+
>+ /* Enabling IPFS Clock Gating */
>+ val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
>+ val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
>+ writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
>
>- /* Unmask SATA interrupts */
>+ tegra_ahci_handle_quirks(hpriv);
>
> val = readl(tegra->sata_regs + SATA_INTR_MASK);
> val |= SATA_INTR_MASK_IP_INT_MASK;
>@@ -278,7 +456,7 @@ static struct ata_port_operations ahci_tegra_port_ops =
>{
> .host_stop = tegra_ahci_host_stop,
> };
>
>-static const struct ata_port_info ahci_tegra_port_info = {
>+static struct ata_port_info ahci_tegra_port_info = {
> .flags = AHCI_FLAG_COMMON,
> .pio_mask = ATA_PIO4,
> .udma_mask = ATA_UDMA6,
>@@ -286,7 +464,14 @@ static const struct ata_port_info ahci_tegra_port_info =
>{ };
>
> static const struct of_device_id tegra_ahci_of_match[] = {
>- { .compatible = "nvidia,tegra124-ahci" },
>+ {
>+ .compatible = "nvidia,tegra124-ahci",
>+ .data = &tegra124_ahci_soc_data
>+ },
>+ {
>+ .compatible = "nvidia,tegra210-ahci",
>+ .data = &tegra210_ahci_soc_data
>+ },
> {}
> };
> MODULE_DEVICE_TABLE(of, tegra_ahci_of_match); @@ -295,12 +480,27 @@
>static struct scsi_host_template ahci_platform_sht = {
> AHCI_SHT(DRV_NAME),
> };
>
>+static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv) {
>+ struct tegra_ahci_priv *tegra = hpriv->plat_data;
>+ u32 val;
>+
>+ if (tegra->soc_data->quirks & NO_DEVSLP) {
>+ val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
>+ val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
>+ writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
>+ } else if (tegra->soc_data->quirks & NO_DIPM) {
>+ ahci_tegra_port_info.flags |= ATA_FLAG_NO_DIPM;
>+ }
>+}
>+
> static int tegra_ahci_probe(struct platform_device *pdev) {
> struct ahci_host_priv *hpriv;
> struct tegra_ahci_priv *tegra;
> struct resource *res;
> int ret;
>+ unsigned int i;
>
> hpriv = ahci_platform_get_resources(pdev);
> if (IS_ERR(hpriv))
>@@ -311,13 +511,18 @@ static int tegra_ahci_probe(struct platform_device
>*pdev)
> return -ENOMEM;
>
> hpriv->plat_data = tegra;
>-
> tegra->pdev = pdev;
>+ tegra->soc_data =
>+ (struct tegra_ahci_soc *)of_device_get_match_data(&pdev->dev);
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(tegra->sata_regs))
> return PTR_ERR(tegra->sata_regs);
>+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>+ tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
>+ if (IS_ERR(tegra->sata_aux_regs))
>+ return PTR_ERR(tegra->sata_aux_regs);
>
> tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
> if (IS_ERR(tegra->sata_rst)) {
>@@ -343,13 +548,17 @@ static int tegra_ahci_probe(struct platform_device
>*pdev)
> return PTR_ERR(tegra->sata_clk);
> }
>
>- tegra->supplies[0].supply = "avdd";
>- tegra->supplies[1].supply = "hvdd";
>- tegra->supplies[2].supply = "vddio";
>- tegra->supplies[3].supply = "target-5v";
>- tegra->supplies[4].supply = "target-12v";
>+ tegra->supplies = devm_kcalloc(&pdev->dev,
>+ tegra->soc_data->num_supplies,
>+ sizeof(*tegra->supplies), GFP_KERNEL);
>+ if (!tegra->supplies)
>+ return -ENOMEM;
>+
>+ for (i = 0; i < tegra->soc_data->num_supplies; i++)
>+ tegra->supplies[i].supply = tegra->soc_data->supply_names[i];
>
>- ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra-
>>supplies),
>+ ret = devm_regulator_bulk_get(&pdev->dev,
>+ tegra->soc_data->num_supplies,
> tegra->supplies);
> if (ret) {
> dev_err(&pdev->dev, "Failed to get regulators\n"); @@ -385,5
>+594,5 @@ static struct platform_driver tegra_ahci_driver = {
>module_platform_driver(tegra_ahci_driver);
>
> MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
>-MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
>+MODULE_DESCRIPTION("Tegra AHCI SATA driver");
> MODULE_LICENSE("GPL v2");
>--
>2.1.4
^ permalink raw reply
* RE: [PATCH V3 1/3] ata: ahci_tegra: Add AHCI support for tegra210
From: Preetham Chandru @ 2017-05-12 9:55 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Laxman Dewangan,
preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
Venu Byravarasu, Pavan Kunapuli,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1494581650-11115-2-git-send-email-pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
+CC linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>-----Original Message-----
>From: Preetham Chandru
>Sent: Friday, May 12, 2017 3:04 PM
>To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
>Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Laxman Dewangan
><ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; Venu Byravarasu
><vbyravarasu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Pavan Kunapuli <pkunapuli-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Preetham
>Chandru <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>Subject: [PATCH V3 1/3] ata: ahci_tegra: Add AHCI support for tegra210
>
>From: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
>1. Move tegra124 specifics to tegra124_ahci_init.
>2. Separate the regulators needed for tegra124 and tegra210.
>3. Disable DIPM and Devslp for t210 and t124 as there are known issues
>
>Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>---
>v3:
>* Remove inline functions for read/write and modify to
> SATA, SATA Config and SATA Aux registers.
>* Add code to disable DIPM and DevSlp for t210 and t124
>v2:
>* Fix indentation issues
>* Move the change to disable DIPM, HIPM, DevSlp, partial,
> slumber and NCQ into a separate patch
>---
> drivers/ata/ahci_tegra.c | 377 ++++++++++++++++++++++++++++++++++++-------
>----
> 1 file changed, 293 insertions(+), 84 deletions(-)
>
>diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c index
>3a62eb2..cd581a6 100644
>--- a/drivers/ata/ahci_tegra.c
>+++ b/drivers/ata/ahci_tegra.c
>@@ -34,7 +34,8 @@
> #define DRV_NAME "tegra-ahci"
>
> #define SATA_CONFIGURATION_0 0x180
>-#define SATA_CONFIGURATION_EN_FPCI BIT(0)
>+#define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
>+#define SATA_CONFIGURATION_0_CLK_OVERRIDE BIT(31)
>
> #define SCFG_OFFSET 0x1000
>
>@@ -45,17 +46,55 @@
> #define T_SATA0_CFG_1_SERR BIT(8)
>
> #define T_SATA0_CFG_9 0x24
>-#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13
>+#define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000
>
> #define SATA_FPCI_BAR5 0x94
>-#define SATA_FPCI_BAR5_START_SHIFT 4
>+#define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4)
>+#define SATA_FPCI_BAR5_START (0x0040020 <<
>4)
>+#define SATA_FPCI_BAR5_ACCESS_TYPE (0x1)
>
> #define SATA_INTR_MASK 0x188
> #define SATA_INTR_MASK_IP_INT_MASK BIT(16)
>
>+#define T_SATA0_CFG_35 0x94
>+#define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2)
>+#define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2)
>+
>+#define T_SATA0_AHCI_IDP1 0x98
>+#define T_SATA0_AHCI_IDP1_DATA (0x400040)
>+
>+#define T_SATA0_CFG_PHY_1 0x12c
>+#define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23)
>+#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22)
>+
>+#define T_SATA0_NVOOB 0x114
>+#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
>+#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
>+#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
>+#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
>+#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
>+#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
>+
>+#define T_SATA_CFG_PHY_0 0x120
>+#define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11)
>+#define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24)
>+
>+#define T_SATA0_CFG2NVOOB_2 0x134
>+#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff
><< 18)
>+#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
>+
> #define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
>+#define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13)
>+#define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14)
>+#define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26)
>+#define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17)
>+#define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30)
>
> #define T_SATA0_BKDOOR_CC 0x4a4
>+#define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16)
>+#define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
>+#define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8)
>+#define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8)
>
> #define T_SATA0_CFG_SATA 0x54c
> #define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
>@@ -82,9 +121,35 @@
> #define T_SATA0_CHX_PHY_CTRL11 0x6d0
> #define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
>
>+#define T_SATA0_CHX_PHY_CTRL17_0 0x6e8
>+#define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000
>+#define T_SATA0_CHX_PHY_CTRL18_0 0x6ec
>+#define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000
>+#define T_SATA0_CHX_PHY_CTRL20_0 0x6f4
>+#define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1
>+#define T_SATA0_CHX_PHY_CTRL21_0 0x6f8
>+#define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1
>+
>+/* AUX Registers */
>+#define SATA_AUX_MISC_CNTL_1_0 0x8
>+#define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE BIT(17)
>+#define SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT BIT(13)
>+#define SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT BIT(15)
>+
>+#define SATA_AUX_RX_STAT_INT_0 0xc
>+#define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP BIT(7)
>+
>+#define SATA_AUX_SPARE_CFG0_0 0x18
>+#define SATA_AUX_SPARE_CFG0_0_MDAT_TIMER_AFTER_PG_VALID BIT(14)
>+
> #define FUSE_SATA_CALIB 0x124
> #define FUSE_SATA_CALIB_MASK 0x3
>
>+enum {
>+ NO_DEVSLP = (1 << 0),
>+ NO_DIPM = (1 << 1),
>+};
>+
> struct sata_pad_calibration {
> u8 gen1_tx_amp;
> u8 gen1_tx_peak;
>@@ -99,15 +164,89 @@ static const struct sata_pad_calibration
>tegra124_pad_calibration[] = {
> {0x14, 0x0e, 0x1a, 0x0e},
> };
>
>+struct tegra_ahci_ops {
>+ int (*init)(struct ahci_host_priv *);
>+};
>+
>+struct tegra_ahci_soc {
>+ const char *const *supply_names;
>+ u32 num_supplies;
>+ u32 quirks;
>+ struct tegra_ahci_ops ops;
>+};
>+
> struct tegra_ahci_priv {
> struct platform_device *pdev;
> void __iomem *sata_regs;
>+ void __iomem *sata_aux_regs;
> struct reset_control *sata_rst;
> struct reset_control *sata_oob_rst;
> struct reset_control *sata_cold_rst;
> /* Needs special handling, cannot use ahci_platform */
> struct clk *sata_clk;
>- struct regulator_bulk_data supplies[5];
>+ struct regulator_bulk_data *supplies;
>+ struct tegra_ahci_soc *soc_data;
>+};
>+
>+static const char *const tegra124_supply_names[] = {
>+ "avdd", "hvdd", "vddio", "target-5v", "target-12v"
>+};
>+
>+static int tegra124_ahci_init(struct ahci_host_priv *hpriv) {
>+ struct tegra_ahci_priv *tegra = hpriv->plat_data;
>+ struct sata_pad_calibration calib;
>+ int ret;
>+ u32 val;
>+
>+ /* Pad calibration */
>+ ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
>+ if (ret)
>+ return ret;
>+
>+ calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
>+
>+ writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
>+
>+ val = readl(tegra->sata_regs +
>+ SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
>+ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
>+ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
>+ val |= calib.gen1_tx_amp <<
>T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
>+ val |= calib.gen1_tx_peak <<
>T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>+ T_SATA0_CHX_PHY_CTRL1_GEN1);
>+
>+ val = readl(tegra->sata_regs +
>+ SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
>+ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
>+ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
>+ val |= calib.gen2_tx_amp <<
>T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
>+ val |= calib.gen2_tx_peak <<
>T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>+ T_SATA0_CHX_PHY_CTRL1_GEN2);
>+
>+ writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
>+ tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
>+ writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
>+ tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
>+
>+ writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
>+
>+ return 0;
>+}
>+
>+static const struct tegra_ahci_soc tegra124_ahci_soc_data = {
>+ .supply_names = tegra124_supply_names,
>+ .num_supplies = ARRAY_SIZE(tegra124_supply_names),
>+ .quirks = NO_DIPM | NO_DEVSLP,
>+ .ops = {
>+ .init = tegra124_ahci_init,
>+ },
>+};
>+
>+static const struct tegra_ahci_soc tegra210_ahci_soc_data = {
>+ .quirks = NO_DIPM | NO_DEVSLP,
> };
>
> static int tegra_ahci_power_on(struct ahci_host_priv *hpriv) @@ -115,7 +254,7
>@@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
> struct tegra_ahci_priv *tegra = hpriv->plat_data;
> int ret;
>
>- ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
>+ ret = regulator_bulk_enable(tegra->soc_data->num_supplies,
> tegra->supplies);
> if (ret)
> return ret;
>@@ -144,8 +283,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv
>*hpriv)
> tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
>
> disable_regulators:
>- regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
>-
>+ regulator_bulk_disable(tegra->soc_data->num_supplies,
>+tegra->supplies);
> return ret;
> }
>
>@@ -162,97 +300,137 @@ static void tegra_ahci_power_off(struct
>ahci_host_priv *hpriv)
> clk_disable_unprepare(tegra->sata_clk);
> tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
>
>- regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
>+ regulator_bulk_disable(tegra->soc_data->num_supplies,
>+tegra->supplies);
> }
>
> static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv) {
> struct tegra_ahci_priv *tegra = hpriv->plat_data;
> int ret;
>- unsigned int val;
>- struct sata_pad_calibration calib;
>+ u32 val;
>
> ret = tegra_ahci_power_on(hpriv);
>- if (ret) {
>- dev_err(&tegra->pdev->dev,
>- "failed to power on AHCI controller: %d\n", ret);
>+ if (ret)
> return ret;
>- }
>
>+ /*
>+ * Program the following SATA IPFS registers
>+ * to allow SW accesses to SATA's MMIO Register
>+ */
>+ val = readl(tegra->sata_regs + SATA_FPCI_BAR5);
>+ val &= ~(SATA_FPCI_BAR5_START_MASK |
>SATA_FPCI_BAR5_ACCESS_TYPE);
>+ val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE;
>+ writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
>+
>+ /* Program the following SATA IPFS register to enable the SATA */
> val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
>- val |= SATA_CONFIGURATION_EN_FPCI;
>+ val |= SATA_CONFIGURATION_0_EN_FPCI;
> writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
>
>- /* Pad calibration */
>-
>- ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
>- if (ret) {
>- dev_err(&tegra->pdev->dev,
>- "failed to read calibration fuse: %d\n", ret);
>- return ret;
>- }
>-
>- calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
>-
>- writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
>-
>- val = readl(tegra->sata_regs +
>- SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
>- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
>- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
>- val |= calib.gen1_tx_amp <<
>- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
>- val |= calib.gen1_tx_peak <<
>- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
>- writel(val, tegra->sata_regs + SCFG_OFFSET +
>- T_SATA0_CHX_PHY_CTRL1_GEN1);
>-
>- val = readl(tegra->sata_regs +
>- SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
>- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
>- val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
>- val |= calib.gen2_tx_amp <<
>- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
>- val |= calib.gen2_tx_peak <<
>- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
>- writel(val, tegra->sata_regs + SCFG_OFFSET +
>- T_SATA0_CHX_PHY_CTRL1_GEN2);
>-
>- writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
>- tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
>- writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
>- tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
>-
>- writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
>-
>- /* Program controller device ID */
>+ /* Electrical settings for better link stability */
>+ val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>T_SATA0_CHX_PHY_CTRL17_0);
>+ val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>T_SATA0_CHX_PHY_CTRL18_0);
>+ val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>T_SATA0_CHX_PHY_CTRL20_0);
>+ val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>+T_SATA0_CHX_PHY_CTRL21_0);
>+
>+ /* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */
>+
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
>+ val |= T_SATA_CFG_PHY_0_MASK_SQUELCH;
>+ val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
>+
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
>+ val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK |
>+ T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
>+ T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
>+ val |= (T_SATA0_NVOOB_COMMA_CNT |
>+ T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
>+ T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
>+
>+ /*
>+ * Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to
>58.8ns
>+ */
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
>+ val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
>+ val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
>+
>+ if (tegra->soc_data->ops.init)
>+ tegra->soc_data->ops.init(hpriv);
>+
>+ /*
>+ * Program the following SATA configuration registers
>+ * to initialize SATA
>+ */
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
>+ val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
>+ T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR);
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
>+ val = T_SATA0_CFG_9_BASE_ADDRESS;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
>
>+ /* Program Class Code and Programming interface for SATA */
> val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
> val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
> writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
>
>- writel(0x01060100, tegra->sata_regs + SCFG_OFFSET +
>T_SATA0_BKDOOR_CC);
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
>+ val &=
>+ ~(T_SATA0_BKDOOR_CC_CLASS_CODE_MASK |
>+ T_SATA0_BKDOOR_CC_PROG_IF_MASK);
>+ val |= T_SATA0_BKDOOR_CC_CLASS_CODE |
>T_SATA0_BKDOOR_CC_PROG_IF;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
>
> val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
> val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
> writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
>
>- /* Enable IO & memory access, bus master mode */
>-
>- val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
>- val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
>- T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR;
>- writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
>-
>- /* Program SATA MMIO */
>-
>- writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
>- tegra->sata_regs + SATA_FPCI_BAR5);
>-
>- writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
>- tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
>+ /* Enabling LPM capabilities through Backdoor Programming */
>+ val = readl(tegra->sata_regs + SCFG_OFFSET +
>T_SATA0_AHCI_HBA_CAP_BKDR);
>+ val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
>+ T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
>+ T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
>+ T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM);
>+ writel(val, tegra->sata_regs + SCFG_OFFSET +
>+T_SATA0_AHCI_HBA_CAP_BKDR);
>+
>+ /* SATA Second Level Clock Gating configuration
>+ * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane
>+ * IDDQ Signals
>+ */
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
>+ val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
>+ val |= T_SATA0_CFG_35_IDP_INDEX;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
>+
>+ val = T_SATA0_AHCI_IDP1_DATA;
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
>+
>+ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
>+ val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
>+ T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN);
>+ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
>+
>+ /*
>+ * Indicate Sata only has the capability to enter DevSleep
>+ * from slumber link.
>+ */
>+
>+ val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
>+ val |= SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT;
>+ writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
>+
>+ /* Enabling IPFS Clock Gating */
>+ val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
>+ val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
>+ writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
>
>- /* Unmask SATA interrupts */
>+ tegra_ahci_handle_quirks(hpriv);
>
> val = readl(tegra->sata_regs + SATA_INTR_MASK);
> val |= SATA_INTR_MASK_IP_INT_MASK;
>@@ -278,7 +456,7 @@ static struct ata_port_operations ahci_tegra_port_ops =
>{
> .host_stop = tegra_ahci_host_stop,
> };
>
>-static const struct ata_port_info ahci_tegra_port_info = {
>+static struct ata_port_info ahci_tegra_port_info = {
> .flags = AHCI_FLAG_COMMON,
> .pio_mask = ATA_PIO4,
> .udma_mask = ATA_UDMA6,
>@@ -286,7 +464,14 @@ static const struct ata_port_info ahci_tegra_port_info =
>{ };
>
> static const struct of_device_id tegra_ahci_of_match[] = {
>- { .compatible = "nvidia,tegra124-ahci" },
>+ {
>+ .compatible = "nvidia,tegra124-ahci",
>+ .data = &tegra124_ahci_soc_data
>+ },
>+ {
>+ .compatible = "nvidia,tegra210-ahci",
>+ .data = &tegra210_ahci_soc_data
>+ },
> {}
> };
> MODULE_DEVICE_TABLE(of, tegra_ahci_of_match); @@ -295,12 +480,27 @@
>static struct scsi_host_template ahci_platform_sht = {
> AHCI_SHT(DRV_NAME),
> };
>
>+static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv) {
>+ struct tegra_ahci_priv *tegra = hpriv->plat_data;
>+ u32 val;
>+
>+ if (tegra->soc_data->quirks & NO_DEVSLP) {
>+ val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
>+ val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
>+ writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
>+ } else if (tegra->soc_data->quirks & NO_DIPM) {
>+ ahci_tegra_port_info.flags |= ATA_FLAG_NO_DIPM;
>+ }
>+}
>+
> static int tegra_ahci_probe(struct platform_device *pdev) {
> struct ahci_host_priv *hpriv;
> struct tegra_ahci_priv *tegra;
> struct resource *res;
> int ret;
>+ unsigned int i;
>
> hpriv = ahci_platform_get_resources(pdev);
> if (IS_ERR(hpriv))
>@@ -311,13 +511,18 @@ static int tegra_ahci_probe(struct platform_device
>*pdev)
> return -ENOMEM;
>
> hpriv->plat_data = tegra;
>-
> tegra->pdev = pdev;
>+ tegra->soc_data =
>+ (struct tegra_ahci_soc *)of_device_get_match_data(&pdev->dev);
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(tegra->sata_regs))
> return PTR_ERR(tegra->sata_regs);
>+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>+ tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
>+ if (IS_ERR(tegra->sata_aux_regs))
>+ return PTR_ERR(tegra->sata_aux_regs);
>
> tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
> if (IS_ERR(tegra->sata_rst)) {
>@@ -343,13 +548,17 @@ static int tegra_ahci_probe(struct platform_device
>*pdev)
> return PTR_ERR(tegra->sata_clk);
> }
>
>- tegra->supplies[0].supply = "avdd";
>- tegra->supplies[1].supply = "hvdd";
>- tegra->supplies[2].supply = "vddio";
>- tegra->supplies[3].supply = "target-5v";
>- tegra->supplies[4].supply = "target-12v";
>+ tegra->supplies = devm_kcalloc(&pdev->dev,
>+ tegra->soc_data->num_supplies,
>+ sizeof(*tegra->supplies), GFP_KERNEL);
>+ if (!tegra->supplies)
>+ return -ENOMEM;
>+
>+ for (i = 0; i < tegra->soc_data->num_supplies; i++)
>+ tegra->supplies[i].supply = tegra->soc_data->supply_names[i];
>
>- ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra-
>>supplies),
>+ ret = devm_regulator_bulk_get(&pdev->dev,
>+ tegra->soc_data->num_supplies,
> tegra->supplies);
> if (ret) {
> dev_err(&pdev->dev, "Failed to get regulators\n"); @@ -385,5
>+594,5 @@ static struct platform_driver tegra_ahci_driver = {
>module_platform_driver(tegra_ahci_driver);
>
> MODULE_AUTHOR("Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>");
>-MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
>+MODULE_DESCRIPTION("Tegra AHCI SATA driver");
> MODULE_LICENSE("GPL v2");
>--
>2.1.4
^ permalink raw reply
* RE: [PATCH V3 2/3] dt-bindings: tegra: Add tegra210 AHCI
From: Preetham Chandru @ 2017-05-12 9:55 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Laxman Dewangan,
preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
Venu Byravarasu, Pavan Kunapuli,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1494581650-11115-3-git-send-email-pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
+CC linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>-----Original Message-----
>From: Preetham Chandru
>Sent: Friday, May 12, 2017 3:04 PM
>To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
>Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Laxman Dewangan
><ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; Venu Byravarasu
><vbyravarasu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Pavan Kunapuli <pkunapuli-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Preetham
>Chandru <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>Subject: [PATCH V3 2/3] dt-bindings: tegra: Add tegra210 AHCI
>
>From: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
>Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>---
>v3:
>* Add AUX register.
>v2:
>* change cml1, pll_e and phy regulators as optional
> for T210.
>---
> .../bindings/ata/nvidia,tegra124-ahci.txt | 45 +++++++++++++++-------
> 1 file changed, 31 insertions(+), 14 deletions(-)
>
>diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>index 66c83c3..dc62dba 100644
>--- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>+++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>@@ -1,32 +1,49 @@
>-Tegra124 SoC SATA AHCI controller
>+Tegra SoC SATA AHCI controller
>
> Required properties :
>-- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise,
>- must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
>- is tegra132.
>-- reg : Should contain 2 entries:
>+- compatible : Must be one of:
>+ - Tegra124 : "nvidia,tegra124-ahci"
>+ - Tegra210 : "nvidia,tegra210-ahci"
>+- reg : Should contain 3 entries:
> - AHCI register set (SATA BAR5)
> - SATA register set
>+ - AUX register set
> - interrupts : Defines the interrupt used by SATA
> - clocks : Must contain an entry for each entry in clock-names.
> See ../clocks/clock-bindings.txt for details.
> - clock-names : Must include the following entries:
> - sata
> - sata-oob
>- - cml1
>- - pll_e
> - resets : Must contain an entry for each entry in reset-names.
> See ../reset/reset.txt for details.
> - reset-names : Must include the following entries:
> - sata
> - sata-oob
>- - sata-cold
>+ - For T124: sata-cold
> - phys : Must contain an entry for each entry in phy-names.
> See ../phy/phy-bindings.txt for details.
> - phy-names : Must include the following entries:
>- - sata-phy : XUSB PADCTL SATA PHY
>-- hvdd-supply : Defines the SATA HVDD regulator
>-- vddio-supply : Defines the SATA VDDIO regulator
>-- avdd-supply : Defines the SATA AVDD regulator
>-- target-5v-supply : Defines the SATA 5V power regulator
>-- target-12v-supply : Defines the SATA 12V power regulator
>+ - For T124:
>+ - sata-phy : XUSB PADCTL SATA PHY
>+ - For T210:
>+ - sata-0
>+- For T124:
>+ - hvdd-supply : Defines the SATA HVDD regulator
>+ - vddio-supply : Defines the SATA VDDIO regulator
>+ - avdd-supply : Defines the SATA AVDD regulator
>+ - target-5v-supply : Defines the SATA 5V power regulator
>+
>+Optional properties:
>+- clock-names :
>+ - cml1 :
>+ cml1 clock is required by phy so it is optional to define
>+ here as phy driver will be enabling this clock.
>+ - pll_e :
>+ pll_e is the parent of cml1 clock so it is optional to define
>+ here as phy driver will be enabling this clock.
>+- For T210:
>+ - l0-hvddio-sata-supply : Defines the SATA HVDDIO regulator
>+ - l0-dvddio-sata-supply : Defines the SATA DVDDIO regulator
>+ - hvdd-pex-pll-e-supply : Defines the PEX PLL_E regulator
>+ - dvdd-sata-pll-supply : Defines the SATA PLL regulator
>+ - hvdd-sata-supply : Defines the SATA HVDD regulator
>--
>2.1.4
^ permalink raw reply
* RE: [PATCH V3 3/3] arm64: tegra: Enable SATA on Tegra210
From: Preetham Chandru @ 2017-05-12 9:56 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Laxman Dewangan,
preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
Venu Byravarasu, Pavan Kunapuli,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1494581650-11115-4-git-send-email-pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
+CC linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>-----Original Message-----
>From: Preetham Chandru
>Sent: Friday, May 12, 2017 3:04 PM
>To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
>Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Laxman Dewangan
><ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; Venu Byravarasu
><vbyravarasu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Pavan Kunapuli <pkunapuli-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Preetham
>Chandru <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>Subject: [PATCH V3 3/3] arm64: tegra: Enable SATA on Tegra210
>
>From: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
>Enable the SATA unit on Tegra210 systems.
>
>Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>---
> arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 6 ++++++
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 16 ++++++++++++++++
> 2 files changed, 22 insertions(+)
>
>diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
>b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
>index e5fc67b..58c28b9 100644
>--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
>+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
>@@ -1324,6 +1324,12 @@
> status = "okay";
> };
>
>+ sata@70020000 {
>+ status = "okay";
>+ phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
>+ phy-names = "sata-0";
>+ };
>+
> padctl@7009f000 {
> status = "okay";
>
>diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>index 8f26c4d..20c9160 100644
>--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>@@ -795,6 +795,22 @@
> #iommu-cells = <1>;
> };
>
>+ sata@70020000 {
>+ compatible = "nvidia,tegra210-ahci";
>+ reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
>+ <0x0 0x70020000 0x0 0x7000>, /* SATA */
>+ <0x0 0x70001100 0x0 0x1000>; /* SATA AUX*/
>+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
>+ clocks = <&tegra_car TEGRA210_CLK_SATA>,
>+ <&tegra_car TEGRA210_CLK_SATA_OOB>;
>+ clock-names = "sata", "sata-oob";
>+ resets = <&tegra_car 124>,
>+ <&tegra_car 123>,
>+ <&tegra_car 129>;
>+ reset-names = "sata", "sata-oob", "sata-cold";
>+ status = "disabled";
>+ };
>+
> hda@70030000 {
> compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
> reg = <0x0 0x70030000 0x0 0x10000>;
>--
>2.1.4
^ permalink raw reply
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* [PATCH 00/36] Convert DocBook documents to ReST
From: Mauro Carvalho Chehab @ 2017-05-12 13:59 UTC (permalink / raw)
To: linux-kernel, Linux Doc Mailing List
Cc: Andrew Lunn, alsa-devel, Takashi Iwai, Jan Kiszka,
Herton R. Krzesinski, Alexei Starovoitov, J. Bruce Fields,
linux-ide, Eric Dumazet, netdev, Jeff Layton, Jan Kara,
Soheil Hassas Yeganeh, linux-s390, Florian Fainelli,
James E.J. Bottomley, Herbert Xu, linux-scsi, Jonathan Corbet,
Ursula Braun, Rafael J. Wysocki, Mauro Carvalho Chehab,
Peter Zijlstra, Julian Anastasov, Ingo
This patch series convert the following books from
DocBook to ReST:
- filesystems
- kernel-hacking
- kernel-locking
- kgdb
- libata
- networking
- rapidio
- s390-drivers
- scsi
- w1
- z8530book
It also adjusts some Sphinx-pedantic errors/warnings on
some kernel-doc markups.
I also added some patches here to add PDF output for all
existing ReST books.
I did my best to check if what's there is not too outdated, but
the best is if the subsystem maintainers could check it.
After this series, there are only 4 DocBook remaining conversion:
- librs
- lsm
- mtdnand
- sh
I'll likely convert those remaining ones during this weekend.
-
This patch series is based on docs tree (next branch).
The full patch series is on this tree:
https://git.linuxtv.org//mchehab/experimental.git/log/?h=docbook
And the HTML output at:
http://www.infradead.org/~mchehab/kernel_docs/
https://mchehab.fedorapeople.org/kernel_docs/
Mauro Carvalho Chehab (36):
docs-rst: convert kernel-hacking to ReST
kernel-hacking: update document
docs-rst: convert kernel-locking to ReST
mutex, futex: adjust kernel-doc markups to generate ReST
locking.rst: reformat locking table
locking.rst: add captions to two tables
locking.rst: Update some ReST markups
docs-rst: convert kgdb DocBook to ReST
kgdb.rst: Adjust ReST markups
conf.py: define a color for important markup on PDF output
docs-rst: conf.py: sort LaTeX documents in alphabetical order
docs-rst: conf.py: remove kernel-documentation from LaTeX
docs-rst: add crypto API book to pdf output
docs-rst: add dev-tools book to pdf output
docs-rst: add sound book to pdf output
docs-rst: add userspace API book to pdf output
docs-rst: convert filesystems book to ReST
docs-rst: filesystems: use c domain references where needed
fs: jbd2: make jbd2_journal_start() kernel-doc parseable
docs-rst: don't ignore internal functions for jbd2 docs
fs: locks: Fix some troubles at kernel-doc comments
fs: add a blank lines on some kernel-doc comments
fs: eventfd: fix identation on kernel-doc
fs: jbd2: escape a string with special chars on a kernel-doc
docs-rst: convert libata book to ReST
libata.rst: add c function and struct cross-references
libata: fix identation on a kernel-doc markup
docs-rst: convert s390-drivers DocBook to ReST
docs-rst: convert networking book to ReST
net: skbuff.h: properly escape a macro name on kernel-doc
net: fix some identation issues at kernel-doc markups
docs-rst: convert z8530book DocBook to ReST
docs-rst: convert scsi DocBook to ReST
scsi: fix some kernel-doc markups
docs-rst: convert w1 book to ReST
docs-rst: convert rapidio book to ReST
Documentation/DocBook/Makefile | 11 +-
Documentation/DocBook/filesystems.tmpl | 381 -----
Documentation/DocBook/kernel-hacking.tmpl | 1312 ------------------
Documentation/DocBook/kernel-locking.tmpl | 2151 -----------------------------
Documentation/DocBook/kgdb.tmpl | 918 ------------
Documentation/DocBook/libata.tmpl | 1625 ----------------------
Documentation/DocBook/networking.tmpl | 111 --
Documentation/DocBook/rapidio.tmpl | 155 ---
Documentation/DocBook/s390-drivers.tmpl | 161 ---
Documentation/DocBook/scsi.tmpl | 409 ------
Documentation/DocBook/w1.tmpl | 101 --
Documentation/DocBook/z8530book.tmpl | 371 -----
Documentation/conf.py | 35 +-
Documentation/crypto/conf.py | 10 +
Documentation/dev-tools/index.rst | 1 +
Documentation/dev-tools/kgdb.rst | 907 ++++++++++++
Documentation/driver-api/index.rst | 5 +
Documentation/driver-api/libata.rst | 1031 ++++++++++++++
Documentation/driver-api/rapidio.rst | 107 ++
Documentation/driver-api/s390-drivers.rst | 111 ++
Documentation/driver-api/scsi.rst | 344 +++++
Documentation/driver-api/w1.rst | 70 +
Documentation/filesystems/conf.py | 10 +
Documentation/filesystems/index.rst | 317 +++++
Documentation/index.rst | 3 +
Documentation/kernel-hacking/conf.py | 10 +
Documentation/kernel-hacking/hacking.rst | 811 +++++++++++
Documentation/kernel-hacking/index.rst | 5 +
Documentation/kernel-hacking/locking.rst | 1446 +++++++++++++++++++
Documentation/networking/conf.py | 10 +
Documentation/networking/index.rst | 18 +
Documentation/networking/kapi.rst | 147 ++
Documentation/networking/z8530book.rst | 256 ++++
Documentation/sound/conf.py | 10 +
drivers/ata/libata-scsi.c | 7 +-
drivers/net/phy/phy.c | 1 +
drivers/scsi/scsi_scan.c | 7 +-
drivers/scsi/scsi_transport_fc.c | 18 +-
drivers/scsi/scsicam.c | 4 +-
fs/eventfd.c | 4 +-
fs/fs-writeback.c | 12 +-
fs/jbd2/transaction.c | 42 +-
fs/locks.c | 18 +-
fs/mpage.c | 1 +
fs/namei.c | 1 +
include/linux/mutex.h | 6 +-
include/linux/netdevice.h | 9 +-
include/linux/skbuff.h | 2 +-
include/net/sock.h | 9 +-
kernel/futex.c | 40 +-
kernel/locking/mutex.c | 6 +-
net/core/datagram.c | 2 +-
net/core/sock.c | 7 +-
53 files changed, 5764 insertions(+), 7802 deletions(-)
delete mode 100644 Documentation/DocBook/filesystems.tmpl
delete mode 100644 Documentation/DocBook/kernel-hacking.tmpl
delete mode 100644 Documentation/DocBook/kernel-locking.tmpl
delete mode 100644 Documentation/DocBook/kgdb.tmpl
delete mode 100644 Documentation/DocBook/libata.tmpl
delete mode 100644 Documentation/DocBook/networking.tmpl
delete mode 100644 Documentation/DocBook/rapidio.tmpl
delete mode 100644 Documentation/DocBook/s390-drivers.tmpl
delete mode 100644 Documentation/DocBook/scsi.tmpl
delete mode 100644 Documentation/DocBook/w1.tmpl
delete mode 100644 Documentation/DocBook/z8530book.tmpl
create mode 100644 Documentation/crypto/conf.py
create mode 100644 Documentation/dev-tools/kgdb.rst
create mode 100644 Documentation/driver-api/libata.rst
create mode 100644 Documentation/driver-api/rapidio.rst
create mode 100644 Documentation/driver-api/s390-drivers.rst
create mode 100644 Documentation/driver-api/scsi.rst
create mode 100644 Documentation/driver-api/w1.rst
create mode 100644 Documentation/filesystems/conf.py
create mode 100644 Documentation/filesystems/index.rst
create mode 100644 Documentation/kernel-hacking/conf.py
create mode 100644 Documentation/kernel-hacking/hacking.rst
create mode 100644 Documentation/kernel-hacking/index.rst
create mode 100644 Documentation/kernel-hacking/locking.rst
create mode 100644 Documentation/networking/conf.py
create mode 100644 Documentation/networking/index.rst
create mode 100644 Documentation/networking/kapi.rst
create mode 100644 Documentation/networking/z8530book.rst
create mode 100644 Documentation/sound/conf.py
--
2.9.3
^ permalink raw reply
* [PATCH 27/36] libata: fix identation on a kernel-doc markup
From: Mauro Carvalho Chehab @ 2017-05-12 14:00 UTC (permalink / raw)
To: linux-kernel, Linux Doc Mailing List
Cc: Mauro Carvalho Chehab, Mauro Carvalho Chehab, Tejun Heo,
linux-ide
In-Reply-To: <cover.1494596071.git.mchehab@s-opensource.com>
Sphinx got confused with the markup identation:
./drivers/ata/libata-scsi.c:3402: ERROR: Unexpected indentation.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
---
drivers/ata/libata-scsi.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index 49ba9834c715..dcd38d9e9804 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -3398,9 +3398,10 @@ static size_t ata_format_dsm_trim_descr(struct scsi_cmnd *cmd, u32 trmax,
*
* Translate a SCSI WRITE SAME command to be either a DSM TRIM command or
* an SCT Write Same command.
- * Based on WRITE SAME has the UNMAP flag
- * When set translate to DSM TRIM
- * When clear translate to SCT Write Same
+ * Based on WRITE SAME has the UNMAP flag:
+ *
+ * - When set translate to DSM TRIM
+ * - When clear translate to SCT Write Same
*/
static unsigned int ata_scsi_write_same_xlat(struct ata_queued_cmd *qc)
{
--
2.9.3
^ permalink raw reply related
* Re: [PATCH 1/4] ata: Add DT bindings for Faraday Technology FTIDE010
From: Rob Herring @ 2017-05-12 15:24 UTC (permalink / raw)
To: Linus Walleij
Cc: Tejun Heo, Bartlomiej Zolnierkiewicz,
linux-ide-u79uwXL29TY76Z2rM5mHXA, Janos Laube, Paulius Zaleckas,
openwrt-devel-p3rKhJxN3npAfugRpC6u6w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Hans Ulli Kroll, Florian Fainelli,
devicetree-u79uwXL29TY76Z2rM5mHXA, John Feng-Hsin Chiang,
Greentime Hu
In-Reply-To: <20170506121053.11554-1-linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Sat, May 06, 2017 at 02:10:50PM +0200, Linus Walleij wrote:
> This adds device tree bindings for the Faraday Technology
> FTIDE010 found in the Storlink/Storm/Cortina Systems Gemini SoC.
>
> I am not 100% sure that this part if from Faraday Technology but
s/if/is/
> a lot points in that direction:
>
> - A later IDE interface called FTIDE020 exist and share some
> properties.
>
> - The SATA bridge has the same Built In Self Test (BIST) that the
> Faraday FTSATA100 seems to have, and it has version number 0100
> in the device ID register, so this is very likely a FTSATA100
> bundled with the FTIDE010.
>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: John Feng-Hsin Chiang <john453-w0jeGXs5+AWXmMXjJBpWqg@public.gmane.org>
> Cc: Greentime Hu <green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> Greentime: I think this may be interesting to you since the
> FTIDE020 will need the same bindings so we can probably
> just reuse them and maybe make the parser a library if you
> want to upstream the FTIDE020.
>
> Faraday people: I do not have it from a source that this
> hardware is really FTIDE010 but I would be VERY surprised
> if it is not. U-Boot has an FTIDE020 IDE controller
> synthesized in the Andestech platform, and it has a similar
> yet different register layout, featuring similar timing
> set-ups:
> http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/block/ftide020.h
> http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/block/ftide020.c
> ---
> .../devicetree/bindings/ata/faraday,ftide010.txt | 63 ++++++++++++++++++++++
> 1 file changed, 63 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ata/faraday,ftide010.txt
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
--
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^ permalink raw reply
* Re: [PATCH 2/4] ata: Add DT bindings for the Gemini SATA bridge
From: Rob Herring @ 2017-05-12 15:30 UTC (permalink / raw)
To: Linus Walleij
Cc: Tejun Heo, Bartlomiej Zolnierkiewicz,
linux-ide-u79uwXL29TY76Z2rM5mHXA, Janos Laube, Paulius Zaleckas,
openwrt-devel-p3rKhJxN3npAfugRpC6u6w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Hans Ulli Kroll, Florian Fainelli,
devicetree-u79uwXL29TY76Z2rM5mHXA, John Feng-Hsin Chiang,
Greentime Hu
In-Reply-To: <20170506121053.11554-2-linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Sat, May 06, 2017 at 02:10:51PM +0200, Linus Walleij wrote:
> This adds device tree bindings for the Cortina Systems Gemini
> PATA to SATA bridge.
>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: John Feng-Hsin Chiang <john453-w0jeGXs5+AWXmMXjJBpWqg@public.gmane.org>
> Cc: Greentime Hu <green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> .../bindings/ata/cortina,gemini-sata-bridge.txt | 55 ++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH V3 1/3] ata: ahci_tegra: Add AHCI support for tegra210
From: Mikko Perttunen @ 2017-05-14 11:18 UTC (permalink / raw)
To: Preetham Chandru,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Laxman Dewangan,
preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
Venu Byravarasu, Pavan Kunapuli,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <c3457c8e12b0402293bdea825883277f-7W72rfoJkVnYuxH7O460wFaTQe2KTcn/@public.gmane.org>
On 05/12/2017 12:55 PM, Preetham Chandru wrote:
> +CC linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>
>> -----Original Message-----
>> From: Preetham Chandru
>> Sent: Friday, May 12, 2017 3:04 PM
>> To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
>> Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Laxman Dewangan
>> <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; Venu Byravarasu
>> <vbyravarasu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Pavan Kunapuli <pkunapuli-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Preetham
>> Chandru <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> Subject: [PATCH V3 1/3] ata: ahci_tegra: Add AHCI support for tegra210
>>
>> From: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> 1. Move tegra124 specifics to tegra124_ahci_init.
>> 2. Separate the regulators needed for tegra124 and tegra210.
>> 3. Disable DIPM and Devslp for t210 and t124 as there are known issues
>>
>> Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> v3:
>> * Remove inline functions for read/write and modify to
>> SATA, SATA Config and SATA Aux registers.
>> * Add code to disable DIPM and DevSlp for t210 and t124
>> v2:
>> * Fix indentation issues
>> * Move the change to disable DIPM, HIPM, DevSlp, partial,
>> slumber and NCQ into a separate patch
>> ---
>> drivers/ata/ahci_tegra.c | 377 ++++++++++++++++++++++++++++++++++++-------
>> ----
>> 1 file changed, 293 insertions(+), 84 deletions(-)
>>
>> diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c index
>> 3a62eb2..cd581a6 100644
>> --- a/drivers/ata/ahci_tegra.c
>> +++ b/drivers/ata/ahci_tegra.c
>> @@ -34,7 +34,8 @@
>> #define DRV_NAME "tegra-ahci"
>>
>> #define SATA_CONFIGURATION_0 0x180
>> -#define SATA_CONFIGURATION_EN_FPCI BIT(0)
>> +#define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
>> +#define SATA_CONFIGURATION_0_CLK_OVERRIDE BIT(31)
>>
>> #define SCFG_OFFSET 0x1000
>>
>> @@ -45,17 +46,55 @@
>> #define T_SATA0_CFG_1_SERR BIT(8)
>>
>> #define T_SATA0_CFG_9 0x24
>> -#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13
>> +#define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000
>>
>> #define SATA_FPCI_BAR5 0x94
>> -#define SATA_FPCI_BAR5_START_SHIFT 4
>> +#define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4)
>> +#define SATA_FPCI_BAR5_START (0x0040020 <<
>> 4)
>> +#define SATA_FPCI_BAR5_ACCESS_TYPE (0x1)
>>
>> #define SATA_INTR_MASK 0x188
>> #define SATA_INTR_MASK_IP_INT_MASK BIT(16)
>>
>> +#define T_SATA0_CFG_35 0x94
>> +#define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2)
>> +#define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2)
>> +
>> +#define T_SATA0_AHCI_IDP1 0x98
>> +#define T_SATA0_AHCI_IDP1_DATA (0x400040)
>> +
>> +#define T_SATA0_CFG_PHY_1 0x12c
>> +#define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23)
>> +#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22)
>> +
>> +#define T_SATA0_NVOOB 0x114
>> +#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
>> +#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
>> +#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
>> +#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
>> +#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
>> +#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
>> +
>> +#define T_SATA_CFG_PHY_0 0x120
>> +#define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11)
>> +#define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24)
>> +
>> +#define T_SATA0_CFG2NVOOB_2 0x134
>> +#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff
>> << 18)
>> +#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
>> +
>> #define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
>> +#define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13)
>> +#define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14)
>> +#define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26)
>> +#define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17)
>> +#define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30)
>>
>> #define T_SATA0_BKDOOR_CC 0x4a4
>> +#define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16)
>> +#define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
>> +#define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8)
>> +#define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8)
>>
>> #define T_SATA0_CFG_SATA 0x54c
>> #define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
>> @@ -82,9 +121,35 @@
>> #define T_SATA0_CHX_PHY_CTRL11 0x6d0
>> #define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
>>
>> +#define T_SATA0_CHX_PHY_CTRL17_0 0x6e8
>> +#define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000
>> +#define T_SATA0_CHX_PHY_CTRL18_0 0x6ec
>> +#define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000
>> +#define T_SATA0_CHX_PHY_CTRL20_0 0x6f4
>> +#define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1
>> +#define T_SATA0_CHX_PHY_CTRL21_0 0x6f8
>> +#define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1
>> +
>> +/* AUX Registers */
>> +#define SATA_AUX_MISC_CNTL_1_0 0x8
>> +#define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE BIT(17)
>> +#define SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT BIT(13)
>> +#define SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT BIT(15)
>> +
>> +#define SATA_AUX_RX_STAT_INT_0 0xc
>> +#define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP BIT(7)
>> +
>> +#define SATA_AUX_SPARE_CFG0_0 0x18
>> +#define SATA_AUX_SPARE_CFG0_0_MDAT_TIMER_AFTER_PG_VALID BIT(14)
>> +
>> #define FUSE_SATA_CALIB 0x124
>> #define FUSE_SATA_CALIB_MASK 0x3
>>
>> +enum {
>> + NO_DEVSLP = (1 << 0),
>> + NO_DIPM = (1 << 1),
>> +};
>> +
>> struct sata_pad_calibration {
>> u8 gen1_tx_amp;
>> u8 gen1_tx_peak;
>> @@ -99,15 +164,89 @@ static const struct sata_pad_calibration
>> tegra124_pad_calibration[] = {
>> {0x14, 0x0e, 0x1a, 0x0e},
>> };
>>
>> +struct tegra_ahci_ops {
>> + int (*init)(struct ahci_host_priv *);
>> +};
>> +
>> +struct tegra_ahci_soc {
>> + const char *const *supply_names;
>> + u32 num_supplies;
>> + u32 quirks;
>> + struct tegra_ahci_ops ops;
>> +};
>> +
>> struct tegra_ahci_priv {
>> struct platform_device *pdev;
>> void __iomem *sata_regs;
>> + void __iomem *sata_aux_regs;
>> struct reset_control *sata_rst;
>> struct reset_control *sata_oob_rst;
>> struct reset_control *sata_cold_rst;
>> /* Needs special handling, cannot use ahci_platform */
>> struct clk *sata_clk;
>> - struct regulator_bulk_data supplies[5];
>> + struct regulator_bulk_data *supplies;
>> + struct tegra_ahci_soc *soc_data;
>> +};
>> +
>> +static const char *const tegra124_supply_names[] = {
>> + "avdd", "hvdd", "vddio", "target-5v", "target-12v"
>> +};
>> +
>> +static int tegra124_ahci_init(struct ahci_host_priv *hpriv) {
>> + struct tegra_ahci_priv *tegra = hpriv->plat_data;
>> + struct sata_pad_calibration calib;
>> + int ret;
>> + u32 val;
>> +
>> + /* Pad calibration */
>> + ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
>> + if (ret)
>> + return ret;
>> +
>> + calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
>> +
>> + writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
>> +
>> + val = readl(tegra->sata_regs +
>> + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
>> + val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
>> + val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
>> + val |= calib.gen1_tx_amp <<
>> T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
>> + val |= calib.gen1_tx_peak <<
>> T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
>> + writel(val, tegra->sata_regs + SCFG_OFFSET +
>> + T_SATA0_CHX_PHY_CTRL1_GEN1);
>> +
>> + val = readl(tegra->sata_regs +
>> + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
>> + val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
>> + val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
>> + val |= calib.gen2_tx_amp <<
>> T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
>> + val |= calib.gen2_tx_peak <<
>> T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
>> + writel(val, tegra->sata_regs + SCFG_OFFSET +
>> + T_SATA0_CHX_PHY_CTRL1_GEN2);
>> +
>> + writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
>> + tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
>> + writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
>> + tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
>> +
>> + writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct tegra_ahci_soc tegra124_ahci_soc_data = {
>> + .supply_names = tegra124_supply_names,
>> + .num_supplies = ARRAY_SIZE(tegra124_supply_names),
>> + .quirks = NO_DIPM | NO_DEVSLP,
>> + .ops = {
>> + .init = tegra124_ahci_init,
>> + },
Indent this "}," one tab less (i.e. to same level as '.ops')
>> +};
>> +
>> +static const struct tegra_ahci_soc tegra210_ahci_soc_data = {
>> + .quirks = NO_DIPM | NO_DEVSLP,
>> };
>>
>> static int tegra_ahci_power_on(struct ahci_host_priv *hpriv) @@ -115,7 +254,7
>> @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
>> struct tegra_ahci_priv *tegra = hpriv->plat_data;
>> int ret;
>>
>> - ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
>> + ret = regulator_bulk_enable(tegra->soc_data->num_supplies,
>> tegra->supplies);
>> if (ret)
>> return ret;
>> @@ -144,8 +283,7 @@ static int tegra_ahci_power_on(struct ahci_host_priv
>> *hpriv)
>> tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
>>
>> disable_regulators:
>> - regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
>> -
>> + regulator_bulk_disable(tegra->soc_data->num_supplies,
>> +tegra->supplies);
Indent this.
>> return ret;
>> }
>>
>> @@ -162,97 +300,137 @@ static void tegra_ahci_power_off(struct
>> ahci_host_priv *hpriv)
>> clk_disable_unprepare(tegra->sata_clk);
>> tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
>>
>> - regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
>> + regulator_bulk_disable(tegra->soc_data->num_supplies,
>> +tegra->supplies);
And this
>> }
>>
>> static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv) {
>> struct tegra_ahci_priv *tegra = hpriv->plat_data;
>> int ret;
>> - unsigned int val;
>> - struct sata_pad_calibration calib;
>> + u32 val;
>>
>> ret = tegra_ahci_power_on(hpriv);
>> - if (ret) {
>> - dev_err(&tegra->pdev->dev,
>> - "failed to power on AHCI controller: %d\n", ret);
>> + if (ret)
>> return ret;
>> - }
>>
>> + /*
>> + * Program the following SATA IPFS registers
Extra space between "following" and "SATA"
>> + * to allow SW accesses to SATA's MMIO Register
Perhaps say "register range"
>> + */
>> + val = readl(tegra->sata_regs + SATA_FPCI_BAR5);
>> + val &= ~(SATA_FPCI_BAR5_START_MASK |
>> SATA_FPCI_BAR5_ACCESS_TYPE);
>> + val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE;
>> + writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
>> +
>> + /* Program the following SATA IPFS register to enable the SATA */
>> val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
>> - val |= SATA_CONFIGURATION_EN_FPCI;
>> + val |= SATA_CONFIGURATION_0_EN_FPCI;
>> writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
>>
>> - /* Pad calibration */
>> -
>> - ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
>> - if (ret) {
>> - dev_err(&tegra->pdev->dev,
>> - "failed to read calibration fuse: %d\n", ret);
>> - return ret;
>> - }
>> -
>> - calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
>> -
>> - writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
>> -
>> - val = readl(tegra->sata_regs +
>> - SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
>> - val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
>> - val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
>> - val |= calib.gen1_tx_amp <<
>> - T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
>> - val |= calib.gen1_tx_peak <<
>> - T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
>> - writel(val, tegra->sata_regs + SCFG_OFFSET +
>> - T_SATA0_CHX_PHY_CTRL1_GEN1);
>> -
>> - val = readl(tegra->sata_regs +
>> - SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
>> - val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
>> - val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
>> - val |= calib.gen2_tx_amp <<
>> - T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
>> - val |= calib.gen2_tx_peak <<
>> - T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
>> - writel(val, tegra->sata_regs + SCFG_OFFSET +
>> - T_SATA0_CHX_PHY_CTRL1_GEN2);
>> -
>> - writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
>> - tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
>> - writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
>> - tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
>> -
>> - writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
>> -
>> - /* Program controller device ID */
>> + /* Electrical settings for better link stability */
>> + val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1;
>> + writel(val, tegra->sata_regs + SCFG_OFFSET +
>> T_SATA0_CHX_PHY_CTRL17_0);
>> + val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2;
>> + writel(val, tegra->sata_regs + SCFG_OFFSET +
>> T_SATA0_CHX_PHY_CTRL18_0);
>> + val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1;
>> + writel(val, tegra->sata_regs + SCFG_OFFSET +
>> T_SATA0_CHX_PHY_CTRL20_0);
>> + val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2;
>> + writel(val, tegra->sata_regs + SCFG_OFFSET +
>> +T_SATA0_CHX_PHY_CTRL21_0);
Indent
>> +
>> + /* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */
>> +
>> + val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
>> + val |= T_SATA_CFG_PHY_0_MASK_SQUELCH;
>> + val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
>> + writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
>> +
>> + val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
>> + val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK |
>> + T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
>> + T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
>> + val |= (T_SATA0_NVOOB_COMMA_CNT |
>> + T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
>> + T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
>> + writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
>> +
>> + /*
>> + * Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to
>> 58.8ns
>> + */
>> + val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
>> + val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
>> + val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
>> + writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
>> +
>> + if (tegra->soc_data->ops.init)
>> + tegra->soc_data->ops.init(hpriv);
>> +
>> + /*
>> + * Program the following SATA configuration registers
>> + * to initialize SATA
>> + */
>> + val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
>> + val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
>> + T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR);
>> + writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
>> + val = T_SATA0_CFG_9_BASE_ADDRESS;
>> + writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
>>
>> + /* Program Class Code and Programming interface for SATA */
>> val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
>> val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
>> writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
>>
>> - writel(0x01060100, tegra->sata_regs + SCFG_OFFSET +
>> T_SATA0_BKDOOR_CC);
>> + val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
>> + val &=
>> + ~(T_SATA0_BKDOOR_CC_CLASS_CODE_MASK |
>> + T_SATA0_BKDOOR_CC_PROG_IF_MASK);
>> + val |= T_SATA0_BKDOOR_CC_CLASS_CODE |
>> T_SATA0_BKDOOR_CC_PROG_IF;
>> + writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
>>
>> val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
>> val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
>> writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
>>
>> - /* Enable IO & memory access, bus master mode */
>> -
>> - val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
>> - val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
>> - T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR;
>> - writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
>> -
>> - /* Program SATA MMIO */
>> -
>> - writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
>> - tegra->sata_regs + SATA_FPCI_BAR5);
>> -
>> - writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
>> - tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
>> + /* Enabling LPM capabilities through Backdoor Programming */
>> + val = readl(tegra->sata_regs + SCFG_OFFSET +
>> T_SATA0_AHCI_HBA_CAP_BKDR);
>> + val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
>> + T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
>> + T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
>> + T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM);
>> + writel(val, tegra->sata_regs + SCFG_OFFSET +
>> +T_SATA0_AHCI_HBA_CAP_BKDR);
>> +
>> + /* SATA Second Level Clock Gating configuration
>> + * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane
>> + * IDDQ Signals
>> + */
>> + val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
>> + val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
>> + val |= T_SATA0_CFG_35_IDP_INDEX;
>> + writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
>> +
>> + val = T_SATA0_AHCI_IDP1_DATA;
>> + writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
>> +
>> + val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
>> + val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
>> + T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN);
>> + writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
>> +
>> + /*
>> + * Indicate Sata only has the capability to enter DevSleep
Stray space in front
>> + * from slumber link.
>> + */
>> +
>> + val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
>> + val |= SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT;
>> + writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
>> +
>> + /* Enabling IPFS Clock Gating */
>> + val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
>> + val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
>> + writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
>>
>> - /* Unmask SATA interrupts */
>> + tegra_ahci_handle_quirks(hpriv);
>>
>> val = readl(tegra->sata_regs + SATA_INTR_MASK);
>> val |= SATA_INTR_MASK_IP_INT_MASK;
>> @@ -278,7 +456,7 @@ static struct ata_port_operations ahci_tegra_port_ops =
>> {
>> .host_stop = tegra_ahci_host_stop,
>> };
>>
>> -static const struct ata_port_info ahci_tegra_port_info = {
>> +static struct ata_port_info ahci_tegra_port_info = {
>> .flags = AHCI_FLAG_COMMON,
>> .pio_mask = ATA_PIO4,
>> .udma_mask = ATA_UDMA6,
>> @@ -286,7 +464,14 @@ static const struct ata_port_info ahci_tegra_port_info =
>> { };
>>
>> static const struct of_device_id tegra_ahci_of_match[] = {
>> - { .compatible = "nvidia,tegra124-ahci" },
>> + {
>> + .compatible = "nvidia,tegra124-ahci",
>> + .data = &tegra124_ahci_soc_data
>> + },
>> + {
>> + .compatible = "nvidia,tegra210-ahci",
>> + .data = &tegra210_ahci_soc_data
>> + },
>> {}
>> };
>> MODULE_DEVICE_TABLE(of, tegra_ahci_of_match); @@ -295,12 +480,27 @@
>> static struct scsi_host_template ahci_platform_sht = {
>> AHCI_SHT(DRV_NAME),
>> };
>>
>> +static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv) {
>> + struct tegra_ahci_priv *tegra = hpriv->plat_data;
>> + u32 val;
>> +
>> + if (tegra->soc_data->quirks & NO_DEVSLP) {
>> + val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
>> + val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
>> + writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
>> + } else if (tegra->soc_data->quirks & NO_DIPM) {
I don't think this should be 'else if', but just two separate regular 'if's?
>> + ahci_tegra_port_info.flags |= ATA_FLAG_NO_DIPM;
Looking at the downstream device trees, it looks like DIPM and DEVSLP
are still disabled for Tegra186 - so why don't we just hardcode these
quirks, by always writing the MISC_CNTL_1_0 register and just adding
ATA_FLAG_NO_DIPM to ahci_tegra_port_info's static definition.
>> + }
>> +}
>> +
>> static int tegra_ahci_probe(struct platform_device *pdev) {
>> struct ahci_host_priv *hpriv;
>> struct tegra_ahci_priv *tegra;
>> struct resource *res;
>> int ret;
>> + unsigned int i;
>>
>> hpriv = ahci_platform_get_resources(pdev);
>> if (IS_ERR(hpriv))
>> @@ -311,13 +511,18 @@ static int tegra_ahci_probe(struct platform_device
>> *pdev)
>> return -ENOMEM;
>>
>> hpriv->plat_data = tegra;
>> -
>> tegra->pdev = pdev;
>> + tegra->soc_data =
>> + (struct tegra_ahci_soc *)of_device_get_match_data(&pdev->dev);
>>
>> res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>> tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
>> if (IS_ERR(tegra->sata_regs))
>> return PTR_ERR(tegra->sata_regs);
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>> + tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(tegra->sata_aux_regs))
>> + return PTR_ERR(tegra->sata_aux_regs);
Requiring aux_regs would break backwards compatibility for Tegra124
device trees. We will have to keep aux_regs optional for Tegra124, and
skip writes to them if they are not available.
>>
>> tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
>> if (IS_ERR(tegra->sata_rst)) {
>> @@ -343,13 +548,17 @@ static int tegra_ahci_probe(struct platform_device
>> *pdev)
>> return PTR_ERR(tegra->sata_clk);
>> }
>>
>> - tegra->supplies[0].supply = "avdd";
>> - tegra->supplies[1].supply = "hvdd";
>> - tegra->supplies[2].supply = "vddio";
>> - tegra->supplies[3].supply = "target-5v";
>> - tegra->supplies[4].supply = "target-12v";
>> + tegra->supplies = devm_kcalloc(&pdev->dev,
>> + tegra->soc_data->num_supplies,
>> + sizeof(*tegra->supplies), GFP_KERNEL);
>> + if (!tegra->supplies)
>> + return -ENOMEM;
>> +
>> + for (i = 0; i < tegra->soc_data->num_supplies; i++)
>> + tegra->supplies[i].supply = tegra->soc_data->supply_names[i];
>>
>> - ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra-
>>> supplies),
>> + ret = devm_regulator_bulk_get(&pdev->dev,
>> + tegra->soc_data->num_supplies,
>> tegra->supplies);
>> if (ret) {
>> dev_err(&pdev->dev, "Failed to get regulators\n"); @@ -385,5
>> +594,5 @@ static struct platform_driver tegra_ahci_driver = {
>> module_platform_driver(tegra_ahci_driver);
>>
>> MODULE_AUTHOR("Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>");
>> -MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
>> +MODULE_DESCRIPTION("Tegra AHCI SATA driver");
>> MODULE_LICENSE("GPL v2");
>> --
>> 2.1.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
Thanks for posting!
Mikko
^ permalink raw reply
* Re: [PATCH V3 2/3] dt-bindings: tegra: Add tegra210 AHCI
From: Mikko Perttunen @ 2017-05-14 11:26 UTC (permalink / raw)
To: Preetham Chandru,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Laxman Dewangan,
preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
Venu Byravarasu, Pavan Kunapuli,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <66578c4b5f77447aa6c4e3c7ce0cf8db-7W72rfoJkVnYuxH7O460wFaTQe2KTcn/@public.gmane.org>
On 05/12/2017 12:55 PM, Preetham Chandru wrote:
> +CC linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>
>> -----Original Message-----
>> From: Preetham Chandru
>> Sent: Friday, May 12, 2017 3:04 PM
>> To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
>> Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Laxman Dewangan
>> <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; Venu Byravarasu
>> <vbyravarasu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Pavan Kunapuli <pkunapuli-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Preetham
>> Chandru <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> Subject: [PATCH V3 2/3] dt-bindings: tegra: Add tegra210 AHCI
>>
>> From: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
This needs a commit message. Something simple, like "This adds bindings
documentation for the AHCI controller on Tegra210." is fine.
>> Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> v3:
>> * Add AUX register.
>> v2:
>> * change cml1, pll_e and phy regulators as optional
>> for T210.
>> ---
>> .../bindings/ata/nvidia,tegra124-ahci.txt | 45 +++++++++++++++-------
>> 1 file changed, 31 insertions(+), 14 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> index 66c83c3..dc62dba 100644
>> --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
>> @@ -1,32 +1,49 @@
>> -Tegra124 SoC SATA AHCI controller
>> +Tegra SoC SATA AHCI controller
>>
>> Required properties :
>> -- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise,
>> - must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
>> - is tegra132.
>> -- reg : Should contain 2 entries:
>> +- compatible : Must be one of:
>> + - Tegra124 : "nvidia,tegra124-ahci"
>> + - Tegra210 : "nvidia,tegra210-ahci"
>> +- reg : Should contain 3 entries:
>> - AHCI register set (SATA BAR5)
>> - SATA register set
>> + - AUX register set
The AUX register set must be optional on Tegra124, as it was not
required previously.
>> - interrupts : Defines the interrupt used by SATA
>> - clocks : Must contain an entry for each entry in clock-names.
>> See ../clocks/clock-bindings.txt for details.
>> - clock-names : Must include the following entries:
>> - sata
>> - sata-oob
>> - - cml1
>> - - pll_e
>> - resets : Must contain an entry for each entry in reset-names.
>> See ../reset/reset.txt for details.
>> - reset-names : Must include the following entries:
>> - sata
>> - sata-oob
>> - - sata-cold
>> + - For T124: sata-cold
>> - phys : Must contain an entry for each entry in phy-names.
>> See ../phy/phy-bindings.txt for details.
>> - phy-names : Must include the following entries:
>> - - sata-phy : XUSB PADCTL SATA PHY
>> -- hvdd-supply : Defines the SATA HVDD regulator
>> -- vddio-supply : Defines the SATA VDDIO regulator
>> -- avdd-supply : Defines the SATA AVDD regulator
>> -- target-5v-supply : Defines the SATA 5V power regulator
>> -- target-12v-supply : Defines the SATA 12V power regulator
>> + - For T124:
>> + - sata-phy : XUSB PADCTL SATA PHY
>> + - For T210:
>> + - sata-0
>> +- For T124:
>> + - hvdd-supply : Defines the SATA HVDD regulator
>> + - vddio-supply : Defines the SATA VDDIO regulator
>> + - avdd-supply : Defines the SATA AVDD regulator
>> + - target-5v-supply : Defines the SATA 5V power regulator
This is missing the 12V supply regulator
>> +
>> +Optional properties:
>> +- clock-names :
>> + - cml1 :
>> + cml1 clock is required by phy so it is optional to define
>> + here as phy driver will be enabling this clock.
>> + - pll_e :
>> + pll_e is the parent of cml1 clock so it is optional to define
>> + here as phy driver will be enabling this clock.
>> +- For T210:
>> + - l0-hvddio-sata-supply : Defines the SATA HVDDIO regulator
>> + - l0-dvddio-sata-supply : Defines the SATA DVDDIO regulator
>> + - hvdd-pex-pll-e-supply : Defines the PEX PLL_E regulator
>> + - dvdd-sata-pll-supply : Defines the SATA PLL regulator
>> + - hvdd-sata-supply : Defines the SATA HVDD regulator
I don't think the driver currently has code to enable these regulators?
>> --
>> 2.1.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* Re: [PATCH V3 3/3] arm64: tegra: Enable SATA on Tegra210
From: Mikko Perttunen @ 2017-05-14 11:29 UTC (permalink / raw)
To: Preetham Chandru,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Laxman Dewangan,
preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
Venu Byravarasu, Pavan Kunapuli,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1f54292e718c4bb5a02d547d041804b0-7W72rfoJkVnYuxH7O460wFaTQe2KTcn/@public.gmane.org>
On 05/12/2017 12:56 PM, Preetham Chandru wrote:
> +CC linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>
>> -----Original Message-----
>> From: Preetham Chandru
>> Sent: Friday, May 12, 2017 3:04 PM
>> To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
>> Cc: tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Laxman Dewangan
>> <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; preetham260-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; Venu Byravarasu
>> <vbyravarasu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Pavan Kunapuli <pkunapuli-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>; Preetham
>> Chandru <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> Subject: [PATCH V3 3/3] arm64: tegra: Enable SATA on Tegra210
>>
>> From: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> Enable the SATA unit on Tegra210 systems.
>>
>> Signed-off-by: Preetham Chandru R <pchandru-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 6 ++++++
>> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 16 ++++++++++++++++
>> 2 files changed, 22 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
>> b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
>> index e5fc67b..58c28b9 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
>> @@ -1324,6 +1324,12 @@
>> status = "okay";
>> };
>>
>> + sata@70020000 {
>> + status = "okay";
>> + phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
>> + phy-names = "sata-0";
>> + };
>> +
>> padctl@7009f000 {
>> status = "okay";
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>> b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>> index 8f26c4d..20c9160 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
>> @@ -795,6 +795,22 @@
>> #iommu-cells = <1>;
>> };
>>
>> + sata@70020000 {
>> + compatible = "nvidia,tegra210-ahci";
>> + reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
>> + <0x0 0x70020000 0x0 0x7000>, /* SATA */
>> + <0x0 0x70001100 0x0 0x1000>; /* SATA AUX*/
Missing space after 'AUX'
>> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&tegra_car TEGRA210_CLK_SATA>,
>> + <&tegra_car TEGRA210_CLK_SATA_OOB>;
>> + clock-names = "sata", "sata-oob";
>> + resets = <&tegra_car 124>,
>> + <&tegra_car 123>,
>> + <&tegra_car 129>;
>> + reset-names = "sata", "sata-oob", "sata-cold";
The binding documentation says that sata-cold is not required for tegra210?
>> + status = "disabled";
>> + };
>> +
>> hda@70030000 {
>> compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
>> reg = <0x0 0x70030000 0x0 0x10000>;
>> --
>> 2.1.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH 00/13] Get rid of DocBook
From: Mauro Carvalho Chehab @ 2017-05-14 15:38 UTC (permalink / raw)
To: Linux Doc Mailing List
Cc: linux-ide, linux-fbdev, linux-ia64, Fenghua Yu, Peter Zijlstra,
linux-pci, Richard Sailer, Herton R. Krzesinski, alsa-devel,
dri-devel, Jaroslav Kysela, Masahiro Yamada, Daniel Vetter,
Jiri Slaby, Ingo Molnar, Hans-Christian Noren Egtvedt,
Markus Heiser, James E.J. Bottomley, linux-scsi, Jonathan Corbet,
Sanjeev, Bartlomiej Zolnierkiewicz, Tony Luck,
Mauro Carvalho Chehab
As just one book (lsm) was missing conversion, let's convert it
and store as if it were a plain text file under Documentation/lsm.txt,
adding a notice that it requires update.
This way, as everything is now converted, we can get rid of
the DocBook building system and update places that were
mentioning it.
PS.: We could also remove the parts of the kernel-doc script that
produce DocBook outputs, but, as this might still be useful
for someone, for now let's just keep the functionality there.
-
This patch series is based on my past 00/05 and 00/36 patch series
that convert the other DocBooks to ReST, applied on the top of
docs tree (next branch).
The full patch series is on this tree is at:
https://git.linuxtv.org//mchehab/experimental.git/log/?h=docbook2
And the HTML output at:
http://www.infradead.org/~mchehab/kernel_docs/
https://mchehab.fedorapeople.org/kernel_docs/
Mauro Carvalho Chehab (13):
docs-rst: convert lsm from DocBook to ReST
docs: remove DocBook from the building system
docs: update old references for DocBook from the documentation
MAINTAINERS: update old references for DocBook directory
ata: update references for libata documentation
ia64, scsi: update references for the device-io book
irq: update genericirq book location
fs: update location of filesystems documentation
lib: update location of kgdb documentation
sound: fix the comments that refers to kernel-doc
fs: fix the location of the kernel-api book
usb: fix the comment with regards to DocBook
docs-rst: get rid of Documentation/sphinx/tmplcvt script
Documentation/00-INDEX | 6 +-
Documentation/DocBook/.gitignore | 17 --
Documentation/DocBook/Makefile | 276 -----------------------------
Documentation/DocBook/lsm.tmpl | 265 ---------------------------
Documentation/DocBook/stylesheet.xsl | 11 --
Documentation/Makefile | 125 +++++++++++++
Documentation/Makefile.sphinx | 130 --------------
Documentation/PCI/MSI-HOWTO.txt | 2 +-
Documentation/admin-guide/README.rst | 6 -
Documentation/doc-guide/docbook.rst | 90 ----------
Documentation/doc-guide/index.rst | 1 -
Documentation/doc-guide/sphinx.rst | 5 -
Documentation/fb/api.txt | 4 +-
Documentation/gpu/todo.rst | 2 +-
Documentation/kernel-doc-nano-HOWTO.txt | 65 ++-----
Documentation/lsm.txt | 201 +++++++++++++++++++++
Documentation/process/changes.rst | 26 +--
Documentation/process/howto.rst | 8 -
Documentation/process/kernel-docs.rst | 34 +---
Documentation/sphinx/tmplcvt | 28 ---
Documentation/translations/ja_JP/howto.rst | 7 -
Documentation/translations/ko_KR/howto.rst | 7 -
MAINTAINERS | 5 +-
Makefile | 11 +-
arch/ia64/include/asm/io.h | 2 +-
arch/ia64/sn/kernel/iomv.c | 2 +-
drivers/ata/acard-ahci.c | 2 +-
drivers/ata/ahci.c | 2 +-
drivers/ata/ahci.h | 2 +-
drivers/ata/ata_piix.c | 2 +-
drivers/ata/libahci.c | 2 +-
drivers/ata/libata-core.c | 2 +-
drivers/ata/libata-eh.c | 2 +-
drivers/ata/libata-scsi.c | 2 +-
drivers/ata/libata-sff.c | 2 +-
drivers/ata/libata.h | 2 +-
drivers/ata/pata_pdc2027x.c | 2 +-
drivers/ata/pdc_adma.c | 2 +-
drivers/ata/sata_nv.c | 2 +-
drivers/ata/sata_promise.c | 2 +-
drivers/ata/sata_promise.h | 2 +-
drivers/ata/sata_qstor.c | 2 +-
drivers/ata/sata_sil.c | 2 +-
drivers/ata/sata_sis.c | 2 +-
drivers/ata/sata_svw.c | 2 +-
drivers/ata/sata_sx4.c | 2 +-
drivers/ata/sata_uli.c | 2 +-
drivers/ata/sata_via.c | 2 +-
drivers/ata/sata_vsc.c | 2 +-
drivers/scsi/qla1280.c | 2 +-
drivers/usb/gadget/Kconfig | 2 +-
fs/debugfs/file.c | 2 +-
fs/debugfs/inode.c | 2 +-
include/linux/ata.h | 2 +-
include/linux/debugfs.h | 2 +-
include/linux/libata.h | 2 +-
include/sound/pcm.h | 2 +-
kernel/irq/chip.c | 2 +-
kernel/irq/handle.c | 2 +-
kernel/irq/irqdesc.c | 2 +-
lib/Kconfig.debug | 2 +-
lib/Kconfig.kgdb | 2 +-
scripts/Makefile | 9 +-
scripts/check-lc_ctype.c | 11 --
64 files changed, 396 insertions(+), 1032 deletions(-)
delete mode 100644 Documentation/DocBook/.gitignore
delete mode 100644 Documentation/DocBook/Makefile
delete mode 100644 Documentation/DocBook/lsm.tmpl
delete mode 100644 Documentation/DocBook/stylesheet.xsl
delete mode 100644 Documentation/Makefile.sphinx
delete mode 100644 Documentation/doc-guide/docbook.rst
create mode 100644 Documentation/lsm.txt
delete mode 100755 Documentation/sphinx/tmplcvt
delete mode 100644 scripts/check-lc_ctype.c
--
2.9.3
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
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