* [PATCH v2 0/2] Add support for MediaTek AHCI SATA
From: Ryder Lee @ 2017-08-07 9:52 UTC (permalink / raw)
To: Hans de Goede, Tejun Heo
Cc: Rob Herring, devicetree, linux-mediatek, linux-kernel, linux-ide,
Long Cheng, Ryder Lee
Hi,
This patch series add support for AHCI compatible SATA controller, and it is
compliant with the ahci 1.3 and sata 3.0 specification. This driver is slightly
different than ahci_platform.c (e.g., reset control, subsystem setting).
changes since v2:
- according to Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines").
replace devm_reset_control_get_optional() by devm_reset_control_get_optional_exclusive().
changes since v1:
- update binding text: add missing "specifier pairs" descriptions.
- fix kbuild test warning: fix the error handling.
Ryder Lee (2):
ata: mediatek: add support for MediaTek SATA controller
dt-bindings: ata: add DT bindings for MediaTek SATA controller
Documentation/devicetree/bindings/ata/ahci-mtk.txt | 50 ++++++
drivers/ata/Kconfig | 10 ++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_mtk.c | 196 +++++++++++++++++++++
4 files changed, 257 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt
create mode 100644 drivers/ata/ahci_mtk.c
--
1.9.1
^ permalink raw reply
* [PATCH v2 2/2] dt-bindings: ata: add DT bindings for MediaTek SATA controller
From: Ryder Lee @ 2017-08-07 9:52 UTC (permalink / raw)
To: Hans de Goede, Tejun Heo
Cc: Rob Herring, devicetree, linux-mediatek, linux-kernel, linux-ide,
Long Cheng, Ryder Lee
In-Reply-To: <cover.1502098458.git.ryder.lee@mediatek.com>
Add DT bindings for the onboard SATA controller present on the MediaTek
SoCs.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
Documentation/devicetree/bindings/ata/ahci-mtk.txt | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt
diff --git a/Documentation/devicetree/bindings/ata/ahci-mtk.txt b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
new file mode 100644
index 0000000..ed04dfc
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
@@ -0,0 +1,50 @@
+MediaTek Seria ATA controller
+
+Required properties:
+ - compatible : Must be "mediatek,ahci".
+ - reg : Physical base addresses and length of register sets.
+ - interrupts : Interrupt associated with the SATA device.
+ - interrupt-names : Associated name must be: "hostc".
+ - clocks : A list of phandle and clock specifier pairs, one for each
+ entry in clock-names.
+ - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
+ - phys : A phandle and PHY specifier pair for the PHY port.
+ - phy-names : Associated name must be: "sata-phy".
+ - ports-implemented : Mask that indicates which ports that the HBA supports
+ are available for software to use. Useful if PORTS_IMPL
+ is not programmed by the BIOS, which is true with some
+ embedded SOC's.
+
+Optional properties:
+ - power-domains : A phandle and power domain specifier pair to the power
+ domain which is responsible for collapsing and restoring
+ power to the peripheral.
+ - resets : Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+ - reset-names : Associated names must be: "axi", "sw", "reg".
+ - mediatek,phy-mode : A phandle to the system controller, used to enable
+ SATA function.
+
+Example:
+
+ sata: sata@1a200000 {
+ compatible = "mediatek,ahci";
+ reg = <0 0x1a200000 0 0x1100>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ clocks = <&pciesys CLK_SATA_AHB_EN>,
+ <&pciesys CLK_SATA_AXI_EN>,
+ <&pciesys CLK_SATA_ASIC_EN>,
+ <&pciesys CLK_SATA_RBC_EN>,
+ <&pciesys CLK_SATA_PM_EN>;
+ clock-names = "ahb", "axi", "asic", "rbc", "pm";
+ phys = <&u3port1 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+ <&pciesys MT7622_SATA_PHY_SW_RST>,
+ <&pciesys MT7622_SATA_PHY_REG_RST>;
+ reset-names = "axi", "sw", "reg";
+ mediatek,phy-mode = <&pciesys>;
+ };
--
1.9.1
^ permalink raw reply related
* [PATCH v2 1/2] ata: mediatek: add support for MediaTek SATA controller
From: Ryder Lee @ 2017-08-07 9:52 UTC (permalink / raw)
To: Hans de Goede, Tejun Heo
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Ryder Lee,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
linux-ide-u79uwXL29TY76Z2rM5mHXA, Long Cheng,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <cover.1502098458.git.ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
This adds support the AHCI-compliant Serial ATA controller present
on MediaTek SoCs.
Signed-off-by: Ryder Lee <ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/ata/Kconfig | 10 +++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_mtk.c | 196 +++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 207 insertions(+)
create mode 100644 drivers/ata/ahci_mtk.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 363fc53..488c937 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -153,6 +153,16 @@ config AHCI_CEVA
If unsure, say N.
+config AHCI_MTK
+ tristate "MediaTek AHCI SATA support"
+ depends on ARCH_MEDIATEK
+ select MFD_SYSCON
+ help
+ This option enables support for the MediaTek SoC's
+ onboard AHCI SATA controller.
+
+ If unsure, say N.
+
config AHCI_MVEBU
tristate "Marvell EBU AHCI SATA support"
depends on ARCH_MVEBU
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index a26ef5a..ff9cd2e 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DM816) += ahci_dm816.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_MTK) += ahci_mtk.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_OCTEON) += ahci_octeon.o
obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_mtk.c b/drivers/ata/ahci_mtk.c
new file mode 100644
index 0000000..5bd3046
--- /dev/null
+++ b/drivers/ata/ahci_mtk.c
@@ -0,0 +1,196 @@
+/*
+ * MeidaTek AHCI SATA driver
+ *
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/ahci_platform.h>
+#include <linux/kernel.h>
+#include <linux/libata.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include "ahci.h"
+
+#define DRV_NAME "ahci"
+
+#define SYS_CFG 0x14
+#define SYS_CFG_SATA_MSK GENMASK(31, 30)
+#define SYS_CFG_SATA_EN BIT(31)
+
+struct mtk_ahci_plat {
+ struct regmap *mode;
+ struct reset_control *axi_rst;
+ struct reset_control *sw_rst;
+ struct reset_control *reg_rst;
+};
+
+static const struct ata_port_info ahci_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &ahci_platform_ops,
+};
+
+static struct scsi_host_template ahci_platform_sht = {
+ AHCI_SHT(DRV_NAME),
+};
+
+static int mtk_ahci_platform_resets(struct ahci_host_priv *hpriv,
+ struct device *dev)
+{
+ struct mtk_ahci_plat *plat = hpriv->plat_data;
+ int err;
+
+ /* reset AXI bus and PHY part */
+ plat->axi_rst = devm_reset_control_get_optional_exclusive(dev, "axi");
+ if (PTR_ERR(plat->axi_rst) == -EPROBE_DEFER)
+ return PTR_ERR(plat->axi_rst);
+
+ plat->sw_rst = devm_reset_control_get_optional_exclusive(dev, "sw");
+ if (PTR_ERR(plat->sw_rst) == -EPROBE_DEFER)
+ return PTR_ERR(plat->sw_rst);
+
+ plat->reg_rst = devm_reset_control_get_optional_exclusive(dev, "reg");
+ if (PTR_ERR(plat->reg_rst) == -EPROBE_DEFER)
+ return PTR_ERR(plat->reg_rst);
+
+ err = reset_control_assert(plat->axi_rst);
+ if (err) {
+ dev_err(dev, "assert axi bus failed\n");
+ return err;
+ }
+
+ err = reset_control_assert(plat->sw_rst);
+ if (err) {
+ dev_err(dev, "assert phy digital part failed\n");
+ return err;
+ }
+
+ err = reset_control_assert(plat->reg_rst);
+ if (err) {
+ dev_err(dev, "assert phy register part failed\n");
+ return err;
+ }
+
+ err = reset_control_deassert(plat->reg_rst);
+ if (err) {
+ dev_err(dev, "deassert phy register part failed\n");
+ return err;
+ }
+
+ err = reset_control_deassert(plat->sw_rst);
+ if (err) {
+ dev_err(dev, "deassert phy digital part failed\n");
+ return err;
+ }
+
+ err = reset_control_deassert(plat->axi_rst);
+ if (err) {
+ dev_err(dev, "deassert axi bus failed\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv,
+ struct device *dev)
+{
+ struct mtk_ahci_plat *plat = hpriv->plat_data;
+ struct device_node *np = dev->of_node;
+
+ /* enable SATA function if needed */
+ if (of_find_property(np, "mediatek,phy-mode", NULL)) {
+ plat->mode = syscon_regmap_lookup_by_phandle(
+ np, "mediatek,phy-mode");
+ if (IS_ERR(plat->mode)) {
+ dev_err(dev, "missing phy-mode phandle\n");
+ return PTR_ERR(plat->mode);
+ }
+
+ regmap_update_bits(plat->mode, SYS_CFG, SYS_CFG_SATA_MSK,
+ SYS_CFG_SATA_EN);
+ }
+
+ of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map);
+
+ return 0;
+}
+
+static int mtk_ahci_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ahci_plat *plat;
+ struct ahci_host_priv *hpriv;
+ int err;
+
+ plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL);
+ if (!plat)
+ return -ENOMEM;
+
+ hpriv = ahci_platform_get_resources(pdev);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
+
+ hpriv->plat_data = plat;
+
+ err = mtk_ahci_parse_property(hpriv, dev);
+ if (err)
+ return err;
+
+ err = mtk_ahci_platform_resets(hpriv, dev);
+ if (err)
+ return err;
+
+ err = ahci_platform_enable_resources(hpriv);
+ if (err)
+ return err;
+
+ err = ahci_platform_init_host(pdev, hpriv, &ahci_port_info,
+ &ahci_platform_sht);
+ if (err)
+ goto disable_resources;
+
+ return 0;
+
+disable_resources:
+ ahci_platform_disable_resources(hpriv);
+ return err;
+}
+
+static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
+ ahci_platform_resume);
+
+static const struct of_device_id ahci_of_match[] = {
+ { .compatible = "mediatek,ahci", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ahci_of_match);
+
+static struct platform_driver mtk_ahci_driver = {
+ .probe = mtk_ahci_probe,
+ .remove = ata_platform_remove_one,
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = ahci_of_match,
+ .pm = &ahci_pm_ops,
+ },
+};
+module_platform_driver(mtk_ahci_driver);
+
+MODULE_DESCRIPTION("MeidaTek SATA AHCI Driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1
^ permalink raw reply related
* Re: [PATCH] ata: ahci_platform: Add shutdown handler
From: Tejun Heo @ 2017-08-04 20:35 UTC (permalink / raw)
To: Nate Watterson; +Cc: Hans de Goede, linux-ide, linux-kernel
In-Reply-To: <1500578784-15407-1-git-send-email-nwatters@codeaurora.org>
On Thu, Jul 20, 2017 at 03:26:24PM -0400, Nate Watterson wrote:
> The newly introduced ahci_platform_shutdown() method is called during
> system shutdown to disable host controller DMA and interrupts in order
> to avoid potentially corrupting or otherwise interfering with a new
> kernel being started with kexec.
>
> Signed-off-by: Nate Watterson <nwatters@codeaurora.org>
Applied to libata/for-4.14.
Thanks.
--
tejun
^ permalink raw reply
* [PATCH 6/9] ata: ceva: Add CCI support for SATA if CCI is enabled
From: Michal Simek @ 2017-08-04 13:18 UTC (permalink / raw)
To: linux-kernel, monstr
Cc: Alexander Graf, Anurag Kumar Vulisha, Tejun Heo, linux-ide
In-Reply-To: <cover.1501852693.git.michal.simek@xilinx.com>
From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
This patch adds support for CCI in SATA controller if CCI is
enabled in design. This patch will add CCI settings for SATA
if "dma-coherent" dts property is added.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/ata/ahci_ceva.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index eff40ec86065..ec9cfb52c6f6 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -32,6 +32,7 @@
#define AHCI_VEND_PP3C 0xB0
#define AHCI_VEND_PP4C 0xB4
#define AHCI_VEND_PP5C 0xB8
+#define AHCI_VEND_AXICC 0xBC
#define AHCI_VEND_PAXIC 0xC0
#define AHCI_VEND_PTC 0xC8
@@ -41,6 +42,15 @@
#define PAXIC_MARIDD (1 << 16)
#define PAXIC_OTL (0x4 << 20)
+/* Register bit definitions for cache control */
+#define AXICC_ARCA_VAL (0xF << 0)
+#define AXICC_ARCF_VAL (0xF << 4)
+#define AXICC_ARCH_VAL (0xF << 8)
+#define AXICC_ARCP_VAL (0xF << 12)
+#define AXICC_AWCFD_VAL (0xF << 16)
+#define AXICC_AWCD_VAL (0xF << 20)
+#define AXICC_AWCF_VAL (0xF << 24)
+
#define PCFG_TPSS_VAL (0x32 << 16)
#define PCFG_TPRS_VAL (0x2 << 12)
#define PCFG_PAD_VAL 0x2
@@ -82,6 +92,9 @@ struct ceva_ahci_priv {
u32 pp3c[NR_PORTS];
u32 pp4c[NR_PORTS];
u32 pp5c[NR_PORTS];
+ /* Axi Cache Control Register */
+ u32 axicc;
+ bool is_cci_enabled;
int flags;
};
@@ -139,6 +152,16 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
writel(tmp, mmio + AHCI_VEND_PCFG);
+ /* Set AXI cache control register if CCi is enabled */
+ if (cevapriv->is_cci_enabled) {
+ tmp = readl(mmio + AHCI_VEND_AXICC);
+ tmp |= AXICC_ARCA_VAL | AXICC_ARCF_VAL |
+ AXICC_ARCH_VAL | AXICC_ARCP_VAL |
+ AXICC_AWCFD_VAL | AXICC_AWCD_VAL |
+ AXICC_AWCF_VAL;
+ writel(tmp, mmio + AHCI_VEND_AXICC);
+ }
+
/* Port Phy Cfg register enables */
tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
writel(tmp, mmio + AHCI_VEND_PPCFG);
@@ -177,6 +200,7 @@ static int ceva_ahci_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct ahci_host_priv *hpriv;
struct ceva_ahci_priv *cevapriv;
+ enum dev_dma_attr attr;
int rc;
cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL);
@@ -248,6 +272,13 @@ static int ceva_ahci_probe(struct platform_device *pdev)
return -EINVAL;
}
+ /*
+ * Check if CCI is enabled for SATA. The DEV_DMA_COHERENT is returned
+ * if CCI is enabled, so check for DEV_DMA_COHERENT.
+ */
+ attr = device_get_dma_attr(dev);
+ cevapriv->is_cci_enabled = (attr == DEV_DMA_COHERENT);
+
hpriv->plat_data = cevapriv;
/* CEVA specific initialization */
--
1.9.1
^ permalink raw reply related
* [PATCH 9/9] ata: ceva: Add SMMU support for SATA IP
From: Michal Simek @ 2017-08-04 13:18 UTC (permalink / raw)
To: linux-kernel, monstr
Cc: Alexander Graf, Anurag Kumar Vulisha, Tejun Heo, linux-ide
In-Reply-To: <cover.1501852693.git.michal.simek@xilinx.com>
From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
AXI master interface in CEVA AHCI controller requires two unique
Write/Read ID tags per port. This is because, ahci controller uses
different AXI ID[3:0] bits for identifying non-data transfers(like
reading descriptors, updating PRD tables, etc) and data transfers
(like sending/receiving FIS).To make SMMU work with SATA we need to
add correct SMMU stream id for SATA. SMMU stream id for SATA is
determined based on the AXI ID[1:0] as shown below
SATA SMMU ID = <TBU number>, 0011, 00, 00, AXI ID[1:0]
Note: SATA in ZynqMp uses TBU1 so TBU number = 0x1, so
SMMU ID = 001, 0011, 00, 00, AXI ID[1:0]
Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1
as said above) we get four different SMMU stream id's combinations
for SATA. These AXI ID can be configured using PAXIC register.
In this patch we assumed the below AXI ID values
Read ID/ Write ID for Non-Data Port0 transfers = 0
Read ID/ Write ID for Data Port0 transfers = 1
Read ID/ Write ID for Non-Data Port1 transfers = 2
Read ID/ Write ID for Data Port1 transfers = 3
Based on the above values,SMMU stream ID's for SATA will be 0x4c0 &
0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be
added to iommus dts property. This patch does the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/ata/ahci_ceva.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index c0742cbe4faa..5ecc9d46cb54 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -38,8 +38,10 @@
/* Vendor Specific Register bit definitions */
#define PAXIC_ADBW_BW64 0x1
-#define PAXIC_MAWIDD (1 << 8)
-#define PAXIC_MARIDD (1 << 16)
+#define PAXIC_MAWID(i) (((i) * 2) << 4)
+#define PAXIC_MARID(i) (((i) * 2) << 12)
+#define PAXIC_MARIDD(i) ((((i) * 2) + 1) << 16)
+#define PAXIC_MAWIDD(i) ((((i) * 2) + 1) << 8)
#define PAXIC_OTL (0x4 << 20)
/* Register bit definitions for cache control */
@@ -147,9 +149,11 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
/*
* AXI Data bus width to 64
* Set Mem Addr Read, Write ID for data transfers
+ * Set Mem Addr Read ID, Write ID for non-data transfers
* Transfer limit to 72 DWord
*/
- tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
+ tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD(i) | PAXIC_MARIDD(i) |
+ PAXIC_MAWID(i) | PAXIC_MARID(i) | PAXIC_OTL;
writel(tmp, mmio + AHCI_VEND_PAXIC);
/* Set AXI cache control register if CCi is enabled */
--
1.9.1
^ permalink raw reply related
* [PATCH 8/9] ata: ceva: Correct the suspend and resume logic for SATA
From: Michal Simek @ 2017-08-04 13:18 UTC (permalink / raw)
To: linux-kernel, monstr
Cc: Alexander Graf, Anurag Kumar Vulisha, Tejun Heo, linux-ide
In-Reply-To: <cover.1501852693.git.michal.simek@xilinx.com>
From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
The present suspend code disables the port interrupts
and stops the HBA. On resume it enables the interrupts and HBA.
This works fine until the FPD power domain is not off.
If FPD is off then the ceva vendor specific configurations like
OOB, AXI settings are lost, they need to be re-programmed and
also since SERDES is also in FPD , SATA lane phy init needs to
be called again (which is not happening in the present sequence)
Because of this incorrect sequence SATA fails to work on resume.
This patch corrects the code to make Suspend & Resume work in normal
and FPD off cases.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Reviewed-by: Shubhrajyoti Datta <shubhraj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/ata/ahci_ceva.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index 113c1f617da9..c0742cbe4faa 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -298,12 +298,37 @@ static int ceva_ahci_probe(struct platform_device *pdev)
static int __maybe_unused ceva_ahci_suspend(struct device *dev)
{
- return ahci_platform_suspend_host(dev);
+ return ahci_platform_suspend(dev);
}
static int __maybe_unused ceva_ahci_resume(struct device *dev)
{
- return ahci_platform_resume_host(dev);
+ struct ata_host *host = dev_get_drvdata(dev);
+ struct ahci_host_priv *hpriv = host->private_data;
+ int rc;
+
+ rc = ahci_platform_enable_resources(hpriv);
+ if (rc)
+ return rc;
+
+ /* Configure CEVA specific config before resuming HBA */
+ ahci_ceva_setup(hpriv);
+
+ rc = ahci_platform_resume_host(dev);
+ if (rc)
+ goto disable_resources;
+
+ /* We resumed so update PM runtime state */
+ pm_runtime_disable(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ return 0;
+
+disable_resources:
+ ahci_platform_disable_resources(hpriv);
+
+ return rc;
}
static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume);
--
1.9.1
^ permalink raw reply related
* [PATCH 7/9] ata: ceva: Correct the AXI bus configuration for SATA ports
From: Michal Simek @ 2017-08-04 13:18 UTC (permalink / raw)
To: linux-kernel, monstr
Cc: Alexander Graf, Anurag Kumar Vulisha, Tejun Heo, linux-ide
In-Reply-To: <cover.1501852693.git.michal.simek@xilinx.com>
From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Previously PAXIC register was programmed before configuring PCFG
register. PCFG should be programmed with the address of the port
for which PAXIC should be configured for.
This was not happening before, so only one port PAXIC was written
correctly and the other port was having wrong value.
This patch moves the PXAIC register write after configuring PCFG,
doing so will correct the axi bus settings for sata port0 & port1.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/ata/ahci_ceva.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index ec9cfb52c6f6..113c1f617da9 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -134,14 +134,6 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
u32 tmp;
int i;
- /*
- * AXI Data bus width to 64
- * Set Mem Addr Read, Write ID for data transfers
- * Transfer limit to 72 DWord
- */
- tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
- writel(tmp, mmio + AHCI_VEND_PAXIC);
-
/* Set AHCI Enable */
tmp = readl(mmio + HOST_CTL);
tmp |= HOST_AHCI_EN;
@@ -152,6 +144,14 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
writel(tmp, mmio + AHCI_VEND_PCFG);
+ /*
+ * AXI Data bus width to 64
+ * Set Mem Addr Read, Write ID for data transfers
+ * Transfer limit to 72 DWord
+ */
+ tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
+ writel(tmp, mmio + AHCI_VEND_PAXIC);
+
/* Set AXI cache control register if CCi is enabled */
if (cevapriv->is_cci_enabled) {
tmp = readl(mmio + AHCI_VEND_AXICC);
--
1.9.1
^ permalink raw reply related
* [PATCH 5/9] ata: ceva: Make RxWaterMark value as module parameter
From: Michal Simek @ 2017-08-04 13:18 UTC (permalink / raw)
To: linux-kernel, monstr
Cc: Alexander Graf, Anurag Kumar Vulisha, Tejun Heo, linux-ide
In-Reply-To: <cover.1501852693.git.michal.simek@xilinx.com>
From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
This patch updates the driver to make Rx Fifo water mark value
as a module parameter.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/ata/ahci_ceva.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index b63fab2507fa..eff40ec86065 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -71,6 +71,10 @@
#define DRV_NAME "ahci-ceva"
#define CEVA_FLAG_BROKEN_GEN2 1
+static unsigned int rx_watermark = PTC_RX_WM_VAL;
+module_param(rx_watermark, uint, 0644);
+MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
+
struct ceva_ahci_priv {
struct platform_device *ahci_pdev;
/* Port Phy2Cfg Register */
@@ -152,7 +156,7 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
writel(cevapriv->pp5c[i], mmio + AHCI_VEND_PP5C);
/* Rx Watermark setting */
- tmp = PTC_RX_WM_VAL | PTC_RSVD;
+ tmp = rx_watermark | PTC_RSVD;
writel(tmp, mmio + AHCI_VEND_PTC);
/* Default to Gen 3 Speed and Gen 1 if Gen2 is broken */
--
1.9.1
^ permalink raw reply related
* [PATCH 4/9] ata: ceva: Disable Device Sleep capability
From: Michal Simek @ 2017-08-04 13:18 UTC (permalink / raw)
To: linux-kernel, monstr
Cc: Alexander Graf, Anurag Kumar Vulisha, Tejun Heo, linux-ide
In-Reply-To: <cover.1501852693.git.michal.simek@xilinx.com>
From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Since CEVA controller does not support Device Sleep capability,
we need to clear that feature by clearing the DEVSLP bit in word78
of IDENTIFY DEVICE data. This patch does the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/ata/ahci_ceva.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index aa32c8a0f083..b63fab2507fa 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -81,8 +81,26 @@ struct ceva_ahci_priv {
int flags;
};
+static unsigned int ceva_ahci_read_id(struct ata_device *dev,
+ struct ata_taskfile *tf, u16 *id)
+{
+ u32 err_mask;
+
+ err_mask = ata_do_dev_read_id(dev, tf, id);
+ if (err_mask)
+ return err_mask;
+ /*
+ * Since CEVA controller does not support device sleep feature, we
+ * need to clear DEVSLP (bit 8) in word78 of the IDENTIFY DEVICE data.
+ */
+ id[ATA_ID_FEATURE_SUPP] &= cpu_to_le16(~(1 << 8));
+
+ return 0;
+}
+
static struct ata_port_operations ahci_ceva_ops = {
.inherits = &ahci_platform_ops,
+ .read_id = ceva_ahci_read_id,
};
static const struct ata_port_info ahci_ceva_port_info = {
--
1.9.1
^ permalink raw reply related
* [PATCH 3/9] ata: ceva: Add gen 3 mode support in driver
From: Michal Simek @ 2017-08-04 13:18 UTC (permalink / raw)
To: linux-kernel, monstr
Cc: Alexander Graf, Anurag Kumar Vulisha, Tejun Heo, linux-ide
In-Reply-To: <cover.1501852693.git.michal.simek@xilinx.com>
From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
This patch sets gen 3 mode as default mode in ahci_ceva driver.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/ata/ahci_ceva.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index 59de2ca1885c..aa32c8a0f083 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -60,6 +60,7 @@
#define PORT1_BASE 0x180
/* Port Control Register Bit Definitions */
+#define PORT_SCTL_SPD_GEN3 (0x3 << 4)
#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
#define PORT_SCTL_IPM (0x3 << 8)
@@ -136,8 +137,8 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
tmp = PTC_RX_WM_VAL | PTC_RSVD;
writel(tmp, mmio + AHCI_VEND_PTC);
- /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
- tmp = PORT_SCTL_SPD_GEN2 | PORT_SCTL_IPM;
+ /* Default to Gen 3 Speed and Gen 1 if Gen2 is broken */
+ tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2)
tmp = PORT_SCTL_SPD_GEN1 | PORT_SCTL_IPM;
writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
--
1.9.1
^ permalink raw reply related
* [PATCH 2/9] ata: ceva: Move sata port phy oob settings to device-tree
From: Michal Simek @ 2017-08-04 13:18 UTC (permalink / raw)
To: linux-kernel, monstr
Cc: Alexander Graf, Anurag Kumar Vulisha, Tejun Heo, linux-ide
In-Reply-To: <cover.1501852693.git.michal.simek@xilinx.com>
From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
In SATA Speed negotiation happens with OOB(Out of Band) signals. These OOB
signal timing values are configured through vendor specific registers in the
SATA controller. These OOB timings depends on the generator and detector clock
frequency, which varies from board to board (ex: ep108 and zc1751 has different
clock frequencies).
To avoid maintaing these OOB settings in the driver, it is better to move these
settings to the device-tree node and read from the device-tree.
This patch does the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/ata/ahci_ceva.c | 84 +++++++++++++++++++++++++++++++++++--------------
1 file changed, 61 insertions(+), 23 deletions(-)
diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index 207649d323c5..59de2ca1885c 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -50,21 +50,6 @@
#define PPCFG_PSS_EN (1 << 29)
#define PPCFG_ESDF_EN (1 << 31)
-#define PP2C_CIBGMN 0x0F
-#define PP2C_CIBGMX (0x25 << 8)
-#define PP2C_CIBGN (0x18 << 16)
-#define PP2C_CINMP (0x29 << 24)
-
-#define PP3C_CWBGMN 0x04
-#define PP3C_CWBGMX (0x0B << 8)
-#define PP3C_CWBGN (0x08 << 16)
-#define PP3C_CWNMP (0x0F << 24)
-
-#define PP4C_BMX 0x0a
-#define PP4C_BNM (0x08 << 8)
-#define PP4C_SFD (0x4a << 16)
-#define PP4C_PTST (0x06 << 24)
-
#define PP5C_RIT 0x60216
#define PP5C_RCT (0x7f0 << 20)
@@ -87,6 +72,11 @@
struct ceva_ahci_priv {
struct platform_device *ahci_pdev;
+ /* Port Phy2Cfg Register */
+ u32 pp2c[NR_PORTS];
+ u32 pp3c[NR_PORTS];
+ u32 pp4c[NR_PORTS];
+ u32 pp5c[NR_PORTS];
int flags;
};
@@ -131,20 +121,16 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
writel(tmp, mmio + AHCI_VEND_PPCFG);
/* Phy Control OOB timing parameters COMINIT */
- tmp = PP2C_CIBGMN | PP2C_CIBGMX | PP2C_CIBGN | PP2C_CINMP;
- writel(tmp, mmio + AHCI_VEND_PP2C);
+ writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C);
/* Phy Control OOB timing parameters COMWAKE */
- tmp = PP3C_CWBGMN | PP3C_CWBGMX | PP3C_CWBGN | PP3C_CWNMP;
- writel(tmp, mmio + AHCI_VEND_PP3C);
+ writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C);
/* Phy Control Burst timing setting */
- tmp = PP4C_BMX | PP4C_BNM | PP4C_SFD | PP4C_PTST;
- writel(tmp, mmio + AHCI_VEND_PP4C);
+ writel(cevapriv->pp4c[i], mmio + AHCI_VEND_PP4C);
/* Rate Change Timer and Retry Interval Timer setting */
- tmp = PP5C_RIT | PP5C_RCT;
- writel(tmp, mmio + AHCI_VEND_PP5C);
+ writel(cevapriv->pp5c[i], mmio + AHCI_VEND_PP5C);
/* Rx Watermark setting */
tmp = PTC_RX_WM_VAL | PTC_RSVD;
@@ -187,6 +173,58 @@ static int ceva_ahci_probe(struct platform_device *pdev)
if (of_property_read_bool(np, "ceva,broken-gen2"))
cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
+ /* Read OOB timing value for COMINIT from device-tree */
+ if (of_property_read_u8_array(np, "ceva,p0-cominit-params",
+ (u8 *)&cevapriv->pp2c[0], 4) < 0) {
+ dev_warn(dev, "ceva,p0-cominit-params property not defined\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u8_array(np, "ceva,p1-cominit-params",
+ (u8 *)&cevapriv->pp2c[1], 4) < 0) {
+ dev_warn(dev, "ceva,p1-cominit-params property not defined\n");
+ return -EINVAL;
+ }
+
+ /* Read OOB timing value for COMWAKE from device-tree*/
+ if (of_property_read_u8_array(np, "ceva,p0-comwake-params",
+ (u8 *)&cevapriv->pp3c[0], 4) < 0) {
+ dev_warn(dev, "ceva,p0-comwake-params property not defined\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u8_array(np, "ceva,p1-comwake-params",
+ (u8 *)&cevapriv->pp3c[1], 4) < 0) {
+ dev_warn(dev, "ceva,p1-comwake-params property not defined\n");
+ return -EINVAL;
+ }
+
+ /* Read phy BURST timing value from device-tree */
+ if (of_property_read_u8_array(np, "ceva,p0-burst-params",
+ (u8 *)&cevapriv->pp4c[0], 4) < 0) {
+ dev_warn(dev, "ceva,p0-burst-params property not defined\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u8_array(np, "ceva,p1-burst-params",
+ (u8 *)&cevapriv->pp4c[1], 4) < 0) {
+ dev_warn(dev, "ceva,p1-burst-params property not defined\n");
+ return -EINVAL;
+ }
+
+ /* Read phy RETRY interval timing value from device-tree */
+ if (of_property_read_u16_array(np, "ceva,p0-retry-params",
+ (u16 *)&cevapriv->pp5c[0], 2) < 0) {
+ dev_warn(dev, "ceva,p0-retry-params property not defined\n");
+ return -EINVAL;
+ }
+
+ if (of_property_read_u16_array(np, "ceva,p1-retry-params",
+ (u16 *)&cevapriv->pp5c[1], 2) < 0) {
+ dev_warn(dev, "ceva,p1-retry-params property not defined\n");
+ return -EINVAL;
+ }
+
hpriv->plat_data = cevapriv;
/* CEVA specific initialization */
--
1.9.1
^ permalink raw reply related
* [PATCH 1/9] devicetree: bindings: Add sata port phy config parameters in ahci-ceva
From: Michal Simek @ 2017-08-04 13:18 UTC (permalink / raw)
To: linux-kernel, monstr
Cc: Alexander Graf, Anurag Kumar Vulisha, Tejun Heo, devicetree,
linux-ide, Rob Herring, Mark Rutland
In-Reply-To: <cover.1501852693.git.michal.simek@xilinx.com>
From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
This patch adds device tree bindings for sata port phy parameters
in the ahci-ceva.txt file.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
.../devicetree/bindings/ata/ahci-ceva.txt | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
index 7ca8b976c13a..f97546f61444 100644
--- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
@@ -5,6 +5,36 @@ Required properties:
- compatible: Compatibility string. Must be 'ceva,ahci-1v84'.
- clocks: Input clock specifier. Refer to common clock bindings.
- interrupts: Interrupt specifier. Refer to interrupt binding.
+ - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
+ - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
+ The fields for the above parameter must be as shown below:
+ ceva,phy-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
+ CINMP : COMINIT Negate Minimum Period.
+ CIBGN : COMINIT Burst Gap Nominal.
+ CIBGMX: COMINIT Burst Gap Maximum.
+ CIBGMN: COMINIT Burst Gap Minimum.
+ - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
+ - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
+ The fields for the above parameter must be as shown below:
+ ceva,phy-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
+ CWBGMN: COMWAKE Burst Gap Minimum.
+ CWBGMX: COMWAKE Burst Gap Maximum.
+ CWBGN: COMWAKE Burst Gap Nominal.
+ CWNMP: COMWAKE Negate Minimum Period.
+ - ceva,p0-burst-params: Burst timing value for COM parameter for port 0.
+ - ceva,p1-burst-params: Burst timing value for COM parameter for port 1.
+ The fields for the above parameter must be as shown below:
+ ceva,phy-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
+ BMX: COM Burst Maximum.
+ BNM: COM Burst Nominal.
+ SFD: Signal Failure Detection value.
+ PTST: Partial to Slumber timer value.
+ - ceva,p0-retry-params: Retry interval timing value for port 0.
+ - ceva,p1-retry-params: Retry interval timing value for port 1.
+ The fields for the above parameter must be as shown below:
+ ceva,phy-retry-params = /bits/ 16 <RIT RCT>;
+ RIT: Retry Interval Timer.
+ RCT: Rate Change Timer.
Optional properties:
- ceva,broken-gen2: limit to gen1 speed instead of gen2.
@@ -16,5 +46,14 @@ Examples:
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
clocks = <&clkc SATA_CLK_ID>;
+ ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+ ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+ ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
+
+ ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+ ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+ ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,broken-gen2;
};
--
1.9.1
^ permalink raw reply related
* [PATCH 0/9] Ata ceva patches
From: Michal Simek @ 2017-08-04 13:18 UTC (permalink / raw)
To: linux-kernel, monstr
Cc: Alexander Graf, Tejun Heo, devicetree, linux-ide, Rob Herring,
Mark Rutland
Hi,
this patchset contains the latest changes which are available in Xilinx tree.
Thanks,
Michal
Anurag Kumar Vulisha (9):
devicetree: bindings: Add sata port phy config parameters in ahci-ceva
ata: ceva: Move sata port phy oob settings to device-tree
ata: ceva: Add gen 3 mode support in driver
ata: ceva: Disable Device Sleep capability
ata: ceva: Make RxWaterMark value as module parameter
ata: ceva: Add CCI support for SATA if CCI is enabled
ata: ceva: Correct the AXI bus configuration for SATA ports
ata: ceva: Correct the suspend and resume logic for SATA
ata: ceva: Add SMMU support for SATA IP
.../devicetree/bindings/ata/ahci-ceva.txt | 39 ++++
drivers/ata/ahci_ceva.c | 197 +++++++++++++++++----
2 files changed, 198 insertions(+), 38 deletions(-)
--
1.9.1
^ permalink raw reply
* 201705031342248841.jpg★★★ 全世界轨道交通规模最大 —— InnoTrans 2018 德国柏林国际轨道交通技术展 ★★★ [地右P4/L100-Z]
From: 施厐竽 @ 2017-08-04 0:24 UTC (permalink / raw)
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在线客服： QQ/邮箱/ 82775507@qq.com； 微信/ yondexpo； 微博/ http://weibo.com/guidaojiaotong
咨询电话： 4000-680-860（转8888、8144）； 139-1031-8144； 010—8699-7155、6923-6944；
２、 市 场 背 景 ：
随着世界经济的快速发展，人们对安全、快捷、环保的交通运输需求越来越高。作为一种能够使用各种能源种类的交通运输方式，轨道交通具有占地少、能耗低、污染小、运量大、全天候等多种优势，是节能环保型的运输工具。因此，当今世界各国纷纷对轨道交通建设投入巨资。根据世界顶级铁路行业机构——欧洲铁路行业联盟（CER）的调查统计，目前全球铁路市场总额为1033亿欧元，其中718亿欧元为可获取金额。未来十年铁路行业呈现上升趋势，预计年度增长为1.5-2%，十年后的铁路市场增幅将达到20%左右。
目前，除了西欧、日本和中国专注于发展高速铁路外，很多国家和地区如：印度、巴西、俄罗斯、中东、非洲、东南亚、甚至美国也开始纷纷加快干线铁路和城市轨道交通建设。
经过几十年的努力，我国的铁路和轨道交通建设事业取得了举世瞩目的成就，也培养和锻炼了我国自己的铁路工业体系。现在，我国轨道交通企业技术水平和竞争力不断提高，与西方发达国家相比，我国的很多轨道交通技术产品在技术和成本等方面具有自己的优势和特点，有着很强的竞争力。
３、 本 展 简 介 ：
“德国柏林国际轨道交通技术展览会（InnoTrans）”创办于1996年，每两年一届，2018年度为第十二届，十余年来发展迅速，目前是“全世界轨道交通行业规模最大，发展最快，专业观众最多的国际展览盛会”。展会分为“轨道技术展区”、“基础设施展区”、“隧道建设展区”、“公共交通展区”和“车辆内饰展区”等五大展区。由德国柏林国际展览有限公司（Messe Berlin GmbH）主办，得到了欧洲铁路联合会、德国铁路协会等机构的大力支持和协助。中国总展团的组办方为映德国际会展集团（YOND EXPO）中国代表处，在北京、上海等地设有分支机构，负责该展会在中国的推广和招商工作，以及中国境内企业参展参观的组织管理事宜，InnoTrans德国柏林轨道展中国总展团报名热线：4000-680-860转8888、8144；139-1031-8144。
InnoTrans是世界上轨道交通产品和技术展示与贸易的最佳平台，也是全世界专业人士沟通交流的理想场所，每一届的Innotrans展览会上都会出现很多来自各个国家的采购商、贸易商和相关政府官员。
“2018第12届德国柏林国际轨道交通技术展览会（InnoTrans 2018）”将于“9月18日至21日”在“柏林国际展览中心” 再度盛大举行。为了增进国内外轨道交通行业的交流与合作，同时展示我国轨道交通产业的发展与成就，帮助企业开拓国外市场，映德国际会展集团中国代表处将联合国家有关部门继续组团参加InnoTrans轨道交通展。我们诚邀全国各地相关单位与业界人士加入咱们的中国总展团前往参展参观。参加InnoTrans展会是一个轨道交通企业走向国际化的标志和途径。
展会组织者除了举行各种与轨道交通有关的高层研讨会以外，还将举办数十场专业会议和论坛等一系列的活动如：对话论坛、国际轨道交通高峰会以及2014年铁路技术设施建设特别会议。除了以上大型系列活动，展会中还有内容丰富的以轨道交通为中心的小型活动，如：“第五届UITP区域性和郊区轨道交通大会”，“第五届VDWG铁道论坛等。规模最大的组委会每届举办的圆桌会议和欧洲-亚洲轨道高峰会议，今年的第五届欧洲-亚洲轨道高峰会议邀请到了来自欧洲和亚洲多个国家的铁路部门部长等高级官员，以及轨道交通行业各大企业的高层人士。德国隧道联合会（Stuva）还专门举办了国际隧道论坛会议。
４、 区 位 优 势 ：
柏林位于欧洲中部，作为德国交通运输制造业最集中的重要城市，汇集了大约220家世界知名轨道交通技术公司，承办了世界各地大量大规模的相关施工项目。因此，柏林成为举办交通技术展览的理想场所，为众多此类的买家和卖家提供了交流和交易的平台。
欧洲铁路工业每年销售额为600亿欧元左右，占世界总量的70％。
５、 历 届 回 顾 ：
2014年柏林国际轨道交通技术展展览面积超过了138600平方米，使用了整个柏林国际展览中心的全部室内外场地。吸引了来自46个国家的2351家参展商，国际展商为1065家；展商展出的展品中，铁路设备及技术展52.9％，基础设施建设23.2％，公共交通工具为14.5％，隧道施工1.9％。本届展会接待超过87个国家的专业观众89600人，德国观众占53.5%，海外观众近51000名。德国、法国、美国、日本、英国、巴西等均组织了庞大的参观团到会参观采购。
轨道技术展区（Rail Technology）是最大的展区，几乎环绕了整个展览馆的中庭花园；
第二大展区是交通基础建设展区（Railway Infrastructure）其参展商数量从上届的300家增到了353余家；
隧道建设展区（Tunnel Construction）是2006年开始增加的特色展区，随着随到建设技术的逐渐成熟也越来越引起关注；
公共交通展区（Public Transport）的扩大则充分反映了世界各国城市轨道交通业对通讯需求的重视，面积达到了18000平米，285家展商中有一半来自德国以外的国家，该展区参展企业的展品集中于轨道交通通讯系统、公共交通管理系统、旅客信息系统等领域；
车辆内饰展区（Interior）的面积也比上届增长了50%，达到了13000平米。
在展览会举行期间，还同时举办了各种与轨道交通有关的高层研讨会和专业活动，如：铁路对话论坛、欧亚轨道交通高峰会、铁路技术设施建设特别会议等。
中国共有96家企业组团参与了本届展会，展示了我国在轨道交通车辆、零部件与配件、车辆内饰、电子、通信通讯等方面的产品和技术，受到了与会者的高度关注，取得了很好的效果。
６、 展 品 范 围 ：
◆ 铁道技术展区：
轨道交通及铁路机车车辆设备及零部件和机电设备；车辆段设备；供电系统；通信、信号系统；自动售检票系统；升降系统；火灾报警系统；通风、空调与采暖系统；环境与设备监控系统；综合监控系统；票务清分系统；屏蔽门安全系统；轨道交通及铁路建设施工材料、装备、安全、节能、环保技术与维护等；
◆ 基础设施展区：
铁道设施建设，车站及站场设备，轨道线路铺设、养护、维修装备与技术；铁道土木工程、桥梁道路、给排水、环境工程、风景园林、公用工程等建设；
◆ 隧道建设展区：
隧道施工建设机械设备、配件、材料与技术，工程机械，安全装置及设备等；地下交通检测、勘探技术、建设材料与技术设备等；地下线路、信号、桥梁、隧道、供电网、站房等施工机械及配套设备等；
◆ 公共交通展区：
智能交通管理系统、道路收费系统设备、智能交通产品及安防监控设备；视频监控设备、交通信息采集设备、交通控制设备、道路收费系统设备；地铁、汽车、巴士等轨道交通运输工具；
◆ 内部装饰展区：
铁轨车内部设计、更新、装饰服务，门、窗帘，隔断，桌椅，行李架，扶手杆，替换零件，锁柜，安全带，涂料，手推车，洗手间，厨房设备等。
７、 参 展 形 式 ：
◆ 参 展： 租赁【展位】，展示企业形象及产品，主要费用有【展位费】【运输费】【搭建费】【人员费】等。
◆ 参 观： 派遣【人员】，莅临展场参观及考察，主要费用有【报名费】【注册费】【交通费】【食宿费】等。
８、 筹 展 联 络 ：
有关参展参观“InnoTrans德国柏林轨道展”事宜，请联络【中国总展团】组办方：
参展顾问： 王先生、 杨先生、 孙小姐、 吴小姐
参展热线： 139-1031-8144、 131-2662-5206； 010— 8699- 7155、 6923- 6944.
全国统一客服热线： 4000- 580- 850.（分机:8888 / 分机:6666）
全国统一报名专线： 4000- 680- 860.（兼传真）
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^ permalink raw reply
* [bug report] potential out of bounds in IDE
From: Dan Carpenter @ 2017-08-03 14:48 UTC (permalink / raw)
To: Borislav Petkov; +Cc: linux-ide
Hi Borislav,
I was reviewing a static checker warning:
drivers/ide/ide-cd_ioctl.c:346 ide_cd_get_toc_entry()
warn: buffer overflow 'toc->ent' 100 <= 255
drivers/ide/ide-cd_ioctl.c
322 static int ide_cd_get_toc_entry(ide_drive_t *drive, int track,
323 struct atapi_toc_entry **ent)
324 {
325 struct cdrom_info *info = drive->driver_data;
326 struct atapi_toc *toc = info->toc;
327 int ntracks;
328
329 /*
330 * don't serve cached data, if the toc isn't valid
331 */
332 if ((drive->atapi_flags & IDE_AFLAG_TOC_VALID) == 0)
333 return -EINVAL;
334
335 /* Check validity of requested track number. */
336 ntracks = toc->hdr.last_track - toc->hdr.first_track + 1;
337
338 if (toc->hdr.first_track == CDROM_LEADOUT)
339 ntracks = 0;
340
341 if (track == CDROM_LEADOUT)
342 *ent = &toc->ent[ntracks];
343 else if (track < toc->hdr.first_track || track > toc->hdr.last_track)
344 return -EINVAL;
345 else
346 *ent = &toc->ent[track - toc->hdr.first_track];
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
->ent[] has 100 elements but we can't gaurantee that
"toc->hdr.last_track - toc->hdr.first_track" is is in 0-99 range.
347
348 return 0;
349 }
The ->first_track and ->last_track variables are set in ide_cd_read_toc()
from drivers/ide/ide-cd.c:
1017
1018 if (drive->atapi_flags & IDE_AFLAG_TOCTRACKS_AS_BCD) {
1019 toc->hdr.first_track = bcd2bin(toc->hdr.first_track);
1020 toc->hdr.last_track = bcd2bin(toc->hdr.last_track);
1021 }
1022
1023 ntracks = toc->hdr.last_track - toc->hdr.first_track + 1;
1024 if (ntracks <= 0)
1025 return -EIO;
1026 if (ntracks > MAX_TRACKS)
^^^^^^^^^^^^^^^^^^^^
This check implies that we can go over, but we leave the ->last_track as
is and continue.
1027 ntracks = MAX_TRACKS;
1028
1029 /* now read the whole schmeer */
1030 stat = cdrom_read_tocentry(drive, toc->hdr.first_track, 1, 0,
1031 (char *)&toc->hdr,
1032 sizeof(struct atapi_toc_header) +
1033 (ntracks + 1) *
1034 sizeof(struct atapi_toc_entry), sense);
1035
regards,
dan carpenter
^ permalink raw reply
* Re: [PATCH 005/102] ata: sata_gemini: explicitly request exclusive reset control
From: Tejun Heo @ 2017-08-02 15:15 UTC (permalink / raw)
To: Philipp Zabel; +Cc: linux-kernel, Linus Walleij, linux-ide
In-Reply-To: <20170719152646.25903-6-p.zabel@pengutronix.de>
On Wed, Jul 19, 2017 at 05:25:09PM +0200, Philipp Zabel wrote:
> Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
> reset lines") started to transition the reset control request API calls
> to explicitly state whether the driver needs exclusive or shared reset
> control behavior. Convert all drivers requesting exclusive resets to the
> explicit API call so the temporary transition helpers can be removed.
>
> No functional changes.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Tejun Heo <tj@kernel.org>
> Cc: linux-ide@vger.kernel.org
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Applied to libata/for-4.14.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 08/11] ata: Drop unnecessary static
From: Tejun Heo @ 2017-08-02 15:12 UTC (permalink / raw)
To: Julia Lawall
Cc: Linus Walleij, keescook, kernel-janitors, linux-ide, linux-kernel
In-Reply-To: <1500149266-32357-9-git-send-email-Julia.Lawall@lip6.fr>
On Sat, Jul 15, 2017 at 10:07:43PM +0200, Julia Lawall wrote:
> Drop static on a local variable, when the variable is initialized before
> any possible use. Thus, the static has no benefit.
>
> The semantic patch that fixes this problem is as follows:
> (http://coccinelle.lip6.fr/)
>
> // <smpl>
> @bad exists@
> position p;
> identifier x;
> type T;
> @@
> static T x@p;
> ...
> x = <+...x...+>
>
> @@
> identifier x;
> expression e;
> type T;
> position p != bad.p;
> @@
> -static
> T x@p;
> ... when != x
> when strict
> ?x = e;
> // </smpl>
>
> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Applied to libata/for-4.14.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 005/102] ata: sata_gemini: explicitly request exclusive reset control
From: Linus Walleij @ 2017-08-02 9:39 UTC (permalink / raw)
To: Philipp Zabel; +Cc: linux-kernel@vger.kernel.org, Tejun Heo, linux-ide
In-Reply-To: <20170719152646.25903-6-p.zabel@pengutronix.de>
On Wed, Jul 19, 2017 at 5:25 PM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
> reset lines") started to transition the reset control request API calls
> to explicitly state whether the driver needs exclusive or shared reset
> control behavior. Convert all drivers requesting exclusive resets to the
> explicit API call so the temporary transition helpers can be removed.
>
> No functional changes.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Tejun Heo <tj@kernel.org>
> Cc: linux-ide@vger.kernel.org
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 08/11] ata: Drop unnecessary static
From: Linus Walleij @ 2017-08-02 8:23 UTC (permalink / raw)
To: Julia Lawall
Cc: Kees Cook, kernel-janitors, Tejun Heo, linux-ide,
linux-kernel@vger.kernel.org
In-Reply-To: <1500149266-32357-9-git-send-email-Julia.Lawall@lip6.fr>
On Sat, Jul 15, 2017 at 10:07 PM, Julia Lawall <Julia.Lawall@lip6.fr> wrote:
> Drop static on a local variable, when the variable is initialized before
> any possible use. Thus, the static has no benefit.
>
> The semantic patch that fixes this problem is as follows:
> (http://coccinelle.lip6.fr/)
>
> // <smpl>
> @bad exists@
> position p;
> identifier x;
> type T;
> @@
> static T x@p;
> ...
> x = <+...x...+>
>
> @@
> identifier x;
> expression e;
> type T;
> position p != bad.p;
> @@
> -static
> T x@p;
> ... when != x
> when strict
> ?x = e;
> // </smpl>
>
> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: Extremely important and Urgent
From: Singer Valve @ 2017-08-02 3:46 UTC (permalink / raw)
To: Recipients
I am getting in touch with you regarding an extremely important and urgent matter.
If you would oblige me the opportunity, I shall provide you with details upon your response.
Faithfully,
Ms. Singer Valve
^ permalink raw reply
* [PATCH v1 2/2] dt-bindings: ata: add DT bindings for MediaTek SATA controller
From: Ryder Lee @ 2017-08-01 7:33 UTC (permalink / raw)
To: Hans de Goede, Tejun Heo
Cc: Rob Herring, devicetree, linux-mediatek, linux-kernel, linux-ide,
Long Cheng, Ryder Lee
In-Reply-To: <cover.1501381975.git.ryder.lee@mediatek.com>
Add DT bindings for the onboard SATA controller present on the MediaTek
SoCs.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
Documentation/devicetree/bindings/ata/ahci-mtk.txt | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt
diff --git a/Documentation/devicetree/bindings/ata/ahci-mtk.txt b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
new file mode 100644
index 0000000..8f64f15
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
@@ -0,0 +1,50 @@
+MediaTek Seria ATA controller
+
+Required properties:
+ - compatible : Must be "mediatek,ahci".
+ - reg : Physical base addresses and length of register sets.
+ - interrupts : Interrupt associated with the SATA device.
+ - interrupt-names : Associated name must be: "hostc".
+ - clocks : A list of phandle and clock specifier pairs, one for each
+ entry in clock-names.
+ - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
+ - phys : A phandle and PHY specifier pair for the PHY port.
+ - phy-names : Associated name must be: "sata-phy".
+ - ports-implemented : Mask that indicates which ports that the HBA supports
+ are available for software to use. Useful if PORTS_IMPL
+ is not programmed by the BIOS, which is true with some
+ embedded SOC's.
+
+Optional properties:
+ - power-domains : A phandle and power domain specifier pair to the power
+ domain which is responsible for collapsing and restoring
+ power to the peripheral.
+ - resets : Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+ - reset-names : Associated names must be: "axi-rst", "sw-rst", "reg-rst".
+ - mediatek,phy-mode : A phandle to the system controller, used to enable
+ SATA function.
+
+Example:
+
+ sata: sata@1a200000 {
+ compatible = "mediatek,ahci";
+ reg = <0 0x1a200000 0 0x1100>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ clocks = <&pciesys CLK_SATA_AHB_EN>,
+ <&pciesys CLK_SATA_AXI_EN>,
+ <&pciesys CLK_SATA_ASIC_EN>,
+ <&pciesys CLK_SATA_RBC_EN>,
+ <&pciesys CLK_SATA_PM_EN>;
+ clock-names = "ahb", "axi", "asic", "rbc", "pm";
+ phys = <&u3port1 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+ <&pciesys MT7622_SATA_PHY_SW_RST>,
+ <&pciesys MT7622_SATA_PHY_REG_RST>;
+ reset-names = "axi-rst", "sw-rst", "reg-rst";
+ mediatek,phy-mode = <&pciesys>;
+ };
--
1.9.1
^ permalink raw reply related
* [PATCH v1 1/2] ata: mediatek: add support for MediaTek SATA controller
From: Ryder Lee @ 2017-08-01 7:33 UTC (permalink / raw)
To: Hans de Goede, Tejun Heo
Cc: Rob Herring, devicetree, linux-mediatek, linux-kernel, linux-ide,
Long Cheng, Ryder Lee
In-Reply-To: <cover.1501381975.git.ryder.lee@mediatek.com>
This adds support the AHCI-compliant Serial ATA controller present
on MediaTek SoCs.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
drivers/ata/Kconfig | 10 +++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_mtk.c | 196 +++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 207 insertions(+)
create mode 100644 drivers/ata/ahci_mtk.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 948fc86..7d3eb47 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -153,6 +153,16 @@ config AHCI_CEVA
If unsure, say N.
+config AHCI_MTK
+ tristate "MediaTek AHCI SATA support"
+ depends on ARCH_MEDIATEK
+ select MFD_SYSCON
+ help
+ This option enables support for the MediaTek SoC's
+ onboard AHCI SATA controller.
+
+ If unsure, say N.
+
config AHCI_MVEBU
tristate "Marvell EBU AHCI SATA support"
depends on ARCH_MVEBU
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index a26ef5a..ff9cd2e 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DM816) += ahci_dm816.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_MTK) += ahci_mtk.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_OCTEON) += ahci_octeon.o
obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_mtk.c b/drivers/ata/ahci_mtk.c
new file mode 100644
index 0000000..6361316
--- /dev/null
+++ b/drivers/ata/ahci_mtk.c
@@ -0,0 +1,196 @@
+/*
+ * MeidaTek AHCI SATA driver
+ *
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/ahci_platform.h>
+#include <linux/kernel.h>
+#include <linux/libata.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include "ahci.h"
+
+#define DRV_NAME "ahci"
+
+#define SYS_CFG 0x14
+#define SYS_CFG_SATA_MSK GENMASK(31, 30)
+#define SYS_CFG_SATA_EN BIT(31)
+
+struct mtk_ahci_drv_data {
+ struct regmap *mode;
+ struct reset_control *axi_rst;
+ struct reset_control *sw_rst;
+ struct reset_control *reg_rst;
+};
+
+static const struct ata_port_info ahci_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &ahci_platform_ops,
+};
+
+static struct scsi_host_template ahci_platform_sht = {
+ AHCI_SHT(DRV_NAME),
+};
+
+static int mtk_ahci_platform_resets(struct ahci_host_priv *hpriv,
+ struct device *dev)
+{
+ struct mtk_ahci_drv_data *drv_data = hpriv->plat_data;
+ int err;
+
+ /* reset AXI bus and phy part */
+ drv_data->axi_rst = devm_reset_control_get_optional(dev, "axi-rst");
+ if (PTR_ERR(drv_data->axi_rst) == -EPROBE_DEFER)
+ return PTR_ERR(drv_data->axi_rst);
+
+ drv_data->sw_rst = devm_reset_control_get_optional(dev, "sw-rst");
+ if (PTR_ERR(drv_data->sw_rst) == -EPROBE_DEFER)
+ return PTR_ERR(drv_data->sw_rst);
+
+ drv_data->reg_rst = devm_reset_control_get_optional(dev, "reg-rst");
+ if (PTR_ERR(drv_data->reg_rst) == -EPROBE_DEFER)
+ return PTR_ERR(drv_data->reg_rst);
+
+ err = reset_control_assert(drv_data->axi_rst);
+ if (err) {
+ dev_err(dev, "assert axi bus failed\n");
+ return err;
+ }
+
+ err = reset_control_assert(drv_data->sw_rst);
+ if (err) {
+ dev_err(dev, "assert phy digital part failed\n");
+ return err;
+ }
+
+ err = reset_control_assert(drv_data->reg_rst);
+ if (err) {
+ dev_err(dev, "assert phy register part failed\n");
+ return err;
+ }
+
+ err = reset_control_deassert(drv_data->reg_rst);
+ if (err) {
+ dev_err(dev, "deassert phy register part failed\n");
+ return err;
+ }
+
+ err = reset_control_deassert(drv_data->sw_rst);
+ if (err) {
+ dev_err(dev, "deassert phy digital part failed\n");
+ return err;
+ }
+
+ err = reset_control_deassert(drv_data->axi_rst);
+ if (err) {
+ dev_err(dev, "deassert axi bus failed\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv,
+ struct device *dev)
+{
+ struct mtk_ahci_drv_data *drv_data = hpriv->plat_data;
+ struct device_node *np = dev->of_node;
+
+ /* enable SATA function if needed */
+ if (of_find_property(np, "mediatek,phy-mode", NULL)) {
+ drv_data->mode = syscon_regmap_lookup_by_phandle(
+ np, "mediatek,phy-mode");
+ if (IS_ERR(drv_data->mode)) {
+ dev_err(dev, "missing phy-mode phandle\n");
+ return PTR_ERR(drv_data->mode);
+ }
+
+ regmap_update_bits(drv_data->mode, SYS_CFG, SYS_CFG_SATA_MSK,
+ SYS_CFG_SATA_EN);
+ }
+
+ of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map);
+
+ return 0;
+}
+
+static int mtk_ahci_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ahci_drv_data *drv_data;
+ struct ahci_host_priv *hpriv;
+ int err;
+
+ drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
+ if (!drv_data)
+ return -ENOMEM;
+
+ hpriv = ahci_platform_get_resources(pdev);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
+
+ hpriv->plat_data = drv_data;
+
+ err = mtk_ahci_parse_property(hpriv, dev);
+ if (err)
+ return err;
+
+ err = mtk_ahci_platform_resets(hpriv, dev);
+ if (err)
+ return err;
+
+ err = ahci_platform_enable_resources(hpriv);
+ if (err)
+ return err;
+
+ err = ahci_platform_init_host(pdev, hpriv, &ahci_port_info,
+ &ahci_platform_sht);
+ if (err)
+ goto disable_resources;
+
+ return 0;
+
+disable_resources:
+ ahci_platform_disable_resources(hpriv);
+ return err;
+}
+
+static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
+ ahci_platform_resume);
+
+static const struct of_device_id ahci_of_match[] = {
+ { .compatible = "mediatek,ahci", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ahci_of_match);
+
+static struct platform_driver mtk_ahci_driver = {
+ .probe = mtk_ahci_probe,
+ .remove = ata_platform_remove_one,
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = ahci_of_match,
+ .pm = &ahci_pm_ops,
+ },
+};
+module_platform_driver(mtk_ahci_driver);
+
+MODULE_DESCRIPTION("MeidaTek SATA AHCI Driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1
^ permalink raw reply related
* [PATCH v1 0/2] Add support for MediaTek AHCI SATA
From: Ryder Lee @ 2017-08-01 7:33 UTC (permalink / raw)
To: Hans de Goede, Tejun Heo
Cc: Rob Herring, devicetree, linux-mediatek, linux-kernel, linux-ide,
Long Cheng, Ryder Lee
Hi,
This patch series add support for AHCI compatible SATA controller, and it is
compliant with the ahci 1.3 and sata 3.0 specification. This driver is slightly
different than ahci_platform.c (e.g., reset control, subsystem setting).
changes since v1:
- update binding text: add missing "specifier pairs" descriptions.
- fix kbuild test warning: fix the error handling.
Ryder Lee (2):
ata: mediatek: add support for MediaTek SATA controller
dt-bindings: ata: add DT bindings for MediaTek SATA controller
Documentation/devicetree/bindings/ata/ahci-mtk.txt | 50 ++++++
drivers/ata/Kconfig | 10 ++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_mtk.c | 196 +++++++++++++++++++++
4 files changed, 257 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt
create mode 100644 drivers/ata/ahci_mtk.c
--
1.9.1
^ permalink raw reply
* [PATCH v2 tip/core/rcu 08/10] drivers/ata: Replace spin_unlock_wait() with lock/unlock pair
From: Paul E. McKenney @ 2017-07-31 22:58 UTC (permalink / raw)
To: linux-kernel
Cc: mingo, jiangshanlai, dipankar, akpm, mathieu.desnoyers, josh,
tglx, peterz, rostedt, dhowells, edumazet, fweisbec, oleg,
Paul E. McKenney, linux-ide, Will Deacon, Alan Stern,
Andrea Parri, Linus Torvalds
In-Reply-To: <20170731225754.GB2674@linux.vnet.ibm.com>
There is no agreed-upon definition of spin_unlock_wait()'s semantics,
and it appears that all callers could do just as well with a lock/unlock
pair. This commit therefore eliminates the spin_unlock_wait() call and
associated else-clause and hoists the then-clause's lock and unlock out of
the "if" statement. This should be safe from a performance perspective
because according to Tejun there should be few if any drivers that don't
set their own error handler.
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: Tejun Heo <tj@kernel.org>
Cc: <linux-ide@vger.kernel.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Andrea Parri <parri.andrea@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
---
drivers/ata/libata-eh.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index b70bcf6d2914..b325db27eb8c 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -645,12 +645,11 @@ void ata_scsi_cmd_error_handler(struct Scsi_Host *host, struct ata_port *ap,
* completions are honored. A scmd is determined to have
* timed out iff its associated qc is active and not failed.
*/
+ spin_lock_irqsave(ap->lock, flags);
if (ap->ops->error_handler) {
struct scsi_cmnd *scmd, *tmp;
int nr_timedout = 0;
- spin_lock_irqsave(ap->lock, flags);
-
/* This must occur under the ap->lock as we don't want
a polled recovery to race the real interrupt handler
@@ -700,12 +699,11 @@ void ata_scsi_cmd_error_handler(struct Scsi_Host *host, struct ata_port *ap,
if (nr_timedout)
__ata_port_freeze(ap);
- spin_unlock_irqrestore(ap->lock, flags);
/* initialize eh_tries */
ap->eh_tries = ATA_EH_MAX_TRIES;
- } else
- spin_unlock_wait(ap->lock);
+ }
+ spin_unlock_irqrestore(ap->lock, flags);
}
EXPORT_SYMBOL(ata_scsi_cmd_error_handler);
--
2.5.2
^ permalink raw reply related
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